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-rw-r--r--ChangeLog5
-rw-r--r--gcc/config/rs6000/rs6000.c18
-rw-r--r--gcc/testsuite/ChangeLog10
-rw-r--r--gcc/testsuite/gcc.target/powerpc/fold-vec-sub-char.c46
-rw-r--r--gcc/testsuite/gcc.target/powerpc/fold-vec-sub-float.c17
-rw-r--r--gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c23
-rw-r--r--gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int.c47
-rw-r--r--gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c24
-rw-r--r--gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c47
-rw-r--r--gcc/testsuite/gcc.target/powerpc/fold-vec-sub-short.c47
10 files changed, 284 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog
index c97158a9699..b3dfcd9387b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for
+ early expansion of vector subtract builtins.
+
2016-12-19 Chenghua Xu <paul.hua.gm@gmail.com>
* MAINTAINERS (Write After Approval): Add myself.
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7076ca16a4f..1f02d1442d3 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16564,6 +16564,24 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
gsi_replace (gsi, g, true);
return true;
}
+ /* Flavors of vec_sub. We deliberately don't expand
+ P8V_BUILTIN_VSUBUQM. */
+ case ALTIVEC_BUILTIN_VSUBUBM:
+ case ALTIVEC_BUILTIN_VSUBUHM:
+ case ALTIVEC_BUILTIN_VSUBUWM:
+ case P8V_BUILTIN_VSUBUDM:
+ case ALTIVEC_BUILTIN_VSUBFP:
+ case VSX_BUILTIN_XVSUBDP:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+
default:
break;
}
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 53813b5ab24..a3eea070b5a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2016-12-19 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * gcc.target/powerpc/fold-vec-sub-char.c: New.
+ * gcc.target/powerpc/fold-vec-sub-float.c: New.
+ * gcc.target/powerpc/fold-vec-sub-floatdouble.c: New.
+ * gcc.target/powerpc/fold-vec-sub-int.c: New.
+ * gcc.target/powerpc/fold-vec-sub-int128.c: New.
+ * gcc.target/powerpc/fold-vec-sub-longlong.c: New.
+ * gcc.target/powerpc/fold-vec-sub-short.c: New.
+
2016-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com>
PR target/78748
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-char.c
new file mode 100644
index 00000000000..5063bd8cb10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-char.c
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_sub with char
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed char
+test1 (vector bool char x, vector signed char y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed char
+test2 (vector signed char x, vector bool char y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed char
+test3 (vector signed char x, vector signed char y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned char
+test4 (vector bool char x, vector unsigned char y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned char
+test5 (vector unsigned char x, vector bool char y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned char
+test6 (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sub (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsububm" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-float.c
new file mode 100644
index 00000000000..8a29def8cc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-float.c
@@ -0,0 +1,17 @@
+/* Verify that overloaded built-ins for vec_sub with float
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+ return vec_sub (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsubfp" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c
new file mode 100644
index 00000000000..c29acc93b56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-floatdouble.c
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_sub with float and
+ double inputs for VSX produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec -mvsx" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+ return vec_sub (x, y);
+}
+
+vector double
+test2 (vector double x, vector double y)
+{
+ return vec_sub (x, y);
+}
+
+/* { dg-final { scan-assembler-times "xvsubsp" 1 } } */
+/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int.c
new file mode 100644
index 00000000000..1fac1dc0eeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int.c
@@ -0,0 +1,47 @@
+/* Verify that overloaded built-ins for vec_sub with int
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector bool int x, vector signed int y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed int
+test2 (vector signed int x, vector bool int y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed int
+test3 (vector signed int x, vector signed int y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned int
+test4 (vector bool int x, vector unsigned int y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned int
+test5 (vector unsigned int x, vector bool int y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned int
+test6 (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sub (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsubuwm" 6 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c
new file mode 100644
index 00000000000..13caa9e6455
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c
@@ -0,0 +1,24 @@
+/* Verify that overloaded built-ins for vec_sub with __int128
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
+
+#include "altivec.h"
+
+vector signed __int128
+test1 (vector signed __int128 x, vector signed __int128 y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned __int128
+test2 (vector unsigned __int128 x, vector unsigned __int128 y)
+{
+ return vec_sub (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsubuqm" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c
new file mode 100644
index 00000000000..889fba4b2aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c
@@ -0,0 +1,47 @@
+/* Verify that overloaded built-ins for vec_sub with long long
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+
+#include <altivec.h>
+
+vector signed long long
+test1 (vector bool long long x, vector signed long long y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed long long
+test2 (vector signed long long x, vector bool long long y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed long long
+test3 (vector signed long long x, vector signed long long y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned long long
+test4 (vector bool long long x, vector unsigned long long y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned long long
+test5 (vector unsigned long long x, vector bool long long y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned long long
+test6 (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sub (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsubudm" 6 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-short.c
new file mode 100644
index 00000000000..67052a2474d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-short.c
@@ -0,0 +1,47 @@
+/* Verify that overloaded built-ins for vec_sub with short
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed short
+test1 (vector bool short x, vector signed short y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed short
+test2 (vector signed short x, vector bool short y)
+{
+ return vec_sub (x, y);
+}
+
+vector signed short
+test3 (vector signed short x, vector signed short y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned short
+test4 (vector bool short x, vector unsigned short y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned short
+test5 (vector unsigned short x, vector bool short y)
+{
+ return vec_sub (x, y);
+}
+
+vector unsigned short
+test6 (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sub (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsubuhm" 6 } } */
+
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