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-rw-r--r--gcc/config/riscv/bitmanip.md9
-rw-r--r--gcc/config/riscv/thead.md4
2 files changed, 7 insertions, 6 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index ccda25c01c1..ad3ad758959 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -50,11 +50,11 @@
(sign_extend:DI (div:SI (plus:SI (ashift:SI (subreg:SI (match_operand:DI 1 "register_operand") 0)
(match_operand:QI 2 "imm123_operand"))
(subreg:SI (match_operand:DI 3 "register_operand") 0))
- (subreg:SI (match_operand:DI 4 "register_operand") 0))))
+ (match_operand:SI 4 "register_operand"))))
(clobber (match_operand:DI 5 "register_operand"))]
"TARGET_64BIT && TARGET_ZBA"
[(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (subreg:SI (match_dup 4) 0))))])
+ (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (match_dup 4))))])
; Zba does not provide W-forms of sh[123]add(.uw)?, which leads to an
; interesting irregularity: we can generate a signed 32-bit result
@@ -722,13 +722,14 @@
(define_split
[(set (match_operand:X 0 "register_operand")
(and:X (not:X (lshiftrt:X (match_operand:X 1 "register_operand")
- (subreg:QI (match_operand:X 2 "register_operand") 0)))
+ (match_operand:QI 2 "register_operand")))
(const_int 1)))]
"TARGET_ZBS"
[(set (match_dup 0) (zero_extract:X (match_dup 1)
(const_int 1)
(match_dup 2)))
- (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))])
+ (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]
+ "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 })
;; using a bext(i) followed by an addi instruction.
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 5c7d4beb1b6..a47fe6f28b8 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -466,12 +466,12 @@
(define_insn_and_split "*th_memidx_operand"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI
- (zero_extend:DI (subreg:SI (match_operand:DI 1 "register_operand" "r") 0))
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
(match_operand 2 "const_int_operand" "n")))]
"TARGET_64BIT && TARGET_XTHEADMEMIDX && lra_in_progress"
"#"
""
- [(set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 1) 0)))
+ [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
""
[(set_attr "type" "bitmanip")])