diff options
| -rw-r--r-- | ChangeLog | 4 | ||||
| -rw-r--r-- | contrib/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/ChangeLog | 135 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/analyzer/ChangeLog | 26 | ||||
| -rw-r--r-- | gcc/cp/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/jit/ChangeLog | 16 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 106 |
8 files changed, 300 insertions, 1 deletions
diff --git a/ChangeLog b/ChangeLog index c5ab5b88a24..0b836353a03 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,7 @@ +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * MAINTAINERS: Add myself. + 2023-08-22 Filip Kastl <fkastl@suse.cz> * MAINTAINERS: Update my email address. diff --git a/contrib/ChangeLog b/contrib/ChangeLog index fdc044ac001..105726c39d3 100644 --- a/contrib/ChangeLog +++ b/contrib/ChangeLog @@ -1,3 +1,7 @@ +2023-08-29 Lehua Ding <lehua.ding@rivai.ai> + + * mklog.py: Fix bugs. + 2023-08-16 Andrew Pinski <apinski@marvell.com> * gcc_update: Add libstdc++-v3/include/bits/version.h. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1ed4e3a8149..68fff3560f3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,138 @@ +2023-08-29 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/zicond.md: New splitters to rewrite single bit + sign extension as the condition to a czero in the desired form. + +2023-08-29 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/99860 + * doc/invoke.texi: Add -Wanalyzer-overlapping-buffers. + +2023-08-29 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/99860 + * Makefile.in (ANALYZER_OBJS): Add analyzer/ranges.o. + +2023-08-29 Jin Ma <jinma@linux.alibaba.com> + + * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): + zvfh can generate zfa extended instruction fli.h, just like zfh. + +2023-08-29 Edwin Lu <ewlu@rivosinc.com> + Vineet Gupta <vineetg@rivosinc.com> + + * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Generate + __riscv_unaligned_avoid with value 1 or + __riscv_unaligned_slow with value 1 or + __riscv_unaligned_fast with value 1 + * config/riscv/riscv.cc (riscv_option_override): Define + riscv_user_wants_strict_align. Set + riscv_user_wants_strict_align to TARGET_STRICT_ALIGN + * config/riscv/riscv.h: Declare riscv_user_wants_strict_align + +2023-08-29 Edwin Lu <ewlu@rivosinc.com> + + * config/riscv/autovec-vls.md: Update types + * config/riscv/riscv.md: Add vector placeholder type + * config/riscv/vector.md: Update types + +2023-08-29 Carl Love <cel@us.ibm.com> + + * config/rs6000/dfp.md (UNSPEC_DQUAN): New unspec. + (dfp_dqua_<mode>, dfp_dquai_<mode>): New define_insn. + * config/rs6000/rs6000-builtins.def (__builtin_dfp_dqua, + __builtin_dfp_dquai, __builtin_dfp_dquaq, __builtin_dfp_dquaqi): + New buit-in definitions. + * config/rs6000/rs6000-overload.def (__builtin_dfp_quantize): New + overloaded definition. + * doc/extend.texi: Add documentation for __builtin_dfp_quantize. + +2023-08-29 Pan Li <pan2.li@intel.com> + Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.cc (riscv_legitimize_poly_move): New declaration. + (riscv_legitimize_const_move): Handle ref plus const poly. + +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * common/config/riscv/riscv-common.cc + (riscv_implied_info): Add implications from unprivileged extensions. + (riscv_ext_version_table): Add stub support for all unprivileged + extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'. + +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * common/config/riscv/riscv-common.cc (riscv_ext_version_table): + Add stub support for all vendor extensions supported by Binutils. + +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * common/config/riscv/riscv-common.cc + (riscv_implied_info): Add implications from privileged extensions. + (riscv_ext_version_table): Add stub support for all privileged + extensions supported by Binutils. + +2023-08-29 Lehua Ding <lehua.ding@rivai.ai> + + * config/riscv/autovec.md: Adjust + * config/riscv/riscv-protos.h (RVV_VUNDEF): Clean. + (get_vlmax_rtx): Exported. + * config/riscv/riscv-v.cc (emit_nonvlmax_fp_ternary_tu_insn): Deleted. + (emit_vlmax_masked_gather_mu_insn): Adjust. + (get_vlmax_rtx): New func. + (expand_load_store): Adjust. + (expand_cond_len_unop): Call expand_cond_len_op. + (expand_cond_len_op): New subroutine. + (expand_cond_len_binop): Call expand_cond_len_op. + (expand_cond_len_ternop): Call expand_cond_len_op. + (expand_lanes_load_store): Adjust. + +2023-08-29 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/79173 + PR middle-end/111209 + * tree-ssa-math-opts.cc (match_uaddc_usubc): Match also + just 2 limb uaddc/usubc with 0 carry-in on lower limb and ignored + carry-out on higher limb. Don't match it though if it could be + matched later on 4 argument addition/subtraction. + +2023-08-29 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/111147 + * match.pd (`(x | y) & (~x ^ y)`) Use bitwise_inverted_equal_p + instead of matching bit_not. + +2023-08-29 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm-mve-builtins.cc (type_suffixes): Add missing + initializer. + +2023-08-29 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc (vector_insn_info::get_avl_or_vl_reg): New function. + (pass_vsetvl::compute_local_properties): Fix bug. + (pass_vsetvl::commit_vsetvls): Ditto. + * config/riscv/riscv-vsetvl.h: New function. + +2023-08-29 Lehua Ding <lehua.ding@rivai.ai> + + PR target/110943 + * config/riscv/predicates.md (vector_const_int_or_double_0_operand): + New predicate. + * config/riscv/riscv-vector-builtins.cc (function_expander::function_expander): + force_reg mem target operand. + * config/riscv/vector.md (@pred_mov<mode>): Wrapper. + (*pred_mov<mode>): Remove imm -> reg pattern. + (*pred_broadcast<mode>_imm): Add imm -> reg pattern. + +2023-08-29 Lulu Cheng <chenglulu@loongson.cn> + + * common/config/loongarch/loongarch-common.cc: + Enable '-free' on O2 and above. + * doc/invoke.texi: Modify the description information + of the '-free' compilation option and add the LoongArch + description. + 2023-08-28 Tsukasa OI <research_trasio@irq.a4lg.com> * doc/extend.texi: Fix the description of __builtin_riscv_pause. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index fa3e264536d..0e0e43a0354 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20230829 +20230830 diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index b4eb0fce35b..bd9a766f8c0 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,29 @@ +2023-08-29 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/99860 + * analyzer-selftests.cc (selftest::run_analyzer_selftests): Call + selftest::analyzer_ranges_cc_tests. + * analyzer-selftests.h (selftest::run_analyzer_selftests): New + decl. + * analyzer.opt (Wanalyzer-overlapping-buffers): New option. + * call-details.cc: Include "analyzer/ranges.h" and "make-unique.h". + (class overlapping_buffers): New. + (call_details::complain_about_overlap): New. + * call-details.h (call_details::complain_about_overlap): New decl. + * kf.cc (kf_memcpy_memmove::impl_call_pre): Call + cd.complain_about_overlap for memcpy and memcpy_chk. + (kf_strcat::impl_call_pre): Call cd.complain_about_overlap. + (kf_strcpy::impl_call_pre): Likewise. + * ranges.cc: New file. + * ranges.h: New file. + +2023-08-29 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/105899 + * kf.cc (kf_strdup::impl_call_pre): Set size of + dynamically-allocated buffer. Simulate copying the string from + the source region to the new buffer. + 2023-08-27 benjamin priour <vultkayn@gcc.gnu.org> PR analyzer/96395 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ec1f462f8fa..ece1bf90afa 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,11 @@ +2023-08-29 Marek Polacek <polacek@redhat.com> + + * call.cc (convert_like_internal): Show where the conversion function + was declared. + (maybe_show_nonconverting_candidate): New. + * cp-tree.h (maybe_show_nonconverting_candidate): Declare. + * typeck.cc (convert_for_assignment): Call it. + 2023-08-25 Sandra Loosemore <sandra@codesourcery.com> * cp-tree.h (cp_convert_omp_range_for): Adjust declaration. diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog index 4c30cab1db8..38e71c98df2 100644 --- a/gcc/jit/ChangeLog +++ b/gcc/jit/ChangeLog @@ -1,3 +1,19 @@ +2023-08-29 Guillaume Gomez <guillaume1.gomez@gmail.com> + + * docs/topics/compatibility.rst: Add documentation for LIBGCCJIT_ABI_25. + * docs/topics/types.rst: Add documentation for gcc_jit_type_get_restrict. + +2023-08-29 Guillaume Gomez <guillaume1.gomez@gmail.com> + + * jit-playback.cc: Remove trailing whitespace characters. + * jit-playback.h: Add get_restrict method. + * jit-recording.cc: Add get_restrict methods. + * jit-recording.h: Add get_restrict methods. + * libgccjit++.h: Add get_restrict methods. + * libgccjit.cc: Add gcc_jit_type_get_restrict. + * libgccjit.h: Declare gcc_jit_type_get_restrict. + * libgccjit.map: Declare gcc_jit_type_get_restrict. + 2023-02-16 Patrick Palka <ppalka@redhat.com> * jit-dejagnu.h: Mechanically drop static from static inline diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4705152c8ad..c7db53a02b4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,109 @@ +2023-08-29 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * gcc.target/riscv/zicond-xor-01.c: New test. + Co-authored-by: Jeff Law <jlaw@ventanamicro.com> + +2023-08-29 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/99860 + * c-c++-common/analyzer/overlapping-buffers.c: New test. + +2023-08-29 Marek Polacek <polacek@redhat.com> + + * g++.dg/diagnostic/explicit.C: New test. + +2023-08-29 Jin Ma <jinma@linux.alibaba.com> + + * gcc.target/riscv/zfa-fli-7.c: Change fa0 to fa\[0-9\] to avoid + assigning register numbers that are non-zero. + * gcc.target/riscv/zfa-fli-8.c: Ditto. + * gcc.target/riscv/zfa-fli-5.c: New test. + +2023-08-29 Edwin Lu <ewlu@rivosinc.com> + Vineet Gupta <vineetg@rivosinc.com> + + * gcc.target/riscv/attribute-1.c: Check for + __riscv_unaligned_slow or __riscv_unaligned_fast + * gcc.target/riscv/attribute-4.c: Check for + __riscv_unaligned_avoid + * gcc.target/riscv/attribute-5.c: Check for + __riscv_unaligned_slow or __riscv_unaligned_fast + * gcc.target/riscv/predef-align-1.c: New test. + * gcc.target/riscv/predef-align-2.c: New test. + * gcc.target/riscv/predef-align-3.c: New test. + * gcc.target/riscv/predef-align-4.c: New test. + * gcc.target/riscv/predef-align-5.c: New test. + * gcc.target/riscv/predef-align-6.c: New test. + +2023-08-29 Guillaume Gomez <guillaume1.gomez@gmail.com> + + * jit.dg/test-restrict.c: Add test for __restrict__ attribute. + * jit.dg/all-non-failing-tests.h: Add test-restrict.c to the list. + +2023-08-29 Carl Love <cel@us.ibm.com> + + PR target/93448 + * gcc.target/powerpc/pr93448.c: New test case. + +2023-08-29 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/105899 + * c-c++-common/analyzer/pr99193-2.c: Add + -Wno-analyzer-too-complex. + * gcc.dg/analyzer/strdup-1.c: Include "analyzer-decls.h". + (test_concrete_strlen): New. + (test_symbolic_strlen): New. + +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * gcc.target/riscv/predef-31.c: New test for a stub unprivileged + extension 'Zcb' with some implications. + +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * gcc.target/riscv/predef-30.c: New test for a stub + vendor extension 'XVentanaCondOps'. + +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * gcc.target/riscv/predef-29.c: New test for a stub privileged + extension 'Smstateen' with some implications. + +2023-08-29 Tsukasa OI <research_trasio@irq.a4lg.com> + + * gcc.target/riscv/pr102957-2.c: New test case using the 'Zk' + extension to continue testing whether we can use valid two-letter + extensions. + +2023-08-29 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/79173 + PR middle-end/111209 + * gcc.target/i386/pr79173-12.c: New test. + +2023-08-29 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/111147 + * gcc.dg/tree-ssa/cmpbit-4.c: New test. + +2023-08-29 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.dg/vect/no-scevccp-outer-12.c: Add riscv xfail. + +2023-08-29 Juzhe-Zhong <juzhe.zhong@rivai.ai> + + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Fix ASM check. + +2023-08-29 Lehua Ding <lehua.ding@rivai.ai> + + PR target/110943 + * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Adjust. + * gcc.target/riscv/rvv/base/pr110943.c: New test. + +2023-08-29 Lulu Cheng <chenglulu@loongson.cn> + + * gcc.target/loongarch/sign-extend.c: New test. + 2023-08-28 Tsukasa OI <research_trasio@irq.a4lg.com> * gcc.target/riscv/builtin_pause.c: Removed. |