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2017-04-12 gcc/linaro-local/snapshots/linaro-6.3-2017.04Yvan Roux
* LINARO-VERSION: Bump version number, post snapshot. Change-Id: I03f5eba595dfb4b91d28512b6029b9906e6450ce
2017-04-12Make Linaro GCC Snapshot 6.3-2017.04.linaro-snapshot-6.3-2017.04Yvan Roux
gcc/ * LINARO-VERSION: Update. Change-Id: Ie7b5231e142364ed0b1678b148f2c2987bcf26a9
2017-04-11 gcc/Christophe Lyon
Backport from trunk r246760. 2017-04-07 Martin Liska <mliska@suse.cz> PR target/79889 * config/aarch64/aarch64.c (aarch64_process_target_attr): Show error message instead of an ICE. gcc/testsuite/ Backport from trunk r246760. 2017-04-07 Martin Liska <mliska@suse.cz> PR target/79889 * g++.dg/ext/mv8.C: Add aarch64* targets. Change-Id: I916f151b8a955c39d56b34a71605a2e6aef8861d
2017-04-07 gcc/Christophe Lyon
Backport from trunk r246682. 2017-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com> PR target/80307 * config/arm/arm.c (thumb1_rtx_costs): Give a cost of 32 instructions for small multiply cores. gcc/testsuite/ Backport from trunk r246682. 2017-04-04 Thomas Preud'homme <thomas.preudhomme@arm.com> PR target/80307 * gcc.target/arm/small-multiply-m0-1.c: Do not skip test if not targeting any CPU or architecture. * gcc.target/arm/small-multiply-m0-2.c: Likewise. * gcc.target/arm/small-multiply-m0-3.c: Likewise. * gcc.target/arm/small-multiply-m0plus-1.c: Likewise. * gcc.target/arm/small-multiply-m0plus-2.c: Likewise. * gcc.target/arm/small-multiply-m0plus-3.c: Likewise. * gcc.target/arm/small-multiply-m1-1.c: Likewise. * gcc.target/arm/small-multiply-m1-2.c: Likewise. * gcc.target/arm/small-multiply-m1-3.c: Likewise. Change-Id: I6916d48a0f747ff2efe0b907a966e5b7638c1c85
2017-04-04Merge branches/gcc-6-branch rev 246668.Yvan Roux
Change-Id: If1d4497c52a1bdde1390c2377e3f2c16ac2e73b4
2017-04-04 gcc/Yvan Roux
Backport from trunk r245999. 2017-03-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/79913 * config/aarch64/iterators.md (VALL_F16_NO_V2Q): New mode iterator. (VALL_NO_V2Q): Likewise. (VDQF_DF): Delete. * config/aarch64/aarch64-simd.md (aarch64_dup_lane_<vswap_width_name><mode>): Use VALL_F16_NO_V2Q iterator. (*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Use VALL_NO_V2Q mode iterator. (*aarch64_vgetfmulx<mode>): Use VDQF iterator. Change-Id: I12c0bae589b5d9e280e3e86f2b07bb5cf146220c
2017-04-04 gcc/Christophe Lyon
Backport from trunk r246189. 2017-03-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF. * config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup<mode>): Use h_con constraint for operand 1. (*aarch64_fnma4_elt_from_dup<mode>): Likewise. (*aarch64_mulx_elt_from_dup<mode>): Likewise for operand 2. Change-Id: Iaa454b2f6b56fea65515242a8546e639d6ea8021
2017-04-04 gcc/Yvan Roux
Backport from trunk r246084. 2017-03-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/79911 * config/arm/neon.md (vec_sel_widen_ssum_lo<VQI:mode><VW:mode>3): Rename to... (vec_sel_widen_ssum_lo<mode><V_half>3): ... This. Avoid mismatch between vec_select and vector argument. (vec_sel_widen_ssum_hi<VQI:mode><VW:mode>3): Rename to... (vec_sel_widen_ssum_hi<mode><V_half>3): ... This. Likewise. (vec_sel_widen_usum_lo<VQI:mode><VW:mode>3): Rename to... (vec_sel_widen_usum_lo<mode><V_half>3): ... This. (vec_sel_widen_usum_hi<VQI:mode><VW:mode>3): Rename to... (vec_sel_widen_usum_hi<mode><V_half>3): ... This. Change-Id: Idaaaf2fd6b511795ef6081f65777638115fc6eea
2017-04-04 gcc/Christophe Lyon
Backport from trunk r246419. 2017-03-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/71436 * config/arm/arm.md (*load_multiple): Add reload_completed to matching condition. gcc/testsuite/ Backport from trunk r246419. 2017-03-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/71436 * gcc.c-torture/compile/pr71436.c: New test. Change-Id: Ia02c434b2f33a91344a496e3ae83fa932ed3e963
2017-04-04 gcc/Christophe Lyon
Backport from trunk r246397. 2017-03-22 Wilco Dijkstra <wdijkstr@arm.com> * config/aarch64/aarch64.c (generic_branch_cost): Copycortexa57_branch_cost. Change-Id: I98bec5f8c773bfbcf289b906c8087f932847dfb7
2017-04-04 gcc/Christophe Lyon
Backport from trunk r246395. 2017-03-22 Wilco Dijkstra <wdijkstr@arm.com> * config/aarch64/aarch64.c (generic_tunings): Add AES fusion. Change-Id: If55fc9c24b4378a7e7f3aa02452659e7ca4c6588
2017-04-04 gcc/Christophe Lyon
Backport from trunk r246229. 2017-03-17 Richard Earnshaw <rearnsha@arm.com> PR target/80052 * aarch64.opt(verbose-cost-dump): Fix typo. Change-Id: I8afafcbaa5ef0269c5b70bb1563b61f5eb150994
2017-04-04 gcc/Christophe Lyon
Backport from trunk r246190. 2017-03-16 Tamar Christina <tamar.christina@arm.com> * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>) Change ins into fmov. Change-Id: Ic9df76107e902ef9847dff53743c331e67921545
2017-04-04 gcc/Christophe Lyon
Backport from trunk r245029. 2017-01-30 Richard Earnshaw <rearnsh@arm.com> PR target/79260 * config.gcc (arm*-*-*): Add arm/arm-flags.h and arm/arm-isa.h to tm_p_file. * arm/arm-protos.h: Don't directly include arm-flags.h and arm-isa.h. Change-Id: I8c2cd7d502044bdbb4bce5293a91c2f10c30284b
2017-04-04 gcc/Yvan Roux
Backport from trunk r246066. 2017-03-10 David Malcolm <dmalcolm@redhat.com> PR target/79925 * config/aarch64/aarch64.c (aarch64_validate_mcpu): Quote the full command-line argument, rather than just "str". (aarch64_validate_march): Likewise. (aarch64_validate_mtune): Likewise. Change-Id: I17ecebc01bc30837b34ecb63f18b10abac51b26e
2017-04-04 gcc/Yvan Roux
Backport from trunk r245877. 2017-03-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64.c (aarch64_float_const_representable_p): Use wide_int::ulow () instead of .elt (0). Change-Id: I4c65cf7ac10e3c553dff55ae9806ef75b2e44ff7
2017-04-04 gcc/Yvan Roux
Backport from trunk r245328. 2017-02-10 Christophe Lyon <christophe.lyon@linaro.org> * config/aarch64/arm_neon.h (vtst_p8): Rewrite without asm. (vtst_p16): Likewise. (vtstq_p8): Likewise. (vtstq_p16): Likewise. (vtst_p64): New. (vtstq_p64): Likewise. * config/arm/arm_neon.h (vgetq_lane_p64): New. (vset_lane_p64): New. (vsetq_lane_p64): New. gcc/testsuite/ Backport from trunk r245328. 2017-02-10 Christophe Lyon <christophe.lyon@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/p64_p128.c (vget_lane_expected, vset_lane_expected, vtst_expected_poly64x1): New. (vmov_n_expected0, vmov_n_expected1, vmov_n_expected2) (expected_vld_st2_0, expected_vld_st2_1, expected_vld_st3_0) (expected_vld_st3_1, expected_vld_st3_2, expected_vld_st4_0) (expected_vld_st4_1, expected_vld_st4_2, expected_vld_st4_3) (vtst_expected_poly64x2): Move to aarch64-only section. (vget_lane_p64, vgetq_lane_p64, vset_lane_p64, vsetq_lane_p64) (vtst_p64, vtstq_p64): New tests. Change-Id: I88c50b9b0efc55fc10b287b98231dba2dcd23f3c
2017-03-17 gcc/Yvan Roux
Backport from trunk r245101. 2017-02-01 Andrew Pinski <apinski@cavium.com> * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost): Pass stmt_info to record_stmt_cost. (vect_get_known_peeling_cost): Pass stmt_info if known to record_stmt_cost. * config/aarch64/aarch64-protos.h (cpu_vector_cost): Split cpu_vector_cost field into scalar_int_stmt_cost and scalar_fp_stmt_cost. Split vec_stmt_cost field into vec_int_stmt_cost and vec_fp_stmt_cost. * config/aarch64/aarch64.c (generic_vector_cost): Update for the splitting of scalar_stmt_cost and vec_stmt_cost. (thunderx_vector_cost): Likewise. (cortexa57_vector_cost): LIkewise. (exynosm1_vector_cost): Likewise. (xgene1_vector_cost): Likewise. (thunderx2t99_vector_cost): Improve after the splitting of the two fields. (aarch64_builtin_vectorization_cost): Update for the splitting of scalar_stmt_cost and vec_stmt_cost. Change-Id: Id7fb6264970c8f2db785df1bbc6ad3c30821a26f
2017-03-16 gcc/Yvan Roux
* LINARO-VERSION: Bump version number, post snapshot. Change-Id: Ie8541861cf9fed7b86705477a4ee8e69d8677204
2017-03-16Make Linaro GCC Snapshot 6.3-2017.03.linaro-snapshot-6.3-2017.03Yvan Roux
gcc/ * LINARO-VERSION: Update. Change-Id: I4549b534a86a69a1039bc00d48898d74b9e609ee
2017-03-15Merge branches/gcc-6-branch rev 246148.Yvan Roux
Change-Id: I706269373548f876b7f0d205507817f52ee8a2df
2017-03-15 gcc/Yvan Roux
Backport from trunk r242669. 2016-11-21 Richard Earnshaw <rearnsha@arm.com> * arm.opt (mapcs-float): Delete option. * arm.c (arm_option_override): Remove hunk relating to TARGET_APCS_FLOAT. * doc/invoke.texi (arm options): Remove documentation for -mapcs-float. Change-Id: Ied02e63e5d944bb7bd9c7feb6438725361ea84e4
2017-03-15 gcc/Yvan Roux
Backport from trunk r242551. 2016-11-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64.md (mov<mode>): Call aarch64_split_dimode_const_store on DImode constant stores. * config/aarch64/aarch64-protos.h (aarch64_split_dimode_const_store): New prototype. * config/aarch64/aarch64.c (aarch64_split_dimode_const_store): New function. gcc/testsuite/ Backport from trunk r242551. 2016-11-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gcc.target/aarch64/store_repeating_constant_1.c: New test. * gcc.target/aarch64/store_repeating_constant_2.c: Likewise. Change-Id: Icfbf1726c7d33be193cfbd71c3c4ed6e2b45c4a0
2017-03-15 gcc/Yvan Roux
Backport from trunk r242539. 2016-11-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): Check for const_double code before calling aarch64_float_const_zero_rtx_p. Change-Id: I6efc1ff1bb83de2e64575b32389c6d1f8e75f079
2017-03-15 gcc/Yvan Roux
Backport from trunk r243333. 2016-12-07 Naveen H.S <Naveen.Hurugalawadi@cavium.com> * config/aarch64/aarch64.c (aarch64_builtin_support_vector_misalignment): New. (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Define. gcc/testsuite/ Backport from trunk r243333. 2016-12-07 Naveen H.S <Naveen.Hurugalawadi@cavium.com> * gcc.target/aarch64/pr71727.c : New Testcase. Change-Id: Ia6b91005d9fd26b4389c237b58b3f13033070c42
2017-03-14 gcc/Yvan Roux
Backport from trunk r245388. 2016-02-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.c (arm_print_tune_info): Use ASM_COMMENT_START instead of explicit '@'. Add missing assembly comment marker on branch costs printout. Change-Id: I62e85450527ee4c44495794647795c478a79d71d
2017-03-14 gcc/Yvan Roux
Backport from trunk r245030. 2017-01-30 Martin Liska <mliska@suse.cz> PR bootstrap/78985 * config/aarch64/cortex-a57-fma-steering.c (func_fma_steering::analyze): Initialize variables with NULL value. Change-Id: I18e87c74aa42106ffc4f7934918fb3cbb43a83d9
2017-03-14 gcc/Yvan Roux
Backport from trunk r241248. 2016-10-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64.c: Delete inclusion of cortex-a57-fma-steering.h. (aarch64_override_options): Delete call to aarch64_register_fma_steering. * config/aarch64/aarch64-protos.h (make_pass_fma_steering): Declare. * config/aarch64/cortex-a57-fma-steering.h: Delete. * config/aarch64/aarch64-passes.def: New file. * config/aarch64/cortex-a57-fma-steering.c (aarch64_register_fma_steering): Delete definition. (make_pass_fma_steering): Remove static qualifier. * config/aarch64/t-aarch64 (PASSES_EXTRA): New directive. (cortex-a57-fma-steering.o): Remove dependency on cortex-a57-fma-steering.h. Change-Id: I1d33b60fd1fae8c9de3b2a75e51322c04dba9b7a
2017-03-14 gcc/Yvan Roux
Backport from trunk r242491. 2016-11-16 Richard Earnshaw <rearnsha@arm.com> * arm/arm-fpus.def (vfpv2): New FPU, currently an alias for 'vfp'. (neon-vfpv3): New FPU, currently an alias for 'neon'. * arm/arm-tables.opt: Regenerated. * arm/t-aprofile (MULTILIB_REUSE): Add reuse rules for vfpv2 and neon-vfpv3. * doc/invoke.texi (ARM: -mfpu): Document new options. Note that 'vfp' and 'neon' are aliases for specific implementations. Change-Id: I3c49607bc71b26fe547eb8c5e22c7f65a79e0f51
2017-03-14 gcc/testsuite/Yvan Roux
Backport from trunk r244372. 2017-01-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR tree-optimization/78319 * gcc.dg/uninit-pred-8_a.c: Add -mtune=cortex-a15 for arm. Remove xfail. Change-Id: Id16a0354186cd1459223c1eab8d26a69a671a3a2
2017-03-14 gcc/Yvan Roux
Backport from trunk r243541. 2016-12-12 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-opts.h: Move struct arm_arch_core_flag and arm_arch_core_flags to ... * common/config/arm/arm-common.c: There. Change-Id: I9b759fe3a4a657f9d088c13403ec9ff90275a61b
2017-03-14 gcc/Yvan Roux
Backport from trunk r245267. 2017-02-07 Andrew Pinski <apinski@cavium.com> * config/aarch64/aarch64.md (popcount<mode>2): New pattern. gcc/testsuite/ Backport from trunk r245267. 2017-02-07 Andrew Pinski <apinski@cavium.com> * gcc.target/aarch64/popcount.c : New Testcase. Change-Id: Iec549f39196b96849be3902de82e2a11398d07b1
2017-03-14 gcc/testsuite/Yvan Roux
Backport from trunk r245132. 2017-02-02 Tamar Christina <tamar.christina@arm.com> PR middle-end/78142 * gcc.target/aarch64/vector_initialization_nostack.c (f12): Use one vector Change-Id: Iffa83e288c1ea492512c78e85095cb313602df59
2017-03-14 gcc/testsuite/Yvan Roux
Backport from trunk r244723. 2017-01-20 Thomas Preud'homme <thomas.preudhomme@arm.com> * lib/target-supports.exp (check_configured_with): New procedure. (check_effective_target_default_mode): new effective target. * gcc.target/arm/optional_thumb-1.c: Skip if GCC was configured with a default mode. Fix dg-skip-if target selector syntax. * gcc.target/arm/optional_thumb-2.c: Likewise. * gcc.target/arm/optional_thumb-3.c: Fix dg-skip-if target selector syntax. Change-Id: I4b3a1d9dc409d9898f986b399ccf6f4722ad1340
2017-03-14 gcc/Yvan Roux
Backport from trunk r244663. 2017-01-19 Jiong Wang <jiong.wang@arm.com> * config/aarch64/aarch64-arches.def: New entry for "armv8.3-a". * config/aarch64/aarch64.h (AARCH64_FL_V8_3, AARCH64_FL_FOR_ARCH8_3, AARCH64_ISA_V8_3, TARGET_ARMV8_3): New. * doc/invoke.texi (AArch64 Options): Document "armv8.3-a". Change-Id: I40bec8b464c895bb0f80118820d75f9882879418
2017-03-14 gcc/testsuite/Yvan Roux
Backport from trunk r243858. 2016-12-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * gcc.target/arm/unsigned-extend-2.c: Update testcase. Change-Id: Ic7f32494b297610fa3ecb9f6bdfa62759e2b00fd
2017-03-14 gcc/Yvan Roux
Backport from trunk r243427. 2016-12-08 Andrew Pinski <apinski@cavium.com> * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Access the lower part of RTX appropriately. gcc/testsuite/ Backport from trunk r243427. 2016-12-08 Andrew Pinski <apinski@cavium.com> * gcc.target/aarch64/pr71112.c : New Testcase. Change-Id: I65299a59fe8e65328bd6def2ec86cf7fcd10ce8c
2017-03-14 gcc/Yvan Roux
Backport from trunk r243428. 2016-12-08 Naveen H.S <Naveen.Hurugalawadi@cavium.com> * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Handle SYMBOL_SMALL_TLSGD for ILP32. * config/aarch64/aarch64.md : tlsgd_small modified into tlsgd_small_<mode> to support SImode and DImode. *tlsgd_small modified into *tlsgd_small_<mode> to support SImode and DImode. gcc/testsuite/ Backport from trunk r243428. 2016-12-08 Naveen H.S <Naveen.Hurugalawadi@cavium.com> * gcc.target/aarch64/pr78382.c : New Testcase. Change-Id: Ie0bf9fc133bc8f4e696622ffefb1fffb165b48e6
2017-03-03 gcc/Yvan Roux
Backport from trunk r242531. 2016-11-16 Andrew PInski <apinski@cavium.com> * config/aarch64/aarch64.opt (mverbose-cost-dump): New option. * config/aarch64/aarch64.c (aarch64_rtx_costs): Use flag_aarch64_verbose_cost instead of checking for details dump. (aarch64_rtx_costs_wrapper): Likewise. Change-Id: I6d5c86ed82bf4cd4ceedae6a58252ddca292d710
2017-02-10 gcc/Yvan Roux
* LINARO-VERSION: Bump version number, post snapshot. Change-Id: I7399b09db73f3a5005f09ec611fc13652cd7a9df
2017-02-10Make Linaro GCC Snapshot 6.3-2017.02.linaro-snapshot-6.3-2017.02Yvan Roux
gcc/ * LINARO-VERSION: Update. Change-Id: Iacba5ee450e7d5173ae2ae0e1b60100281b09706
2017-02-06Merge branches/gcc-6-branch rev 245201.Yvan Roux
Change-Id: Ibc46d8742ef080683f302f5623b4907e9622ac4c
2017-01-31 gcc/testsuite/Christophe Lyon
Backport from trunk r244891. 2016-01-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gcc.dg/lto/pr54709_0.c: Require 'shared' effective target. * gcc.dg/lto/pr61526_0.c: Likewise. * gcc.dg/lto/pr64415_0.c: Likewise. Change-Id: I5e933c61f5f661ec9dcbd04b9f04b28e5c4ec0fb
2017-01-31 gcc/Christophe Lyon
Backport from trunk r244894. 2016-01-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/79145 * config/arm/arm.md (xordi3): Force constant operand into a register for TARGET_IWMMXT. gcc/testsuite/ Backport from trunk r244894. 2016-01-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/79145 * gcc.target/arm/pr79145.c: New test. Change-Id: Ia1ee8c855c4324fc3226fbc04bd485911c2c6289
2017-01-31 gcc/Christophe Lyon
Backport from trunk r244879. 2017-01-24 Eric Botcazou <ebotcazou@adacore.com> PR target/77439 * config/arm/arm.c (arm_function_ok_for_sibcall): Add back restriction for long calls with APCS frame and VFP. gcc/testsuite/ Backport from trunk r244879. 2017-01-24 Eric Botcazou <ebotcazou@adacore.com> * gcc.target/arm/vfp-longcall-apcs.c: New test. Change-Id: I1663e7b52decbb7c5d9cb13c42136e10e44940b7
2017-01-30 gcc/Christophe Lyon
Backport from trunk r244828. 2017-01-23 Andreas Tobler <andreast@gcc.gnu.org> * config/aarch64/aarch64.c (aarch64_elf_asm_constructor): Increase size of buf. (aarch64_elf_asm_destructor): Likewise. Change-Id: I22482fe29e558254616a97aeddd6b39c48718a85
2017-01-30 gcc/testsuite/Christophe Lyon
Backport from trunk r244772. 2017-01-23 Christophe Lyon <christophe.lyon@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK_POLY): New. (CHECK_RESULTS_NAMED_NO_FP16): Call CHECK_POLY instead of CHECK for poly*_t types. * gcc.target/aarch64/advsimd-intrinsics/vcnt.c (FNNAME): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcombine.c (void exec_vcombine): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcreate.c (FNNAME): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vget_high.c (void exec_vget_high): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vget_low.c (void exec_vget_low): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vldX.c (void exec_vldX): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c (void exec_vldX_dup): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c (void exec_vldX_lane): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vmul.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vmvn.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vqtbX.c (void exec_vqtbX): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrev.c (void exec_vrev): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vsli_n.c (void vsli_extra): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vsri_n.c (void vsri_extra): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c (void exec_vstX_lane): Likewise. * gcc.target/aarch64/advsimd-intrinsics/vtbX.c (void exec_vtbX): Likewise. * gcc.target/aarch64/advsimd-intrinsics/p64_p128.c (int main): Likewise. (TEST_VGET_LANE): Cast to uint to avoid warning. * gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc (void FNNAME): Fix PRIx format for int16_t, int32_t, uint16_t, uint32_t. * gcc.target/aarch64/advsimd-intrinsics/vfms_vfma_n.c (void exec_vfma_vfms_n): Fix PRIx format for float64_t. * gcc.target/aarch64/advsimd-intrinsics/vmovn.c (void exec_vmovn): Fix PRIx format for int8_t, int16_t, uint8_t, uint16_t. * gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c (void exec_vmul_lane): Fix PRIx format for int16_t, uint16_t. * gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vmull.c (void exec_vmull): Fix PRIx format for int16_t, int64_t, uint16_t, uint64_t. Call CHECK_POLY instead of CHECK for poly64_t types. * gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c (void exec_vmull_lane): Fix PRIx format for int64_t, uint64_t. * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: Fix PRIx format for int8_t, int16_t, uint8_t, uint16_t. * gcc.target/aarch64/advsimd-intrinsics/vqabs.c (void vqabs_extra): Fix PRIx format for int16_t, int32_t, uint16_t, uint32_t. * gcc.target/aarch64/advsimd-intrinsics/vqdmull.c: Fix PRIx format for int32_t, int64_t. * gcc.target/aarch64/advsimd-intrinsics/vqneg.c (void vqneg_extra): Fix PRIx format for int16_t, int32_t. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c (TEST_VREINTERPRET_TO_POLY): New. (main): Call TEST_VREINTERPRET_TO_POLY instead of TEST_VREINTERPRET where needed. Change-Id: I4e3d5d184b57c3d544daf384bebe1ca79a747cfe
2017-01-30 gcc/Christophe Lyon
Backport from trunk r241965. 2016-11-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.c (arm_slowmul_tune): Use generic_extra_costs. (arm_fastmul_tune): Likewise. (arm_strongarm_tune): Likewise. (arm_xscale_tune): Likewise. (arm_9e_tune): Likewise. (arm_marvell_pj4_tune): Likewise. (arm_v6t2_tune): Likewise. (arm_v6m_tune): Likewise. (arm_fa726te_tune): Likewise. gcc/ Backport from trunk r241966. 2016-11-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.opt (mold-rtx-costs): Delete. (mnew-generic-costs): Delete. * config/arm/arm-protos.h (struct tune_params): Delete rtx_costs field. * config/arm/arm.c (arm_rtx_costs_1): Delete. (arm_size_rtx_costs): Likewise. (arm_slowmul_rtx_costs): Likewise. (arm_fastmul_rtx_costs): Likewise. (arm_xscale_rtx_costs): Likewise. (arm_9e_rtx_costs): Likewise. (arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune, arm_9e_tune, arm_v6t2_tune, arm_cortex_tune, arm_cortex_a8_tune, arm_cortex_a7_tune, arm_cortex_a15_tune, arm_cortex_a53_tune, arm_cortex_a57_tune, arm_cortex_a9_tune, arm_cortex_a12_tune, arm_v7m_tune, arm_v6m_tune, arm_fa726te_tune arm_cortex_a5_tune, arm_xgene1_tune, arm_marvell_pj4_tune, arm_cortex_a35_tune, arm_exynosm1_tune, arm_cortex_a73_tune, arm_cortex_m7_tune): Delete rtx_costs field. (arm_new_rtx_costs): Rename to... (arm_rtx_costs_internal): ... This. (arm_rtx_costs): Remove old way of doing rtx costs. Change-Id: I6d1dbef466bc74c932fe597f18b8ef6cbcfb4c1c
2017-01-30 gcc/Christophe Lyon
Backport from trunk r244643. 2016-01-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64-protos.h (aarch64_nopcrelative_literal_loads): Delete. * config/aarch64/aarch64.md (aarch64_reload_movcp<GPF_TF:mode><P:mode>): Delete reference to aarch64_nopcrelative_literal_loads. (aarch64_reload_movcp<VALL:mode><P:mode>): Likewise. Change-Id: I734b2d4ee36a58c79daee33a2d221799e6c1efe2
2017-01-30 gcc/Christophe Lyon
Backport from trunk r244716. 2017-01-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/71270 * config/arm/arm.c (neon_valid_immediate): Reject vector constants in big-endian mode when they are not a single duplicated value. Change-Id: Ic4d9bfae5ac18f63895ad5d4206027ce7cbcccd6