2023-07-07 Release Manager * GCC 10.5.0 released. 2023-06-28 liuhongt * config/i386/i386-features.c (pass_insert_vzeroupper:gate): Move flag_expensive_optimizations && !optimize_size to .. * config/i386/i386-options.c (ix86_option_override_internal): .. this, it makes -mvzeroupper independent of optimization level, but still keeps the behavior of architecture tuning(emit_vzeroupper) unchanged. (rest_of_handle_insert_vzeroupper): Remove flag_expensive_optimizations && !optimize_size. 2023-06-20 Kewen Lin Backported from master: 2023-06-20 Kewen Lin PR target/109932 * config/rs6000/rs6000-builtin.def (BU_VSX_MISC_2): New macro. ({un,}pack_vector_int128): Use BU_VSX_MISC_2 instead of BU_P7_MISC_2. 2023-06-19 Kewen Lin Backported from master: 2023-06-12 Kewen Lin PR target/110011 * config/rs6000/rs6000.c (output_toc): Use the mode of the 128-bit floating constant itself for real_to_target call. 2023-06-09 Iain Sandoe Backported from master: 2023-06-02 Iain Sandoe PR target/110044 * config/rs6000/rs6000.c (darwin_rs6000_special_round_type_align): Make sure that we do not have a cap on field alignment before altering the struct layout based on the type alignment of the first entry. 2023-06-01 Jonathan Wakely Backported from master: 2023-06-01 Jonathan Wakely PR target/109954 * doc/invoke.texi (x86 Options): Fix description of -m32 option. 2023-05-22 Michael Meissner PR target/70243 * config/rs6000/vsx.md (vsx_fmav4sf4): Do not generate vmaddfp. Back port from master 04/10/2023. (vsx_nfmsv4sf4): Do not generate vnmsubfp. 2023-05-21 Iain Sandoe Backported from master: 2021-12-24 Iain Sandoe * config.gcc: Emit L2_MAX_OFILE_ALIGNMENT with suitable values for the host. * config/darwin.c (darwin_emit_common): Error for alignment values > 32768. * config/darwin.h (MAX_OFILE_ALIGNMENT): Rework to use the configured L2_MAX_OFILE_ALIGNMENT. 2023-05-09 Jakub Jelinek Backported from master: 2023-05-09 Jakub Jelinek PR tree-optimization/109778 * wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on wi::zext (x, width) rather than x if width != precision, rather than using wi::zext (right, width) after the shift. * tree-ssa-ccp.c (bit_value_binop): Call wi::ext on the results of wi::lrotate or wi::rrotate. 2023-05-04 Richard Biener Revert: 2023-02-07 Richard Biener PR tree-optimization/106809 * tree-ssa-sccvn.c (dominaged_by_p_w_unex): Check we have more than one successor before doing extra work. 2023-05-03 Anthony Sharp Backported from master: 2021-08-27 Anthony Sharp * symbol-summary.h: Added missing template keyword. 2023-05-03 Jakub Jelinek Backported from master: 2023-04-12 Jakub Jelinek PR tree-optimization/109410 * tree-ssa-reassoc.c (build_and_add_sum): Split edge from entry block if first statement of the function is a call to returns_twice function. 2023-05-03 Jakub Jelinek Backported from master: 2023-03-28 Jakub Jelinek PR middle-end/106190 * sanopt.c (pass_sanopt::execute): Return TODO_cleanup_cfg if any of the IFN_{UB,HWA,A}SAN_* internal fns are lowered. 2023-05-03 Jakub Jelinek Backported from master: 2023-03-26 Jakub Jelinek PR ipa/105685 * predict.c (compute_function_frequency): Don't call warn_function_cold if function already has cold attribute. 2023-05-03 Jakub Jelinek Backported from master: 2023-03-17 Jakub Jelinek PR target/105554 * function.h (push_struct_function): Add ABSTRACT_P argument defaulted to false. * function.c (push_struct_function): Add ABSTRACT_P argument, pass it to allocate_struct_function instead of false. * tree-inline.c (initialize_cfun): Don't copy DECL_ARGUMENTS nor DECL_RESULT here. Pass true as ABSTRACT_P to push_struct_function. Call targetm.target_option.relayout_function after it. (tree_function_versioning): Formatting fix. 2023-05-03 Jakub Jelinek Backported from master: 2023-03-17 Jakub Jelinek PR middle-end/108685 * omp-expand.c (expand_omp_for_ordered_loops): Add L0_BB argument, use its loop_father rather than BODY_BB's loop_father. (expand_omp_for_generic): Adjust expand_omp_for_ordered_loops caller. If broken_loop with ordered > collapse and at least one of those extra loops aren't guaranteed to have at least one iteration, change l0_bb's loop_father to entry_bb's loop_father. Set cont_bb's loop_father to l0_bb's loop_father rather than l1_bb's. 2023-05-03 Jakub Jelinek Backported from master: 2023-03-04 Jakub Jelinek PR testsuite/108973 * selftest-diagnostic.c (test_diagnostic_context::test_diagnostic_context): Set caret_max_width to 80. 2023-05-03 Jakub Jelinek Backported from master: 2023-02-24 Jakub Jelinek PR middle-end/108854 * cgraphclones.c (duplicate_thunk_for_node): If no parameter changes are needed, copy at least DECL_ARGUMENTS PARM_DECL nodes and adjust their DECL_CONTEXT. 2023-05-03 Jakub Jelinek Backported from master: 2023-02-24 Jakub Jelinek PR target/108881 * config/i386/i386-builtin.def (__builtin_ia32_cvtne2ps2bf16_v16hi, __builtin_ia32_cvtne2ps2bf16_v16hi_mask, __builtin_ia32_cvtne2ps2bf16_v16hi_maskz, __builtin_ia32_cvtne2ps2bf16_v8hi, __builtin_ia32_cvtne2ps2bf16_v8hi_mask, __builtin_ia32_cvtne2ps2bf16_v8hi_maskz, __builtin_ia32_cvtneps2bf16_v8sf_mask, __builtin_ia32_cvtneps2bf16_v8sf_maskz, __builtin_ia32_cvtneps2bf16_v4sf_mask, __builtin_ia32_cvtneps2bf16_v4sf_maskz, __builtin_ia32_dpbf16ps_v8sf, __builtin_ia32_dpbf16ps_v8sf_mask, __builtin_ia32_dpbf16ps_v8sf_maskz, __builtin_ia32_dpbf16ps_v4sf, __builtin_ia32_dpbf16ps_v4sf_mask, __builtin_ia32_dpbf16ps_v4sf_maskz): Require also OPTION_MASK_ISA_AVX512VL. 2023-05-03 Andrew Pinski Backported from master: 2023-02-09 Andrew Pinski PR tree-optimization/108688 * match.pd (bit_field_ref [bit_insert]): Avoid generating BIT_FIELD_REFs of non-mode-precision integral operands. 2023-05-03 Jakub Jelinek Backported from master: 2023-02-02 Jakub Jelinek PR middle-end/108435 * tree-nested.c (convert_nonlocal_omp_clauses) : If info->new_local_var_chain and *seq is not a GIMPLE_BIND, wrap the sequence into a new GIMPLE_BIND before calling declare_vars. (convert_nonlocal_omp_clauses) : Merge with the OMP_CLAUSE_LASTPRIVATE handling except for whether seq is initialized to &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (clause) or &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause). 2023-05-03 Jakub Jelinek Backported from master: 2023-02-01 Jakub Jelinek PR debug/108573 * ree.c (combine_reaching_defs): Don't return false for paradoxical subregs in DEBUG_INSNs. 2023-05-03 Jakub Jelinek Backported from master: 2023-01-31 Jakub Jelinek PR rtl-optimization/108596 * bb-reorder.c (fix_up_fall_thru_edges): Handle the case where cur_bb ends with asm goto and has a crossing fallthrough edge to the same bb that contains at least one of its labels by restoring EDGE_CROSSING flag even on possible edge from cur_bb to new_bb successor. 2023-05-03 Jakub Jelinek Backported from master: 2023-01-27 Jakub Jelinek PR other/108560 * doc/extend.texi: Fix up return type of __builtin_va_arg_pack_len from size_t to int. 2023-05-03 Eric Biggers Backported from master: 2023-01-24 Eric Biggers PR bootstrap/90543 * optc-save-gen.awk: Fix copy-and-paste error. 2023-05-03 Jakub Jelinek Backported from master: 2023-01-04 Jakub Jelinek PR middle-end/108237 * generic-match-head.c: Include tree-pass.h. (canonicalize_math_p): Define to false if cfun and cfun->curr_properties has PROP_gimple_opt_math resp. PROP_gimple_lvec property set. 2023-05-03 Jakub Jelinek Backported from master: 2022-12-23 Jakub Jelinek PR tree-optimization/108068 * tree.h (real_maybe_zerop): Declare. * tree.c (real_maybe_zerop): Define. * tree-ssa-dom.c (record_edge_info): Use it instead of real_zerop or TREE_CODE (op1) == SSA_NAME || real_zerop. Always set can_infer_simple_equiv to false for decimal floating point types. 2023-05-03 Jakub Jelinek Backported from master: 2022-12-22 Jakub Jelinek PR rtl-optimization/108193 * cse.c (compute_const_anchors): Change n type to unsigned HOST_WIDE_INT, adjust comparison against it to avoid warnings. Formatting fix. (insert_const_anchor): Use gen_int_mode instead of GEN_INT. 2023-05-03 Jakub Jelinek Backported from master: 2022-12-16 Jakub Jelinek PR rtl-optimization/106751 * loop-invariant.c (move_invariant_reg): If preheader bb ends with a JUMP_INSN, split the preheader edge and emit invariants into the new preheader basic block. 2023-05-03 Jakub Jelinek Backported from master: 2022-12-10 Jakub Jelinek PR tree-optimization/107997 * tree-ssa-loop-ivopts.c: Include cfganal.h. (create_new_iv) : If ip_end_pos bb is non-empty and ends with a stmt which ends bb, instead of adding iv update after it split the latch edge and insert iterator into the new latch bb. 2023-05-03 Jakub Jelinek Backported from master: 2022-12-08 Jakub Jelinek PR debug/106719 * cfgbuild.c (find_bb_boundaries): If there are NOTEs in between debug_insn (seen after flow_transfer_insn) and insn, move NOTEs before all the DEBUG_INSNs and split after NOTEs. If there are other insns like jump table data, clear debug_insn. 2023-05-03 Jakub Jelinek Backported from master: 2022-11-24 Jakub Jelinek PR middle-end/107317 * asan.c: Include diagnostic-core.h. (asan_emit_stack_protection): Return NULL early if seen_error (). 2023-05-03 Jakub Jelinek Backported from master: 2022-11-21 Jakub Jelinek PR target/107748 * config/i386/smmintrin.h (_mm_extract_ps): Uglify names of local variables and union members. 2023-05-03 Jakub Jelinek Backported from master: 2022-11-20 Jakub Jelinek PR target/107183 * reg-stack.c (next_flags_user): Add DEBUG_SEEN argument. If >= 0 and a DEBUG_INSN would be otherwise returned, set DEBUG_SEEN to 1 and ignore it. (swap_rtx_condition): Add DEBUG_SEEN argument. In >= 0 mode only set DEBUG_SEEN to 1 if problematic DEBUG_ISNSs were seen and revert all changes on success in that case. Don't try to recog_memoized DEBUG_INSNs. (compare_for_stack_reg): Adjust swap_rtx_condition caller. If it returns true and debug_seen is 1, call swap_rtx_condition again with debug_seen -1. 2023-05-03 Jakub Jelinek Backported from master: 2022-09-24 Jakub Jelinek PR c/107001 * omp-low.c (lower_omp_taskgroup): Don't add GOMP_RETURN statement at the end. * omp-expand.c (build_omp_regions_1): Clarify GF_OMP_TARGET_KIND_DATA is not stand-alone directive. For GIMPLE_OMP_TASKGROUP, also don't update parent. (omp_make_gimple_edges) : Reset cur_region back after new_omp_region. 2023-05-03 Jakub Jelinek Backported from master: 2022-07-27 Jakub Jelinek PR debug/106261 * cgraphunit.c (cgraph_node::assemble_thunks_and_aliases): Don't output asm thunks for -dx. 2023-05-03 Jakub Jelinek Backported from master: 2022-07-01 Jakub Jelinek PR middle-end/106144 * wide-int.cc (wi::shifted_mask): If end >= prec, return right after emitting element for shift or if shift is 0 first element after start. (wide_int_cc_tests): Add tests for equivalency of wi::mask and wi::shifted_mask with 0 start. 2023-05-03 Jakub Jelinek Backported from master: 2022-06-21 Jakub Jelinek PR rtl-optimization/106032 * ifcvt.c (noce_try_sign_mask): Punt if !t_unconditional, and t may_trap_or_fault_p, even if it is cheap. 2023-05-03 Jakub Jelinek Backported from master: 2022-06-21 Jakub Jelinek PR middle-end/106030 * expr.c (expand_cond_expr_using_cmove): Pass NULL_RTX instead of temp to expand_operands if mode has been promoted. 2023-04-18 Philipp Tomsich Backported from master: 2023-01-31 Philipp Tomsich PR target/108589 * config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Check REG_P on SET_DEST. 2023-04-18 Philipp Tomsich Backported from master: 2023-04-17 Philipp Tomsich Di Zhao * config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNING_OPTION): Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE. * config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp): Check for the above tuning option when processing loads. 2023-04-18 Philipp Tomsich Backported from master: 2023-03-27 Philipp Tomsich Jiangning Liu Manolis Tsamis * config/aarch64/aarch64.c: Update vector costs for ampere1. 2023-04-18 Philipp Tomsich Backported from master: 2022-11-14 Philipp Tomsich * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add ampere1a. * config/aarch64/aarch64-cost-tables.h: Add ampere1a_extra_costs. * config/aarch64/aarch64-fusion-pairs.def (AARCH64_FUSION_PAIR): Define a new fusion pair for A+B+1/A-B-1 (i.e., add/subtract two registers and then +1/-1). * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Implement idiom-matcher for the new fusion pair. * doc/invoke.texi: Add ampere1a. 2023-04-18 Philipp Tomsich Backported from master: 2022-10-06 Philipp Tomsich * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update Ampere-1 core entry. 2023-04-18 Philipp Tomsich Backported from master: 2022-10-06 Philipp Tomsich * config/aarch64/driver-aarch64.c (readline): Fix off-by-one. 2023-04-18 Philipp Tomsich Backported from master: 2021-11-03 Philipp Tomsich * config/aarch64/aarch64-cores.def (AARCH64_CORE): New Ampere-1 core. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/aarch64-cost-tables.h: Add extra costs for Ampere-1. * config/aarch64/aarch64.c: Add tuning structures for Ampere-1. * doc/invoke.texi: Add documentation for Ampere-1 core. 2023-04-17 Kewen Lin Backported from master: 2023-04-04 Kewen Lin PR target/108699 * config/rs6000/altivec.md (*p9v_parity2): Rename to ... (rs6000_vprtyb2): ... this. * config/rs6000/rs6000-builtin.def (VPRTYBD): Replace parityv2di2 with rs6000_vprtybv2di2. (VPRTYBW): Replace parityv4si2 with rs6000_vprtybv4si2. (VPRTYBQ): Replace parityv1ti2 with rs6000_vprtybv1ti2. * config/rs6000/vector.md (parity2 with VEC_IP): Expand with popcountv16qi2 and the corresponding rs6000_vprtyb2. 2023-02-24 Sebastian Huber Backported from master: 2023-02-24 Sebastian Huber * config/riscv/t-rtems: Keep only -mcmodel=medany 64-bit multilibs. Add non-compact 32-bit multilibs. 2023-02-20 Alex Coplan Backported from master: 2023-02-06 Alex Coplan PR target/104921 * config/aarch64/aarch64-simd.md (aarch64_bfmlal_lanev4sf): Use correct constraint for operand 3. 2023-02-13 Kewen Lin Backported from master: 2023-01-18 Kewen Lin PR target/108348 * config/rs6000/rs6000.c (rs6000_opaque_type_invalid_use_p): Add the support for invalid uses of MMA opaque type in function arguments. 2023-02-13 Kewen Lin Backported from master: 2023-01-16 Kewen Lin PR target/108272 * config/rs6000/rs6000.c (rs6000_opaque_type_invalid_use_p): Add the support for invalid uses in inline asm, factor out the checking and erroring to lambda function check_and_error_invalid_use. 2023-02-07 Richard Biener Backported from master: 2022-09-02 Richard Biener PR tree-optimization/106809 * tree-ssa-sccvn.c (dominaged_by_p_w_unex): Check we have more than one successor before doing extra work. 2023-02-03 Alex Coplan Backported from master: 2022-12-01 Alex Coplan * varasm.c (assemble_variable): Fix type confusion bug when checking for ".vtable_map_vars" section. 2023-01-26 Richard Biener Backported from master: 2022-11-11 Richard Biener Nikita Voronov PR tree-optimization/107554 * tree-ssa-strlen.c (strlen_pass::count_nonzero_bytes): Use unsigned HOST_WIDE_INT type for the strlen. 2023-01-26 Richard Biener Backported from master: 2022-10-21 Richard Biener PR tree-optimization/107323 * tree-loop-distribution.c (pg_unmark_merged_alias_ddrs): New function. (loop_distribution::break_alias_scc_partitions): Revert postorder save/restore from the PR94125 fix. Instead make sure to not ignore edges from SCCs we are going to merge. 2023-01-26 Richard Biener Backported from master: 2022-10-06 Richard Biener PR tree-optimization/107107 * tree-ssa-sccvn.c (visit_reference_op_store): Do not affect value-numbering when doing the tail merging MODIFY_EXPR lookup. 2023-01-26 Richard Biener Backported from master: 2022-09-14 Richard Biener PR tree-optimization/106934 * tree-ssa.c (non_rewritable_mem_ref_base): Avoid BIT_FIELD_REFs of bitfields. (maybe_rewrite_mem_ref_base): Likewise. 2023-01-25 Christophe Lyon Backported from master: 2023-01-12 Christophe Lyon Richard Sandiford * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Fix comment. (aarch64_layout_arg): Factorize warning conditions. (aarch64_function_arg_boundary): Fix typo. * function.c (currently_expanding_function_start): New variable. (expand_function_start): Handle currently_expanding_function_start. * function.h (currently_expanding_function_start): Declare. 2023-01-24 Sergei Trofimovich Backported from master: 2022-08-16 Sergei Trofimovich PR driver/106624 * gcc.c (driver::detect_jobserver): Allocate storage xputenv() argument using xstrdup(). 2023-01-05 Kewen Lin PR target/106736 * config/rs6000/mma.md (define_expand movoo): Call function rs6000_opaque_type_invalid_use_p to check and emit error message for the invalid use of opaque type. (define_expand movxo): Likewise. * config/rs6000/rs6000-protos.h (rs6000_opaque_type_invalid_use_p): New function declaration. (currently_expanding_gimple_stmt): New extern declaration. * config/rs6000/rs6000.c (rs6000_opaque_type_invalid_use_p): New function. 2022-12-22 Martin Liska Backported from master: 2022-08-10 Martin Liska * opts-jobserver.h: Add one member. * opts-common.c (jobserver_info::jobserver_info): Parse FIFO format of --jobserver-auth. 2022-12-22 Martin Liska Backported from master: 2022-08-10 Martin Liska * gcc.c (driver::detect_jobserver): Remove and move to jobserver.h. * lto-wrapper.c (jobserver_active_p): Likewise. (run_gcc): Likewise. * opts-jobserver.h: New file. * opts-common.c (jobserver_info::jobserver_info): New function. 2022-12-15 Sebastian Pop PR target/98776 * config/aarch64/aarch64-protos.h (aarch64_output_patchable_area): Declared. * config/aarch64/aarch64.c (aarch64_print_patchable_function_entry): Emit an UNSPECV_PATCHABLE_AREA pseudo instruction. (aarch64_output_patchable_area): New. * config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New. (patchable_area): Define. 2022-12-01 liuhongt PR target/107863 * config/i386/i386-expand.c (ix86_expand_vec_set_builtin): Convert op1 to target mode whenever mode mismatch. 2022-11-30 John David Anglin * config/pa/pa.md (addvdi3): Force operand 2 to a register. Remove "addi,tsv,*" instruction from unamed pattern. (subvdi3): Force operand 1 to a register. Remove "subi,tsv" instruction from from unamed pattern. 2022-11-29 Max Filippov Backported from master: 2022-11-08 Max Filippov PR rtl-optimization/107482 * ira-color.c (assign_hard_reg): Only call update_costs_from_copies when retry_p is false. 2022-11-19 Thomas Schwinge Backported from master: 2022-11-19 Thomas Schwinge * config/nvptx/nvptx.h (STARTFILE_SPEC): Fix 'crt0.o' for '-mmainkernel'. 2022-11-14 Richard Biener PR tree-optimization/107485 * tree-inline.c (remap_gimple_stmt): Use correct type for split out condition of [VEC_]COND_EXPRs. 2022-11-08 H.J. Lu Backported from master: 2022-10-25 H.J. Lu PR target/107304 * expr.c (get_inner_reference): Always use TYPE_MODE for vector field with vector raw mode. 2022-11-05 Jonathan Wakely Backported from master: 2022-11-05 Jonathan Wakely PR c/41041 * doc/cppopts.texi: Document -fwide-exec-charset defaults correctly. 2022-10-25 Stefan Schulze Frielinghaus Backported from master: 2022-10-19 Stefan Schulze Frielinghaus PR target/106355 * config/s390/s390.c (s390_call_saved_register_used): For a parameter with BLKmode fix determining number of consecutive registers. 2022-10-25 Martin Liska Backported from master: 2022-10-24 Martin Liska PR target/107364 * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Reorder enum values as BUILTIN_VENDOR_MAX should not point in the middle of the valid enum values. 2022-10-21 Eric Botcazou PR target/107336 * optabs.c (expand_vec_cond_expr): Query both VCOND and VCONDU for EQ and NE. 2022-10-21 Richard Sandiford Backported from master: 2022-10-20 Richard Sandiford * config/aarch64/aarch64-sve.md (*aarch64_brk_cc): Remove merging alternative. (*aarch64_brk_ptest): Likewise. 2022-10-21 Richard Sandiford Backported from master: 2022-10-20 Richard Sandiford * config/aarch64/iterators.md (SVE_BRKP): New iterator. * config/aarch64/aarch64-sve.md (*aarch64_brkn_cc): New pattern. (*aarch64_brkn_ptest): Likewise. (*aarch64_brk_cc): Restrict to SVE_BRKP. (*aarch64_brk_ptest): Likewise. 2022-10-21 Richard Sandiford * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8_3): Add AARCH64_FL_RCPC. (AARCH64_ISA_RCPC): New macro. * config/aarch64/aarch64-cores.def (thunderx3t110, zeus, neoverse-v1) (neoverse-512tvb, saphira): Remove RCPC from these Armv8.3-A+ cores. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_RCPC when appropriate. 2022-10-20 Kewen Lin Backported from master: 2022-09-26 Kewen Lin PR target/96072 * config/rs6000/rs6000-logue.c (rs6000_emit_epilogue): Update the condition for adding REG_CFA_DEF_CFA reg note with frame_pointer_needed_indeed. 2022-10-17 Pat Haugen PR target/99685 * config/rs6000/rs6000-call.c (rs6000_function_arg_advance_1): Bump register count when not splitting IEEE 128-bit Complex. 2022-10-14 Richard Biener Backported from master: 2022-08-10 Richard Biener PR lto/106540 PR lto/106334 * lto-streamer-in.c (lto_read_tree_1): Use lto_input_tree_1 to input DECL_INITIAL, avoiding to commit drefs. 2022-10-14 Richard Biener Backported from master: 2022-08-10 Richard Biener PR tree-optimization/106513 * gimple-ssa-store-merging.c (do_shift_rotate): Use uint64_t for head_marker. 2022-10-14 Richard Biener Backported from master: 2022-07-19 Richard Biener PR middle-end/106331 * builtins.c (get_memory_rtx): Compute alignment from the original address and set MEM_OFFSET to unknown when we create a MEM_EXPR from the base object of the address. 2022-10-14 Richard Biener Backported from master: 2022-07-01 Richard Biener PR tree-optimization/106131 * tree-ssa-sccvn.c (vn_reference_lookup_3): Force alias-set zero when offsetting the read looking through an aggregate copy. 2022-10-14 Richard Biener Backported from master: 2022-06-29 Richard Biener PR tree-optimization/106112 * tree-ssa-sccvn.c (valueized_wider_op): Properly extend a constant operand according to its type. 2022-10-14 Eric Botcazou PR target/107248 * config/sparc/sparc.c (sparc_expand_prologue): Emit a frame blockage for leaf functions. (sparc_flat_expand_prologue): Emit frame instead of full blockage. (sparc_expand_epilogue): Emit a frame blockage for leaf functions. (sparc_flat_expand_epilogue): Emit frame instead of full blockage. 2022-10-03 Sergei Trofimovich Backported from master: 2022-10-03 Sergei Trofimovich PR target/107064 * config/i386/t-i386: Add build-time dependencies against i386-builtin-types.inc to i386-builtins.o, i386-expand.o, i386-features.o. 2022-09-28 Kyrylo Tkachov * config/aarch64/aarch64-cores.def (neoverse-v2): New entry. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (AArch64 Options): Document neoverse-v2. 2022-09-21 Richard Sandiford Backported from master: 2022-09-20 Richard Sandiford PR target/106491 * config/aarch64/aarch64-sve-builtins.cc (scalar_types) (acle_vector_types, acle_svpattern, acle_svprfop): Add GTY markup to (new) extern declarations instead of to the main definition. 2022-09-14 Tom de Vries Backported from master: 2022-02-01 Tom de Vries * config/nvptx/nvptx.c (nvptx_single): Use nvptx_uniform_warp_check. * config/nvptx/nvptx.md (define_c_enum "unspecv"): Add UNSPECV_UNIFORM_WARP_CHECK. (define_insn "nvptx_uniform_warp_check"): New define_insn. 2022-09-14 Tom de Vries Backported from master: 2022-02-01 Tom de Vries * config/nvptx/nvptx.c (nvptx_single): Use nvptx_warpsync. * config/nvptx/nvptx.md (define_c_enum "unspecv"): Add UNSPECV_WARPSYNC. (define_insn "nvptx_warpsync"): New define_insn. 2022-09-14 Thomas Schwinge * config/nvptx/nvptx.h (TARGET_PTX_6_0): '#define' to 'false'. 2022-09-13 Peter Bergner Backported from master: 2022-09-01 Peter Bergner PR target/101322 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Enforce the use of a valid MMA pointer type. 2022-09-08 Sebastian Huber * config/rs6000/rtems.h (CPP_OS_DEFAULT_SPEC): Define __PPC_VRSAVE__ if -mvrsave is present. * config/rs6000/t-rtems: Add -mvrsave multilib variants for -mcpu=e6500. 2022-08-30 Peter Bergner Backported from master: 2022-08-28 Peter Bergner PR target/106017 * config/rs6000/rs6000.c (rs6000_invalid_conversion): Remove handling of MMA pointer conversions. 2022-08-24 Kewen Lin Backported from master: 2022-08-16 Kewen Lin PR target/103353 * config/rs6000/mma.md (define_expand movpoi): Move TARGET_MMA condition check to preparation statements and add handlings for !TARGET_MMA. (define_expand movpxi): Likewise. 2022-08-16 Segher Boessenkool Backported from master: 2022-04-21 Segher Boessenkool PR target/103197 PR target/102146 * config/rs6000/rs6000.md (zero_extendqi2 for EXTQI): Disparage the "Z" alternatives in {l,st}{f,xs}iwzx. (zero_extendhi2 for EXTHI): Ditto. (zero_extendsi2 for EXTSI): Ditto. (*movsi_internal1): Ditto. (*mov_internal1 for QHI): Ditto. (movsd_hardfloat): Ditto. 2022-08-02 Peter Bergner Backported from master: 2022-07-25 Peter Bergner Kewen Lin PR testsuite/106345 * config/rs6000/rs6000.h (DRIVER_SELF_SPECS): Adjust -mdejagnu-cpu to filter out all -mtune options. 2022-08-02 Kewen Lin Backported from master: 2022-07-26 Kewen Lin PR target/106091 * config/rs6000/rs6000-p8swap.c (replace_swapped_aligned_store): Copy REG_EH_REGION when replacing one store insn having it. (replace_swapped_aligned_load): Likewise. 2022-07-25 Sebastian Huber Backported from master: 2022-07-25 Sebastian Huber * config/rs6000/rtems.h (CPLUSPLUS_CPP_SPEC): Undef. 2022-07-22 Surya Kumari Jangala Backported from master: 2022-06-14 Surya Kumari Jangala PR rtl-optimization/105041 * regrename.c (check_new_reg_p): Use nregs value from du chain. 2022-07-13 Martin Jambor Backported from master: 2022-07-04 Martin Jambor PR tree-optimization/105860 * tree-sra.c (build_reconstructed_reference): Start expr traversal only just below the outermost union. 2022-06-28 Release Manager * GCC 10.4.0 released. 2022-06-24 Iain Buclaw Backported from master: 2022-06-24 Iain Buclaw * config/tilepro/gen-mul-tables.cc (tilegx_emit): Adjust loop condition to avoid overflow. 2022-06-20 Uros Bizjak Backported from master: 2022-06-17 Uroš Bizjak PR target/105209 * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New. * config/alpha/alpha.c (alpha_store_data_bypass_p): New function. (alpha_store_data_bypass_p_1): Ditto. * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead of generic store_data_bypass_p. (ev4_ist_c): Remove insn reservation. 2022-06-20 Uros Bizjak Backported from master: 2022-06-17 Uroš Bizjak PR target/105970 * config/i386/i386.c (ix86_function_arg): Assert that the mode of pointer argumet is equal to ptr_mode, not Pmode. 2022-06-20 Segher Boessenkool Backported from master: 2022-03-12 Segher Boessenkool PR target/104829 * config/rs6000/rs6000.c (rs6000_machine_from_flags): Don't output "ppc" and "ppc64" based on rs6000_cpu. 2022-06-20 Segher Boessenkool Backported from master: 2022-03-04 Segher Boessenkool * config/rs6000/rs6000.c (rs6000_machine_from_flags): Restructure a bit. Handle most older CPUs. 2022-06-20 Jakub Jelinek Backported from master: 2022-06-18 Jakub Jelinek PR middle-end/105998 * varasm.c (narrowing_initializer_constant_valid_p): Check SCALAR_INT_MODE_P instead of INTEGRAL_MODE_P, also break on ! INTEGRAL_TYPE_P and do the same check also on op{0,1}'s type. 2022-06-20 Jan Hubicka Backported from master: 2022-06-14 Jan Hubicka PR ipa/105739 * ipa-prop.c (ipa_load_from_parm_agg): Punt on volatile loads. 2022-06-20 Jakub Jelinek Backported from master: 2022-05-27 Jakub Jelinek PR sanitizer/105729 * fold-const.c (fold_unary_loc): Don't optimize (X &) ((Y *) z + w) to (X &) z + w if -fsanitize=null during GENERIC folding. 2022-06-16 Richard Earnshaw Backported from master: 2022-06-15 Richard Earnshaw PR target/105981 * config/arm/arm.c (gen_cpymem_ldrd_strd): Rename low_reg and hi_reg to first_reg and second_reg respectively. Initialize them correctly when generating big-endian code. 2022-06-15 Simon Wright Backported from master: 2022-06-12 Simon Wright PR target/104871 * config/darwin-driver.c (darwin_find_version_from_kernel): If the OS version is darwin20 (macOS 11) or greater, truncate the version to the major number. 2022-06-15 Mark Mentovai Backported from master: 2022-06-12 Mark Mentovai * config/darwin-c.c: Make -mmacosx-version-min more future-proof. 2022-06-15 Richard Biener Backported from master: 2022-05-27 Richard Biener PR tree-optimization/105726 * gimple-ssa-warn-restrict.c (builtin_memref::set_base_and_offset): Constrain array-of-flexarray case more. 2022-06-14 Vladimir N. Makarov PR rtl-optimization/104637 * lra-assigns.c (lra_split_hard_reg_for): Split hard regs as many as possible on one subpass. 2022-06-13 Marek Polacek Backported from master: 2022-03-08 Marek Polacek PR rtl-optimization/104777 * rtl.c (classify_insn): For ASM_OPERANDS, return JUMP_INSN only if ASM_OPERANDS_LABEL_VEC has at least one element. 2022-06-09 Iain Sandoe Backported from master: 2021-09-14 Iain Sandoe * Makefile.in: Remove variables related to applying no-PIE to the exes on $build. * configure: Regenerate. * configure.ac: Remove configuration related to applying no-PIE to the exes on $build. 2022-06-06 Alan Modra Backported from master: 2020-10-24 Alan Modra * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Limit AND addressing to just lvx/stvx style addresses. 2022-05-31 Iain Sandoe * config/darwin-sections.def (objc2_class_names_section, objc2_method_names_section, objc2_method_types_section): New * config/darwin.c (output_objc_section_asm_op): Output new sections. (darwin_objc2_section): Select new sections where used. (darwin_label_is_anonymous_local_objc_name): Make protocol class methods linker-visible. 2022-05-29 Iain Sandoe Backported from master: 2021-11-15 Iain Sandoe PR fortran/102992 * config/darwin.h (TARGET_DTORS_FROM_CXA_ATEXIT): New. * doc/tm.texi: Regenerated. * doc/tm.texi.in: Add TARGET_DTORS_FROM_CXA_ATEXIT hook. * ipa.c (cgraph_build_static_cdtor_1): Return the built function decl. (build_cxa_atexit_decl): New. (build_dso_handle_decl): New. (build_cxa_dtor_registrations): New. (compare_cdtor_tu_order): New. (build_cxa_atexit_fns): New. (ipa_cdtor_merge): If dtors_from_cxa_atexit is set, process the DTORs/CTORs accordingly. (pass_ipa_cdtor_merge::gate): Also run if dtors_from_cxa_atexit is set. * target.def (dtors_from_cxa_atexit): New hook. 2022-05-29 Iain Sandoe Backported from master: 2021-07-09 Iain Sandoe PR target/100152 * config/i386/i386-expand.c (ix86_expand_call): If a call is to a non-local-binding, or local but to a public symbol, then assume that it might be indirected via the lazy symbol binder. Mark R10 and R10 as clobbered in that case. 2022-05-29 Iain Sandoe Vladimir Makarov PR target/104117 * config/rs6000/rs6000.c (darwin_rs6000_legitimate_lo_sum_const_p): Check for UNSPEC_MACHOPIC_OFFSET wrappers on symbolic addresses when emitting PIC code. (legitimate_lo_sum_address_p): Likewise. (rs6000_legitimize_address): Do not apply the TLS processing to Darwin. * config/rs6000/darwin.md (@machopic_high_): New. (@machopic_low_): New. * config/rs6000/predicates.md (macho_pic_address): New. 2022-05-29 Iain Sandoe PR target/80556 * config/darwin-driver.c (darwin_driver_init): Handle exported symbols and symbol lists (suppress automatic export of the TLS symbols). * config/darwin.c (darwin_rename_builtins): Remove workaround. * config/darwin.h (LINK_GCC_C_SEQUENCE_SPEC): Likewise. (REAL_LIBGCC_SPEC): Handle revised library uses. * config/darwin.opt (nodefaultexport): New. * config/i386/darwin.h (PR80556_WORKAROUND): Remove. * config/i386/darwin32-biarch.h (PR80556_WORKAROUND): Likewise. * config/i386/darwin64-biarch.h (PR80556_WORKAROUND): Likewise. 2022-05-29 Iain Sandoe * config/darwin-driver.c (darwin_driver_init): Revise comments, handle filelist and framework options in specs instead of code. Exit from the option handling early if the command line is definitely enpty. * config/darwin.h (SUBTARGET_DRIVER_SELF_SPECS): Update to handle link specs that are really driver ones. Remove setting for the default content of weak_reference_mismatches (DARWIN_CC1_SPEC): Likewise. (CPP_SPEC): Likewise. (SYSROOT_SPEC): Append space. (LINK_SYSROOT_SPEC): Remove most driver link specs. (STANDARD_STARTFILE_PREFIX_2): Update link-related specs. (STARTFILE_SPEC): Likewise. (ASM_MMACOSX_VERSION_MIN_SPEC): Fix line wrap. (ASM_SPEC): Update driver-related specs. (ASM_FINAL_SPEC): Likewise. (LINK_COMMAND_SPEC_A): Update 'r' handling to skip gomp and itm when r or nodefaultlibs is given. (DSYMUTIL_SPEC): Do not call dsymutil for '-r' link lines. Update ordering of exclusions, remove duplicate 'v' addition (collect2 will add this from the main command line). * config/darwin.opt: Remove now unused option aliases. * config/i386/darwin.h (EXTRA_ASM_OPTS): Ensure space after opt. (ASM_SPEC): Update driver-related specs. 2022-05-29 Iain Sandoe Backported from master: 2021-09-19 Iain Sandoe * config/darwin.h (LINK_COMMAND_SPEC_A): Use Darwin10 unwinder shim as a convenience library. 2022-05-29 Iain Sandoe Backported from master: 2021-10-13 Iain Sandoe * collect2.c (is_lto_object_file): Release simple-object resources, close files. 2022-05-29 Iain Sandoe Backported from master: 2021-11-05 Iain Sandoe * config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): Add LTRAMP to the list of symbol prefixes that must be made linker- visible. 2022-05-29 Iain Sandoe Backported from master: 2021-08-27 Iain Sandoe * config/darwin.c (finalize_ctors): Add a section-start linker- visible symbol. (finalize_dtors): Likewise. * config/darwin.h (MIN_LD64_INIT_TERM_START_LABELS): New. 2022-05-29 Iain Sandoe Backported from master: 2021-08-17 Iain Sandoe * config/darwin.c (darwin_file_end): Reset and reclaim the section names table at the end of compile. 2022-05-29 Iain Sandoe Backported from master: 2021-01-02 Iain Sandoe * config/darwin.h (MIN_LD64_NO_COAL_SECTS): Adjust. Amend handling for LD64_VERSION fallback defaults. 2022-05-29 Iain Sandoe * configure.ac: Handle --with-dsymutil in the same way as we do for the assembler and linker. (DEFAULT_DSYMUTIL): New. Extract the type and version for the dsymutil configured or found by the default searches. * config.in: Regenerated. * configure: Regenerated. * collect2.c (do_dsymutil): Handle locating dsymutil in the same way as for the assembler and linker. * config/darwin.h (DSYMUTIL): Delete. * gcc.c: Report a configured dsymutil correctly. * exec-tool.in: Allow for dsymutil. * doc/install.texi: Document --with-dsymutil. 2022-05-29 Iain Sandoe Backported from master: 2021-09-28 Iain Sandoe * config/rs6000/darwin.h (FIXED_R13): Add for PPC64. (FIRST_SAVED_GP_REGNO): Save from R13 even when it is one of the fixed regs. 2022-05-29 François-Xavier Coudert Backported from master: 2021-12-18 François-Xavier Coudert * config/darwin-driver.c: Make version code more future-proof. * config.gcc: Homogeneize darwin versions. * configure.ac: Homogeneize darwin versions. * configure: Regenerate. 2022-05-29 Saagar Jha Backported from master: 2021-10-27 Saagar Jha * config.gcc: Adjust for Darwin21. * config/darwin-c.c (macosx_version_as_macro): Likewise. * config/darwin-driver.c (validate_macosx_version_min): Likewise. (darwin_find_version_from_kernel): Likewise. 2022-05-29 Iain Sandoe Backported from master: 2021-08-17 Iain Sandoe PR target/100340 * config.in: Regenerate. * config/i386/darwin.h (EXTRA_ASM_OPTS): New (ASM_SPEC): Pass options to disable branch shortening where needed. * configure: Regenerate. * configure.ac: Detect versions of 'as' that support the optimisation which has the bug. 2022-05-29 Iain Sandoe Backported from master: 2022-03-04 Iain Sandoe * config/darwin.c (darwin_fold_builtin): Make fcode an int to avoid a mismatch with DECL_MD_FUNCTION_CODE(). 2022-05-27 Richard Biener Backported from master: 2022-04-13 Richard Biener PR tree-optimization/105250 * fold-const.c (fold_convertible_p): Revert r12-7979-geaaf77dd85c333, instead check for size equality of the vector types involved. 2022-05-27 Richard Biener Backported from master: 2022-04-04 Richard Biener PR middle-end/105140 * fold-const.c (fold_convertible_p): Allow a TYPE_P arg. 2022-05-27 Richard Biener Backported from master: 2022-04-06 Richard Biener PR tree-optimization/105163 * tree-ssa-reassoc.c (repropagate_negates): Avoid propagating negated abnormals. 2022-05-27 Richard Biener Backported from master: 2022-04-06 Richard Biener PR tree-optimization/105173 * tree-ssa-reassoc.c (find_insert_point): Get extra insert_before output argument and compute it. (insert_stmt_before_use): Adjust. (rewrite_expr_tree): Likewise. 2022-05-27 Richard Biener Backported from master: 2022-04-29 Richard Biener PR tree-optimization/105431 * tree-ssa-math-opts.c (powi_as_mults_1): Make n unsigned. (powi_as_mults): Use absu_hwi. (gimple_expand_builtin_powi): Remove now pointless n != -n check. 2022-05-27 Richard Biener Backported from master: 2022-04-25 Richard Biener PR tree-optimization/105368 * tree-ssa-math-opts.c (powi_cost): Use absu_hwi. 2022-05-27 Richard Biener Backported from master: 2022-05-11 Richard Biener PR rtl-optimization/105559 * cfgrtl.c (delete_insn_and_edges): Only perform search to BB_END for non-debug insns. 2022-05-23 Paul A. Clarke PR target/104257 * config/rs6000/bmi2intrin.h: Uglify local variables. * config/rs6000/emmintrin.h: Likewise. * config/rs6000/mm_malloc.h: Likewise. * config/rs6000/mmintrin.h: Likewise. * config/rs6000/pmmintrin.h: Likewise. * config/rs6000/tmmintrin.h: Likewise. * config/rs6000/xmmintrin.h: Likewise. 2022-05-16 Sebastian Pop PR target/105162 * config/aarch64/aarch64-protos.h (atomic_ool_names): Increase dimension of str array. * config/aarch64/aarch64.c (aarch64_atomic_ool_func): Call memmodel_from_int and handle MEMMODEL_SYNC_*. (DEF0): Add __aarch64_*_sync functions. 2022-05-10 Jakub Jelinek Backported from master: 2022-04-27 Jakub Jelinek PR sanitizer/105396 * asan.c (asan_redzone_buffer::emit_redzone_byte): Handle the case where offset is bigger than off but smaller than m_prev_offset + 32 bits by pushing one or more 0 bytes. Sink the m_shadow_bytes.safe_push (value); flush_if_full (); statements from all cases to the end of the function. 2022-05-10 Jakub Jelinek Backported from master: 2022-04-22 Jakub Jelinek PR rtl-optimization/105333 * rtlanal.c (replace_rtx): Use simplify_subreg or simplify_unary_operation if CONST_SCALAR_INT_P rather than just CONST_INT_P. 2022-05-10 Jakub Jelinek Backported from master: 2022-04-19 Jakub Jelinek PR target/105257 * config/sparc/sparc.c (epilogue_renumber): If ORIGINAL_REGNO, use gen_raw_REG instead of gen_rtx_REG and copy over also ORIGINAL_REGNO. Use return 0; instead of /* fallthrough */. 2022-05-10 Jakub Jelinek Backported from master: 2022-04-12 Jakub Jelinek PR target/105214 * config/i386/i386-expand.c (ix86_emit_i387_log1p): Call do_pending_stack_adjust. 2022-05-10 Jakub Jelinek Backported from master: 2022-04-12 Jakub Jelinek PR rtl-optimization/105211 * builtins.c (expand_builtin_int_roundingfn_2): If mathfn_built_in_1 fails for TREE_TYPE (arg), retry it with TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (fndecl))) and if even that fails, emit call normally. 2022-05-10 Jakub Jelinek Backported from master: 2022-04-08 Jakub Jelinek PR tree-optimization/105189 * fold-const.c (make_range_step): Fix up handling of (unsigned) x +[low, -] ranges for signed x if low fits into typeof (x). 2022-05-10 Jakub Jelinek Backported from master: 2022-04-06 Jakub Jelinek PR rtl-optimization/104985 * combine.c (struct undo): Add where.regno member. (do_SUBST_MODE): Rename to ... (subst_mode): ... this. Change first argument from rtx * into int, operate on regno_reg_rtx[regno] and save regno into where.regno. (SUBST_MODE): Remove. (try_combine): Use subst_mode instead of SUBST_MODE, change first argument from regno_reg_rtx[whatever] to whatever. For UNDO_MODE, use regno_reg_rtx[undo->where.regno] instead of *undo->where.r. (undo_to_marker): For UNDO_MODE, use regno_reg_rtx[undo->where.regno] instead of *undo->where.r. (simplify_set): Use subst_mode instead of SUBST_MODE, change first argument from regno_reg_rtx[whatever] to whatever. 2022-05-10 Jakub Jelinek Backported from master: 2022-04-03 Jakub Jelinek PR target/105123 * config/i386/i386-expand.c (ix86_expand_vector_init_general): Avoid using word as target for expand_simple_binop when doing ASHIFT and IOR. 2022-05-10 Jakub Jelinek Backported from master: 2022-03-30 Jakub Jelinek PR sanitizer/105093 * ubsan.c (instrument_object_size): If t is equal to inner and is a decl other than global var, punt. When emitting call to UBSAN_OBJECT_SIZE ifn, make sure base is addressable. 2022-05-10 Jakub Jelinek Backported from master: 2022-03-30 Jakub Jelinek PR tree-optimization/105094 * gimple-ssa-store-merging.c (mem_valid_for_store_merging): Punt if bitsize <= 0 rather than just == 0. 2022-05-10 Jakub Jelinek Backported from master: 2022-03-19 Jakub Jelinek PR middle-end/104971 * config/i386/i386-expand.c (ix86_expand_builtin) : If ignore, don't push/pop anything and just return const0_rtx. 2022-05-10 Jakub Jelinek Backported from master: 2022-03-16 Jakub Jelinek PR target/104910 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Copy imm rtx. 2022-05-10 Jakub Jelinek Backported from master: 2022-03-15 Jakub Jelinek PR rtl-optimization/104814 * ifcvt.c (find_if_case_1, find_if_case_2): Punt if test_bb doesn't end with onlyjump_p. Assume BB_END (test_bb) is always non-NULL. 2022-05-10 Jakub Jelinek Backported from master: 2022-03-09 Jakub Jelinek PR c/104711 * doc/invoke.texi (-Wextra): Document that -Wshift-negative-value is enabled by it only for C++11 to C++17 rather than for C++03 or later. (-Wshift-negative-value): Similarly (except here we stated that it is enabled for C++11 or later). 2022-05-10 Jakub Jelinek Backported from master: 2022-03-07 Jakub Jelinek PR target/104775 * config/s390/s390.md (*cmp_and_trap_unsigned_int): Use S constraint instead of T in the last alternative. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-25 Jakub Jelinek Marc Glisse PR tree-optimization/104675 * match.pd (t * 2U / 2 -> t & (~0 / 2), t / 2U * 2 -> t & ~1): Restrict simplifications to INTEGRAL_TYPE_P. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-25 Jakub Jelinek PR target/104681 * config/rs6000/vector.md (movmisalign): Use rs6000_emit_move. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-25 Jakub Jelinek PR tree-optimization/104675 * match.pd (-A - 1 -> ~A, -1 - A -> ~A): Don't simplify for COMPLEX_TYPE. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-19 Jakub Jelinek PR sanitizer/102656 * asan.c (instrument_derefs): If inner is a RESULT_DECL and access is known to be within bounds, treat it like automatic variables. If instrumenting access and inner is {VAR,PARM,RESULT}_DECL from current function and !TREE_STATIC which is not TREE_ADDRESSABLE, mark it addressable. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-17 Jakub Jelinek PR debug/104557 * valtrack.c (debug_lowpart_subreg): Don't call gen_rtx_raw_SUBREG if expr has VOIDmode. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-16 Jakub Jelinek PR rtl-optimization/104544 * combine.c (try_combine): When looking for insn whose links should be updated from i3 to i2, don't stop on debug insns, instead skip over them. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-15 Jakub Jelinek PR debug/104517 * omp-low.c (task_cpyfns): New variable. (delete_omp_context): Don't call finalize_task_copyfn from here. (create_task_copyfn): Push task_stmt into task_cpyfns. (execute_lower_omp): Call finalize_task_copyfn here on entries from task_cpyfns vector and release the vector. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-12 Jakub Jelinek PR sanitizer/104449 * asan.c: Include tree-eh.h. (handle_builtin_alloca): Handle the case when __builtin_alloca or __builtin_alloca_with_align can throw. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-12 Jakub Jelinek PR target/104502 * config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+ and AVX512VL isn't available, move operands[1] to operands[0] first. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-11 Jakub Jelinek PR middle-end/104446 * combine.c (subst): Don't substitute CONST_INTs into RTX_AUTOINC operands. 2022-05-10 Jakub Jelinek Backported from master: 2022-02-08 Jakub Jelinek PR target/102140 * config/rs6000/rs6000.c (vspltis_shifted): Return false also if split1 pass has finished already. 2022-05-10 Jakub Jelinek Backported from master: 2022-01-28 Jakub Jelinek PR tree-optimization/104263 * gimple-ssa-store-merging.c (get_status_for_store_merging): For cfun->can_throw_non_call_exceptions && cfun->eh test whether last non-debug stmt in the bb is store_valid_for_store_merging_p rather than last stmt. 2022-05-10 Jakub Jelinek Backported from master: 2022-01-21 Jakub Jelinek PR rtl-optimization/102478 * optabs.c (prepare_cmp_insn): If !can_create_pseudo_p (), don't force_reg constants and for -fnon-call-exceptions fail if copy_to_reg would be needed. 2022-05-10 Jakub Jelinek Backported from master: 2022-01-19 Jakub Jelinek PR middle-end/102860 * match.pd (x %[fl] y -> x % y): New simplification for unsigned integral types. * optabs-tree.c (optab_for_tree_code): Return unknown_optab for {CEIL,FLOOR,ROUND}_{DIV,MOD}_EXPR with VECTOR_TYPE. 2022-05-10 Jakub Jelinek Backported from master: 2022-01-06 Jakub Jelinek PR rtl-optimization/103908 * ifcvt.c (bb_valid_for_noce_process_p): Punt on bbs ending with asm goto. 2022-05-10 Jakub Jelinek Backported from master: 2021-12-30 Jakub Jelinek PR rtl-optimization/103860 * shrink-wrap.c (try_shrink_wrapping): Make sure can_get_prologue is called on pro even if nothing further is pushed into vec. 2022-05-10 Jakub Jelinek Backported from master: 2021-12-28 Jakub Jelinek PR rtl-optimization/103837 * loop-invariant.c (can_move_invariant_reg): Ignore DEBUG_INSNs in the decisions whether to return false or continue and right before returning true reset those debug insns that previously caused returning false. 2022-05-10 Jakub Jelinek Backported from master: 2021-11-27 Jakub Jelinek PR tree-optimization/103435 * gimple-ssa-store-merging.c (find_bswap_or_nop_finalize): Avoid UB if n->range - rsize == 8, just clear both *cmpnop and *cmpxchg in that case. 2022-05-10 Jakub Jelinek Backported from master: 2021-11-24 Jakub Jelinek PR middle-end/103384 * omp-general.c (omp_context_selector_matches): For ACCEL_COMPILER, return 0 for kind(host) and continue for kind(nohost). 2022-05-10 Jakub Jelinek Backported from master: 2021-11-23 Jakub Jelinek PR middle-end/102431 * gimplify.c (replace_reduction_placeholders): Remove. (note_no_context_vars): New function. (gimplify_omp_loop): For OMP_PARALLEL's BIND_EXPR create a new BLOCK. Use copy_tree_body_r with walk_tree instead of unshare_expr and replace_reduction_placeholders for duplication of OMP_CLAUSE_REDUCTION_{INIT,MERGE} expressions. Ensure all mentioned automatic vars have DECL_CONTEXT set to non-NULL before doing so and reset it afterwards for those vars and their corresponding vars. 2022-05-10 Jakub Jelinek Backported from master: 2021-11-17 Jakub Jelinek PR tree-optimization/103192 * tree-ssa-loop-im.c (move_computations_worker): Use reset_flow_sensitive_info instead of manually clearing SSA_NAME_RANGE_INFO and do it for all SSA_NAMEs, not just ones with integral types. 2022-05-10 Jakub Jelinek Backported from master: 2021-11-15 Jakub Jelinek PR target/103205 * config/i386/sync.md (atomic_bit_test_and_set, atomic_bit_test_and_complement, atomic_bit_test_and_reset): Use OPTAB_WIDEN instead of OPTAB_DIRECT. 2022-05-10 Jakub Jelinek Backported from master: 2021-11-11 Jakub Jelinek PR debug/101378 * dwarf2out.c (field_byte_offset): Do the PCC_BITFIELD_TYPE_MATTERS handling only for DECL_BIT_FIELD_TYPE decls. 2022-05-10 Jakub Jelinek Backported from master: 2021-10-10 Jakub Jelinek PR debug/102441 * var-tracking.c (add_stores): For cselib_sp_derived_value_p values use MO_VAL_SET if loc is not sp. 2022-05-10 Jakub Jelinek Backported from master: 2021-09-28 Jakub Jelinek PR target/102498 * config/i386/i386.c (standard_80387_constant_p): Don't recognize special 80387 instruction XFmode constants if flag_rounding_math. 2022-05-10 Jakub Jelinek Backported from master: 2021-09-15 Jakub Jelinek PR c++/88578 PR c++/102295 * varasm.c (output_constructor_regular_field): Instead of assertion that array_size_for_constructor result is equal to size of TREE_TYPE (local->val) in bytes, assert that the type size is greater or equal to array_size_for_constructor result and use type size as fieldsize. 2022-05-10 Jakub Jelinek Backported from master: 2021-09-08 Jakub Jelinek PR target/102224 * config/i386/i386.md (xorsign3): If operands[1] is equal to operands[2], emit abs2 instead. (@xorsign3_1): Add early-clobber for output operand. 2022-05-10 Jakub Jelinek Backported from master: 2021-08-23 Jakub Jelinek PR debug/101905 * dwarf2out.c (gen_variable_die): Add DW_AT_location for global register variables already during early_dwarf if possible. 2022-05-10 Jakub Jelinek Backported from master: 2021-07-28 Jakub Jelinek PR middle-end/101624 * ubsan.c (maybe_instrument_pointer_overflow, instrument_object_size): Only test DECL_REGISTER on VAR_DECLs, PARM_DECLs or RESULT_DECLs. * sanopt.c (maybe_optimize_ubsan_ptr_ifn): Likewise. 2022-05-10 Jakub Jelinek Backported from master: 2021-07-23 Jakub Jelinek PR rtl-optimization/101562 * expmed.c (store_integral_bit_field): Only use movstrict_optab if the operand isn't paradoxical. 2022-05-10 Jakub Jelinek Backported from master: 2021-07-21 Jakub Jelinek PR middle-end/101535 * gimplify.c (omp_check_private): Properly skip ORT_TARGET_DATA contexts in which decl isn't privatized and for ORT_TARGET return false if decl is mapped. 2022-05-10 Jakub Jelinek Backported from master: 2021-07-20 Jakub Jelinek PR target/101384 * config/rs6000/rs6000.c (vspltis_constant): Accept EASY_VECTOR_MSB only if step and copies are equal to 1. 2022-05-10 Jakub Jelinek Backported from master: 2021-07-01 Jakub Jelinek PR middle-end/94366 * omp-low.c (lower_rec_input_clauses): Rename is_fp_and_or to is_truth_op, set it for TRUTH_*IF_EXPR regardless of new_var's type, use boolean_type_node instead of integer_type_node as NE_EXPR type. (lower_reduction_clauses): Likewise. 2022-05-10 Tobias Burnus Backported from master: 2021-05-04 Tobias Burnus * omp-low.c (lower_rec_input_clauses, lower_reduction_clauses): Handle && and || with floating-point and complex arguments. 2022-05-10 Jakub Jelinek Backported from master: 2021-07-14 Jakub Jelinek PR go/101407 * godump.c (godump_str_hash): New type. (godump_container::pot_dummy_types): Use string_hash instead of ptr_hash in the hash_set. 2022-05-10 Jakub Jelinek Backported from master: 2021-07-01 Jakub Jelinek PR debug/101266 * dwarf2out.c (loc_list_from_tree_1): Handle COMPOUND_LITERAL_EXPR. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-29 Jakub Jelinek PR c++/101210 * match.pd ((intptr_t)x eq/ne CST to x eq/ne (typeof x) CST): Don't perform the optimization in GENERIC when sanitizing and x has a reference type. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-23 Jakub Jelinek PR middle-end/101167 * omp-low.c (lower_omp_regimplify_p): Regimplify also PARM_DECLs and RESULT_DECLs that have DECL_HAS_VALUE_EXPR_P set. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-21 Jakub Jelinek PR inline-asm/100785 * cfgexpand.c (expand_asm_stmt): If errors are emitted, remove all inputs, outputs and clobbers from the asm and set template to "". 2022-05-10 Jakub Jelinek Backported from master: 2021-06-18 Jakub Jelinek PR middle-end/101062 * stor-layout.c (finish_bitfield_layout): Don't add bitfield representatives in QUAL_UNION_TYPE. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-16 Jakub Jelinek PR middle-end/101062 * stor-layout.c (finish_bitfield_representative): For fields in unions assume nextf is always NULL. (finish_bitfield_layout): Compute bit field representatives also in unions, but handle it as if each bitfield was the only field in the aggregate. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-15 Jakub Jelinek PR target/101046 * expr.c (expand_expr_real_2) : Clear subtarget when changing mode. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-11 Jakub Jelinek PR rtl-optimization/101008 * simplify-rtx.c (relational_result): New function. (simplify_logical_relational_operation, simplify_relational_operation): Use it. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-07 Jakub Jelinek PR target/100887 * fold-const.c (fold_read_from_vector): Return NULL if trying to read from a CONSTRUCTOR with vector type elements. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-07 Jakub Jelinek PR middle-end/100898 * tree-inline.c (copy_bb): Only use gimple_call_arg_ptr if memcpy should copy any arguments. Don't call gimple_call_num_args on id->call_stmt or call_stmt more than once. 2022-05-10 Jakub Jelinek Backported from master: 2021-06-04 Jakub Jelinek PR target/100887 * config/i386/i386-expand.c (ix86_expand_vector_init): Handle concatenation from half-sized modes with TImode elements. 2022-05-10 Jakub Jelinek Backported from master: 2021-05-18 Jakub Jelinek PR c++/100580 * function.c (push_dummy_function): Set DECL_ARTIFICIAL and DECL_ASSEMBLER_NAME on the fn_decl. 2022-05-10 Jakub Jelinek Backported from master: 2021-05-15 Jakub Jelinek PR rtl-optimization/100342 * regcprop.c (copy_value): When copying a source reg in a wider mode than it has recorded for the value, adjust recorded destination mode too or punt if !REG_CAN_CHANGE_MODE_P. 2022-05-10 liuhongt Backported from master: 2021-01-21 liuhongt PR rtl-optimization/98694 * regcprop.c (copy_value): If SRC had been assigned a mode narrower than the copy, we can't link DEST into the chain even they have same hard_regno_nregs(i.e. HImode/SImode in i386 backend). 2022-05-10 Jakub Jelinek Backported from master: 2021-05-12 Jakub Jelinek PR middle-end/100508 * cfgexpand.c (expand_debug_expr): For DEBUG_EXPR_DECL with vector type, don't reuse DECL_RTL if it has different mode, instead force creation of a new DEBUG_EXPR. 2022-05-10 Jakub Jelinek Backported from master: 2021-05-11 Jakub Jelinek PR middle-end/100471 * omp-low.c (lower_omp_task_reductions): For OMP_TASKLOOP, if data is 0, bypass the reduction loop including GOMP_taskgroup_reduction_unregister call. 2022-05-10 Eric Botcazou PR target/105292 * config/sparc/sparc.c (sparc_vectorize_vec_perm_const): Return true only for 8-byte vector modes. 2022-05-06 Michael Meissner Backported from master: 2022-05-06 Michael Meissner PR target/102059 * config/rs6000/rs6000.c (rs6000_can_inline_p): Ignore -mpower8-fusion option for inlining purposes. 2022-05-06 Richard Biener Backported from master: 2022-04-08 Richard Biener PR tree-optimization/105198 * tree-predcom.c (find_looparound_phi): Check whether the found memory location of the entry value is clobbered inbetween the value we want to use and loop entry. 2022-05-06 Richard Biener Backported from master: 2022-02-07 Richard Biener PR middle-end/104402 * gimple-expr.c (is_gimple_condexpr): _Complex typed compares are not valid. * tree-cfg.c (verify_gimple_assign_ternary): For COND_EXPR check is_gimple_condexpr. 2022-04-27 Hongyu Wang Backported from master: 2022-04-25 Hongyu Wang PR target/105339 * config/i386/avx512fintrin.h (_mm512_scalef_round_pd): Add parentheses for parameters and djust format. (_mm512_mask_scalef_round_pd): Ditto. (_mm512_maskz_scalef_round_pd): Ditto. (_mm512_scalef_round_ps): Ditto. (_mm512_mask_scalef_round_ps): Ditto. (_mm512_maskz_scalef_round_ps): Ditto. (_mm_scalef_round_sd): Use _mm_undefined_pd. (_mm_scalef_round_ss): Use _mm_undefined_ps. (_mm_mask_scalef_round_sd): New macro. (_mm_mask_scalef_round_ss): Ditto. (_mm_maskz_scalef_round_sd): Ditto. (_mm_maskz_scalef_round_ss): Ditto. 2022-04-21 Richard Biener Backported from master: 2022-01-20 Richard Biener PR middle-end/100786 * gimple-fold.c (get_symbol_constant_value): Only return values of compatible type to the symbol. 2022-04-21 Richard Biener Backported from master: 2021-11-23 Richard Biener PR tree-optimization/103361 * gimple-loop-jam.c (adjust_unroll_factor): Use lambda_int for the dependence distance. * tree-data-ref.c (print_lambda_vector): Properly print a lambda_int. 2022-04-21 Richard Biener Backported from master: 2021-12-07 Richard Biener PR tree-optimization/103596 * tree-ssa-sccvn.c (eliminate_dom_walker::eliminate_stmt): Note we are not propagating into a PHI argument to may_propagate_copy. * tree-ssa-propagate.h (may_propagate_copy): Add argument specifying whether we propagate into a PHI arg. * tree-ssa-propagate.c (may_propagate_copy): Likewise. When not doing so we can replace an abnormal with something else. (may_propagate_into_stmt): Update may_propagate_copy calls. (replace_exp_1): Move propagation checking code to propagate_value and rename to ... (replace_exp): ... this and elide previous wrapper. (propagate_value): Perform checking with adjusted may_propagate_copy call and dispatch to replace_exp. 2022-04-21 Richard Biener Backported from master: 2022-02-03 Richard Biener PR debug/104337 * tree-nrv.c (pass_nrv::execute): Remove tieing result and found together via DECL_ABSTRACT_ORIGIN. 2022-04-21 Richard Biener Backported from master: 2022-03-09 Richard Biener PR middle-end/104786 * cfgexpand.c (expand_asm_stmt): Do not generate a copy for VLAs without an upper size bound. 2022-04-21 Richard Biener Backported from master: 2022-04-12 Richard Biener PR tree-optimization/105226 * tree-vect-loop-manip.c (vect_loop_versioning): Verify we can split the exit of an outer loop we choose to version. 2022-04-21 Richard Biener Backported from master: 2022-03-28 Richard Biener PR tree-optimization/105070 * tree-switch-conversion.h (bit_test_cluster::hoist_edge_and_branch_if_true): Add location argument. * tree-switch-conversion.c (bit_test_cluster::hoist_edge_and_branch_if_true): Annotate cond with location. (bit_test_cluster::emit): Annotate all generated expressions with location. 2022-04-05 Martin Jambor Backported from master: 2022-03-31 Martin Jambor PR ipa/103083 * ipa-prop.h (ipa_ancestor_jf_data): New flag keep_null; (ipa_get_jf_ancestor_keep_null): New function. * ipa-prop.c (ipa_set_ancestor_jf): Initialize keep_null field of the ancestor function. (compute_complex_assign_jump_func): Pass false to keep_null parameter of ipa_set_ancestor_jf. (compute_complex_ancestor_jump_func): Pass true to keep_null parameter of ipa_set_ancestor_jf. (update_jump_functions_after_inlining): Carry over keep_null from the original ancestor jump-function or merge them. (ipa_write_jump_function): Stream keep_null flag. (ipa_read_jump_function): Likewise. (ipa_print_node_jump_functions_for_edge): Print the new flag. * ipa-cp.c (class ipcp_bits_lattice): Make various getters const. New member function known_nonzero_p. (ipcp_bits_lattice::known_nonzero_p): New. (ipcp_bits_lattice::meet_with_1): New parameter drop_all_ones, observe it. (ipcp_bits_lattice::meet_with): Likewise. (propagate_bits_across_jump_function): Simplify. Pass true in drop_all_ones when it is necessary. (propagate_aggs_across_jump_function): Take care of keep_null flag. (ipa_get_jf_ancestor_result): Propagate NULL accross keep_null jump functions. 2022-03-26 H.J. Lu Backported from master: 2022-03-26 H.J. Lu PR target/105052 * config/i386/sse.md (ssse3_phwv4hi3): Replace "Yv" with "x". (ssse3_phdv2si3): Likewise. (ssse3_psign3): Likewise. 2022-03-18 Peter Bergner Backported from master: 2022-03-04 Peter Bergner PR target/87496 PR target/104208 * config/rs6000/rs6000.c (rs6000_option_override_internal): Make the ISA 2.06 requirement for -mabi=ieeelongdouble conditional on -mlong-double-128. Move the -mabi=ieeelongdouble and -mabi=ibmlongdouble error checking from here... * common/config/rs6000/rs6000-common.c (rs6000_handle_option): ... to here. 2022-03-16 Richard Biener Backported from master: 2022-02-09 Richard Biener PR target/104453 * config/i386/i386.c (ix86_gimple_fold_builtin): Guard shift folding for NULL LHS. 2022-03-16 Richard Biener Backported from master: 2022-02-14 Richard Biener PR tree-optimization/104511 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid touching DFP <-> FP conversions. 2022-03-16 Richard Biener Backported from master: 2022-01-20 Richard Biener PR target/100784 * config/i386/i386.c (ix86_gimple_fold_builtin): Check for LHS before folding __builtin_ia32_shufpd and friends. 2022-03-12 Michael Meissner PR target/99708 * config/rs6000/rs6000-c.c: Revert 2022-03-05 patch. 2022-03-06 Michael Meissner PR target/104253 * config/rs6000/rs6000.c (init_float128_ibm): Update the conversion functions used to convert IFmode types. Backport change made to the master branch on 2022-02-14. 2022-03-06 Michael Meissner PR target/99708 * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define __SIZEOF_IBM128__ if the IBM 128-bit long double type is created. Define __SIZEOF_FLOAT128__ if the IEEE 128-bit floating point type is created. Backport change to master branch on 2022-02-17. 2022-02-17 Richard Biener Backported from master: 2021-11-15 Richard Biener PR tree-optimization/103237 * tree-vect-loop.c (vect_is_simple_reduction): Fail for double reductions with multiple inner loop LC PHI nodes. 2022-02-17 Richard Biener Backported from master: 2021-11-22 Richard Biener PR middle-end/103181 PR middle-end/103248 * tree-eh.c (operation_could_trap_helper_p): Properly check vector constants for a zero element for integer division. Separate floating point and integer division code. Properly handle fixed-point RDIV_EXPR. 2022-02-17 Richard Biener Backported from master: 2021-11-08 Richard Biener PR tree-optimization/102798 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Only copy points-to info to newly generated SSA names. 2022-02-17 Richard Biener Backported from master: 2021-10-15 Richard Biener PR ipa/102762 * tree-inline.c (copy_bb): Avoid underflowing nargs. 2022-02-17 Richard Biener Backported from master: 2021-06-08 Richard Biener PR tree-optimization/100923 * tree-ssa-sccvn.c (valueize_refs_1): Take a pointer to the operand vector to be valueized. (valueize_refs): Likewise. (valueize_shared_reference_ops_from_ref): Adjust. (valueize_shared_reference_ops_from_call): Likewise. (vn_reference_lookup_3): Likewise. (vn_reference_lookup_pieces): Likewise. Re-valueize with honoring availability when we are about to create the ao_ref and valueized before. (vn_reference_lookup): Likewise. (vn_reference_insert_pieces): Adjust. 2022-02-17 Richard Biener Backported from master: 2021-06-22 Richard Biener PR tree-optimization/101158 * tree-vect-slp.c (vect_build_slp_tree_1): Move same operand checking after checking for matching operation. 2022-02-15 Kewen Lin Backported from master: 2022-02-07 Kewen Lin PR target/103627 * config/rs6000/rs6000.c (rs6000_option_override_internal): Move the hunk affecting VSX and ALTIVEC to appropriate place. 2022-02-15 Kewen Lin Backported from master: 2022-02-07 Kewen Lin PR target/103627 * config/rs6000/rs6000.c (rs6000_option_override_internal): Disable MMA if !TARGET_VSX. 2022-02-14 Maciej W. Rozycki Backported from master: 2022-02-08 Maciej W. Rozycki * config/riscv/t-riscv (riscv-sr.o): Add $(TM_H) dependency. 2022-02-13 Alan Modra Backported from master: 2020-10-01 Alan Modra * config/rs6000/ppc-asm.h: Support __PCREL__ code. 2022-02-10 Uros Bizjak Backported from master: 2022-02-10 Uroš Bizjak PR target/104469 * config/i386/sse.md (vec_unpacks_float_lo_v4si): Change operand 1 constraint to register_operand. 2022-02-09 Uroš Bizjak PR target/104458 * config/i386/i386-expand.c (ix86_split_idivmod): Force operands[2] and operands[3] into a register.. 2022-02-09 liuhongt PR target/104451 * config/i386/sse.md (3): lowpart_subreg operands[2] from SImode to QImode. 2022-02-03 Sebastian Huber PR target/104090 * config/rs6000/rs6000.c (rs6000_machine_from_flags): Use also rs6000_cpu. 2022-02-02 Xi Ruoyao Backported from master: 2022-02-01 Xi Ruoyao PR middle-end/95115 * fold-const.c (const_binop): Do not fold NaN result from non-NaN operands. 2022-01-15 Peter Bergner Backported from master: 2021-11-16 Peter Bergner PR target/102976 * config/rs6000/mma.md (*vsx_assemble_pair): Add early-clobber for output operand. (*mma_assemble_acc): Likewise. 2022-01-15 Peter Bergner * config/rs6000/mma.md (UNSPEC_VSX_ASSEMBLE): New unspec. (vsx_assemble_pair): Use mma_assemble_input_operand. Expand into UNSPEC_VSX_ASSEMBLE wrapper. (*vsx_assemble_pair): New define_insn_and_split. * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle UNSPEC_VSX_ASSEMBLE. 2022-01-15 Peter Bergner Backported from master: 2021-09-14 Peter Bergner * config/rs6000/mma.md (unspecv): Add UNSPECV_MMA_XXSETACCZ. (*movpxi): Remove 'O' alternative. (mma_xxsetaccz): Change to define_insn. Use UNSPECV_MMA_XXSETACCZ. Add comment. * config/rs6000/rs6000.c (rs6000_rtx_costs): Handle UNSPEC_VOLATILE. 2022-01-14 Eric Botcazou * ipa-param-manipulation.c (ipa_dump_adjusted_parameters): Dump reverse flag as "reverse" for the sake of consistency. * ipa-sra.c: Fix copyright year. (ipa_sra_function_summaries::duplicate): Copy the reverse flag. (dump_isra_access): Tweak dump line. (isra_write_node_summary): Write the reverse flag. (isra_read_node_info): Read it. (pull_accesses_from_callee): Test its consistency and copy it. 2022-01-12 Richard Biener Backported from master: 2020-11-26 Richard Biener PR tree-optimization/97953 * gimple-ssa-evrp-analyze.c (evrp_range_analyzer::record_ranges_from_incoming_edge): Make sure the condition post-dominates the SSA definition before recording into SSA_NAME_RANGE_INFO. 2022-01-10 Eric Botcazou PR target/103465 * coretypes.h (unwind_info_type): Swap UI_SEH and UI_TARGET. 2021-12-16 Martin Liska Backported from master: 2021-12-15 Martin Liska PR target/103661 * config/i386/i386-builtins.c (fold_builtin_cpu): Compare to 0 as API expects that non-zero values are returned (do that it mask == 31). For "avx512vbmi2" argument, we return now 1 << 31, which is a negative integer value. 2021-12-15 Kewen Lin Backported from master: 2021-11-30 Kewen Lin PR target/102347 * config/rs6000/rs6000-call.c (rs6000_builtin_decl): Remove builtin mask check. 2021-12-01 Martin Jambor Backported from master: 2021-11-30 Martin Jambor PR ipa/103267 * ipa-sra.c (scan_function): Also check ECF_LOOPING_CONST_OR_PURE flag. 2021-11-30 Eric Botcazou PR target/103274 * config/i386/i386.c (ix86_output_call_insn): Beef up comment about nops emitted with SEH. * config/i386/winnt.c (i386_pe_seh_unwind_emit): When switching to the cold section, emit a nop before the directive if the previous active instruction is a call. 2021-11-25 Jan Hubicka Backported from master: 2021-11-20 Jan Hubicka PR ipa/103052 * ipa-pure-const.c (propagate_pure_const): Fix merging of loping flag. 2021-11-23 Bill Schmidt PR target/101985 * config/rs6000/altivec.h (vec_cpsgn): Swap operand order. 2021-11-22 Stefan Schulze Frielinghaus Backported from master: 2021-11-19 Stefan Schulze Frielinghaus * config/s390/s390.md (define_peephole2): Variable insn points to the first matched insn. Use peep2_next_insn(1) to refer to the second matched insn. 2021-11-15 Kewen Lin Backported from master: 2021-11-11 Kewen Lin * doc/invoke.texi: Change references to "future cpu" to "power10", "-mcpu=future" to "-mcpu=power10". Adjust words for float128. 2021-11-09 Richard Biener Backported from master: 2021-10-13 Richard Biener PR ipa/102714 * ipa-sra.c (ptr_parm_has_nonarg_uses): Fix volatileness check. 2021-11-09 Richard Biener Backported from master: 2021-05-19 Richard Biener PR middle-end/100672 * fold-const.c (fold_negate_expr_1): Use element_precision. (negate_expr_p): Likewise. 2021-11-09 Richard Biener PR tree-optimization/100253 * tree-vect-stmts.c (vectorizable_load): Do not assume element alignment when DR_MISALIGNMENT is -1. (vectorizable_store): Likewise. 2021-11-08 Kewen Lin Backported from master: 2021-10-26 Kewen Lin PR tree-optimization/102789 * tree-vect-loop-manip.c (vect_update_inits_of_drs): Do not update inits of simd_lane_access. 2021-11-03 Vladimir N. Makarov PR rtl-optimization/102842 * lra-constraints.c (match_reload): Ignore out in checking values of outs. (curr_insn_transform): Collect outputs before doing reloads of operands. 2021-11-02 Martin Jambor Backported from master: 2021-10-21 Martin Jambor PR tree-optimization/102505 * tree-sra.c (totally_scalarize_subtree): Check that the encountered field fits within the acces we would like to put it in. 2021-10-28 Eric Botcazou * doc/invoke.texi (%X): Remove obsolete reference to -Wl. 2021-10-27 Uroš Bizjak PR target/102761 * config/i386/i386.c (ix86_print_operand_address): Error out for non-address_operand asm operands. 2021-10-26 Piotr Kubaj Backported from master: 2021-10-16 Piotr Kubaj * configure.ac: Treat powerpc64*-*-freebsd* the same as powerpc64-*-freebsd*. * configure: Regenerate. 2021-10-24 John David Anglin * config/pa/pa.md: Don't use 'G' constraint in integer move patterns. 2021-10-21 H.J. Lu Backported from master: 2021-10-21 H.J. Lu PR target/98667 * doc/invoke.texi: Document -fcf-protection requires i686 or new. 2021-10-15 John David Anglin * config/pa/pa.md: Consistently use "rG" constraint for copy instruction in move patterns. 2021-10-14 John David Anglin * config/pa/pa.md (cbranchsf4): Disable if TARGET_SOFT_FLOAT. (cbranchdf4): Likewise. Add missing move patterns for TARGET_SOFT_FLOAT. 2021-10-13 John David Anglin * config/pa/pa.md (muldi3): Add support for inlining 64-bit multiplication on 32-bit PA 1.1 and 2.0 targets. 2021-10-13 Richard Biener Backported from master: 2021-08-25 Richard Biener PR tree-optimization/102046 * tree-vect-slp.c (vect_build_slp_tree_2): Conservatively update ->any_pattern when swapping operands. 2021-10-13 Richard Biener Backported from master: 2021-08-17 Richard Biener PR tree-optimization/101925 * tree-ssa-sccvn.c (copy_reference_ops_from_ref): Set reverse on COMPONENT_REF and ARRAY_REF according to what reverse_storage_order_for_component_p does. (vn_reference_eq): Compare reversed on reference ops. (reverse_storage_order_for_component_p): New overload. (vn_reference_lookup_3): Check reverse_storage_order_for_component_p on the reference looked up. 2021-10-13 Richard Biener Backported from master: 2021-08-17 Richard Biener PR tree-optimization/101373 PR tree-optimization/101868 * tree-ssa-pre.c (prune_clobbered_mems): Also prune trapping references when the BB may not return. 2021-10-13 Richard Biener Backported from master: 2021-08-10 Richard Biener PR middle-end/101824 * tree-nested.c (get_frame_field): Mark the COMPONENT_REF as volatile in case the variable was. 2021-10-12 Eric Botcazou PR target/102588 * config/sparc/sparc-modes.def (OI): New integer mode. 2021-10-11 Diane Meirowitz Backported from master: 2021-10-11 Diane Meirowitz * doc/invoke.texi: Add link to UndefinedBehaviorSanitizer documentation, mention UBSAN_OPTIONS, similar to what is done for AddressSanitizer. 2021-10-11 Andrew Pinski PR tree-optimization/102622 * tree-ssa-phiopt.c (conditional_replacement): Set neg to false for one bit signed types. 2021-10-01 Eric Botcazou * explow.c: Include langhooks.h. (set_stack_check_libfunc): Build a proper function type. 2021-10-01 Eric Botcazou PR c++/64697 * config/i386/i386.c (legitimate_pic_address_disp_p): For PE-COFF do not return true for external weak function symbols in medium model. 2021-09-22 Kewen Lin Backported from master: 2021-09-22 Kewen Lin * ipa-fnsummary.c (inline_read_section): Unpack a dummy bit to keep consistent with the side of streaming out. 2021-09-21 Segher Boessenkool Backported from master: 2021-09-08 Segher Boessenkool PR target/102107 * config/rs6000/rs6000-logue.c (rs6000_emit_epilogue): For ELFv2 use r11 instead of r12 for restoring CR. 2021-09-21 Segher Boessenkool Backported from master: 2021-09-03 Segher Boessenkool PR target/102107 * config/rs6000/rs6000-logue.c (rs6000_emit_prologue): On ELFv2 use r11 instead of r12 for CR save, in all cases. 2021-09-17 Eric Botcazou PR rtl-optimization/102306 * combine.c (try_combine): Abort the combination if we are about to duplicate volatile references. 2021-09-16 Daniel Cederman * config/sparc/sparc-opts.h (enum sparc_processor_type): Add LEON5 * config/sparc/sparc.c (struct processor_costs): Add LEON5 costs (leon5_adjust_cost): Increase cost of store with data dependency on ALU instruction and FPU anti-dependencies. (sparc_option_override): Add LEON5 costs (sparc_adjust_cost): Add LEON5 cost adjustments * config/sparc/sparc.h: Add LEON5 * config/sparc/sparc.md: Include LEON5 scheduling information * config/sparc/sparc.opt: Add LEON5 * doc/invoke.texi: Add LEON5 * config/sparc/leon5.md: New file. 2021-09-16 Daniel Cederman * config/sparc/sparc.md (stack_protect_setsi): Add NOP to prevent sensitive sequence for B2BST errata workaround. 2021-09-16 Daniel Cederman * config/sparc/sparc.c (sparc_do_work_around_errata): Do not begin functions with atomic instruction in the UT700 errata workaround. 2021-09-16 Daniel Cederman * config/sparc/sparc.c (next_active_non_empty_insn): New function that returns next active non empty assembly instruction. (sparc_do_work_around_errata): Use new function. 2021-09-16 Daniel Cederman * config/sparc/sparc.c (store_insn_p): Add predicate for store attributes. (load_insn_p): Add predicate for load attributes. (sparc_do_work_around_errata): Use new predicates. 2021-09-16 Andreas Larsson * config/sparc/sparc.c (dump_target_flag_bits): Print bit names for LEON and LEON3. 2021-09-14 Xionghu Luo Backported from master: 2021-09-07 Xionghu Luo PR target/97142 * config/rs6000/rs6000.md (fmod3): New define_expand. (remainder3): Likewise. 2021-09-08 Jonathan Wakely Backported from master: 2021-09-08 Jonathan Wakely PR c++/60318 * doc/trouble.texi (Copy Assignment): Fix description of behaviour and fix code in example. 2021-09-06 Richard Biener Backported from master: 2021-07-12 Richard Biener PR tree-optimization/101394 * tree-ssa-pre.c (do_pre_regular_insertion): Avoid inserting copies from abnormals for a full redundancy. 2021-09-06 Richard Biener Backported from master: 2021-07-05 Richard Biener PR middle-end/101291 * cfgloopmanip.c (loop_version): Set the loop copy of the versioned loop to the new loop. 2021-09-06 Richard Biener Backported from master: 2021-07-07 Richard Biener PR tree-optimization/101173 PR tree-optimization/101280 * gimple-loop-interchange.cc (tree_loop_interchange::valid_data_dependences): Properly guard all dependence checks with DDR_REVERSED_P or its inverse. 2021-09-06 Richard Biener Backported from master: 2021-06-24 Richard Biener PR tree-optimization/101105 * tree-vect-data-refs.c (vect_prune_runtime_alias_test_list): Only ignore steps when they are equal or scalar order is preserved. 2021-09-06 Richard Biener Backported from master: 2021-06-11 Richard Biener PR middle-end/101009 * tree-data-ref.c (build_classic_dist_vector_1): Make sure to set *init_b to true when we encounter a constant equal index pair. (compute_affine_dependence): Also dump the actual DR_REF. 2021-09-03 Peter Bergner Backported from master: 2021-08-19 Peter Bergner PR target/101849 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Cast pointer to __vector_pair *. 2021-09-03 Peter Bergner Backported from master: 2021-07-07 Peter Bergner * config/rs6000/rs6000-call.c (mma_init_builtins): Use VSX_BUILTIN_LXVP and VSX_BUILTIN_STXVP. 2021-09-03 Peter Bergner Backported from master: 2021-07-02 Peter Bergner * config/rs6000/rs6000-builtin.def (BU_MMA_PAIR_LD, BU_MMA_PAIR_ST): New macros. (__builtin_vsx_lxvp, __builtin_vsx_stxvp): New built-ins. * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Expand lxvp and stxvp built-ins. (mma_init_builtins): Handle lxvp and stxvp built-ins. (builtin_function_type): Likewise. * doc/extend.texi (__builtin_vsx_lxvp, __builtin_mma_stxvp): Document. 2021-09-03 Peter Bergner * config/rs6000/rs6000-call.c (mma_init_builtins): Test for MMA_BUILTIN_DISASSEMBLE_ACC and VSX_BUILTIN_DISASSEMBLE_PAIR. (rs6000_gimple_fold_mma_builtin): Likewise. 2021-08-31 Thomas Schwinge Backported from master: 2021-08-31 Thomas Schwinge * tree.c (walk_tree_1) : Handle three operands. 2021-08-27 konglin1 PR target/101472 * config/i386/sse.md: (scattersi): Add mask operand to UNSPEC_VSIBADDR. (scattersi): Likewise. (*avx512f_scattersi): Merge mask operand to set_dest. (*avx512f_scatterdi): Likewise 2021-08-25 konglin1 PR target/101471 * config/i386/avx512dqintrin.h (_mm512_fpclass_ps_mask): Fix macro define in O0. (_mm512_mask_fpclass_ps_mask): Ditto. 2021-08-24 Richard Earnshaw Backported from master: 2021-08-24 Richard Earnshaw PR target/102035 * config/arm/arm.md (attribute arch): Add fix_vlldm. (arch_enabled): Use it. * config/arm/vfp.md (lazy_store_multiple_insn): Add alternative to use when erratum mitigation is needed. 2021-08-24 Richard Earnshaw Backported from master: 2021-08-24 Richard Earnshaw PR target/102035 * config/arm/arm.opt (mfix-cmse-cve-2021-35465): New option. * doc/invoke.texi (Arm Options): Document it. * config/arm/arm-cpus.in (quirk_vlldm): New feature bit. (ALL_QUIRKS): Add quirk_vlldm. (cortex-m33): Add quirk_vlldm. (cortex-m35p, cortex-m55): Likewise. * config/arm/arm.c (arm_option_override): Enable fix_vlldm if targetting an affected CPU and not explicitly controlled on the command line. 2021-08-24 Richard Earnshaw Backported from master: 2021-08-24 Richard Earnshaw * config/arm/vfp.md (lazy_store_multiple_insn): Rewrite as valid RTL. (lazy_load_multiple_insn): Likewise. 2021-08-24 Richard Biener Backported from master: 2021-08-23 Richard Biener PR ipa/97565 * tree-ssa-structalias.c (ipa_pta_execute): Check in_other_partition in addition to has_gimple_body. 2021-08-23 Richard Earnshaw Backported from master: 2021-08-05 Richard Earnshaw PR target/101723 * config/arm/arm-cpus.in (generic-armv7-a): Add quirk to suppress writing .cpu directive in asm output. * config/arm/arm.c (arm_identify_fpu_from_isa): New variable. (arm_last_printed_arch_string): Delete. (arm_last-printed_fpu_string): Delete. (arm_configure_build_target): If use of floating-point/SIMD is disabled, remove all fp/simd related features from the target ISA. (last_arm_targ_options): New variable. (arm_print_asm_arch_directives): Add new parameters. Change order of emitted directives and handle all cases here. (arm_file_start): Always call arm_print_asm_arch_directives, move all generation of .arch/.arch_extension here. (arm_file_end): Call arm_print_asm_arch. (arm_declare_function_name): Call arm_print_asm_arch_directives instead of printing .arch/.fpu directives directly. 2021-08-23 Richard Earnshaw Backported from master: 2021-08-05 Richard Earnshaw * config/arm/arm.c (arm_configure_build_target): Don't call arm_option_reconfigure_globals. (arm_option_restore): Call arm_option_reconfigure_globals after reconfiguring the target. * config/arm/arm-c.c (arm_pragma_target_parse): Likewise. 2021-08-23 Richard Earnshaw Backported from master: 2021-08-05 Richard Earnshaw * config/arm/arm.c (arm_configure_build_target): Ensure the target's arch_name is always set. 2021-08-23 Christophe Lyon Backported from master: 2021-08-23 Christophe Lyon * config/arm/arm_mve.h: Fix __arm_vctp16q return type. 2021-08-19 Richard Earnshaw Backported from master: 2021-05-27 Richard Earnshaw PR target/100767 * config/arm/arm.c (arm_configure_build_target): Remove parameter opts_set, directly check opts parameters for being non-null. (arm_option_restore): Update call to arm_configure_build_target. (arm_option_override): Likewise. (arm_can_inline_p): Likewise. (arm_valid_target_attribute_tree): Likewise. * config/arm/arm-c.c (arm_pragma_target_parse): Likewise. * config/arm/arm-protos.h (arm_configure_build_target): Adjust prototype. 2021-08-17 Richard Sandiford Backported from master: 2021-08-03 Richard Sandiford * doc/invoke.texi: Document -mtune=neoverse-512tvb and -mcpu=neoverse-512tvb. * config/aarch64/aarch64-cores.def (neoverse-512tvb): New entry. * config/aarch64/aarch64-tune.md: Regenerate. 2021-08-17 Richard Sandiford Backported from master: 2021-04-28 Richard Sandiford PR target/100305 * config/aarch64/constraints.md (Utq): Require the address to be valid for both the element mode and for V2DImode. 2021-08-13 Martin Liska PR gcov-profile/100788 * coverage.c (coverage_begin_function): Update function beginning when #line macro is used. 2021-07-31 Xi Ruoyao Backported from master: 2021-07-30 Xi Ruoyao PR target/94780 * config/mips/mips.c (mips_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR. 2021-07-28 Martin Sebor PR c/99295 * doc/extend.texi (attribute malloc): Reword and clarify nonaliasing property. 2021-07-20 Martin Jambor Backported from master: 2021-07-08 Martin Jambor PR ipa/101066 * ipa-sra.c (class isra_call_summary): New member m_before_any_store, initialize it in the constructor. (isra_call_summary::dump): Dump the new field. (ipa_sra_call_summaries::duplicate): Copy it. (process_scan_results): Set it. (isra_write_edge_summary): Stream it. (isra_read_edge_summary): Likewise. (param_splitting_across_edge): Only override safe_to_import_accesses if m_before_any_store is set. 2021-07-20 Uroš Bizjak PR target/100182 * config/i386/sync.md (define_peephole2 atomic_storedi_fpu): Remove. (define_peephole2 atomic_loaddi_fpu): Ditto. 2021-07-19 Bill Schmidt PR target/101129 * config/rs6000/rs6000-p8swap.c (has_part_mult): New. (rs6000_analyze_swaps): Insns containing a subreg of a mult are not swappable. 2021-07-19 Segher Boessenkool PR rtl-optimization/99927 * combine.c (distribute_notes) [REG_UNUSED]: If the register already is dead, just drop it. 2021-07-02 Eric Botcazou * config/i386/i386.c (asm_preferred_eh_data_format): Always use the PIC encodings for PE-COFF targets. 2021-06-24 Uros Bizjak Backported from master: 2021-06-23 Uroš Bizjak PR target/101175 * config/i386/i386.md (bsr_rex64): Add zero-flag setting RTX. (bsr): Ditto. (*bsrhi): Remove. (clz2): Update RTX pattern for additions. 2021-06-18 Srinath Parvathaneni Backported from master: 2021-06-18 Srinath Parvathaneni PR target/100856 * common/config/arm/arm-common.c (arm_canon_arch_option_1): New function derived from arm_canon_arch. (arm_canon_arch_option): Call it. (arm_canon_arch_multilib_option): New function. * config/arm/arm-cpus.in (IGNORE_FOR_MULTILIB): New fgroup. * config/arm/arm.h (arm_canon_arch_multilib_option): New prototype. (CANON_ARCH_MULTILIB_SPEC_FUNCTION): New macro. (MULTILIB_ARCH_CANONICAL_SPECS): New macro. (DRIVER_SELF_SPECS): Add MULTILIB_ARCH_CANONICAL_SPECS. * config/arm/arm.opt (mlibarch): New option. * config/arm/t-rmprofile (MULTILIB_MATCHES): For armv8*-m, replace use of march on RHS with mlibarch. 2021-06-18 Srinath Parvathaneni Backported from master: 2021-06-11 Srinath Parvathaneni PR target/101016 * config/arm/arm_mve.h (__arm_vld1q): Change __ARM_mve_coerce(p0, int8_t const *) to __ARM_mve_coerce1(p0, int8_t *) in the argument for the polymorphic variants matching code. (__arm_vld1q_z): Likewise. (__arm_vld2q): Likewise. (__arm_vld4q): Likewise. (__arm_vldrbq_gather_offset): Likewise. (__arm_vldrbq_gather_offset_z): Likewise. 2021-06-18 Peter Bergner Backported from master: 2021-06-14 Peter Bergner PR target/100777 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Use create_tmp_reg_or_ssa_name(). 2021-06-18 Peter Bergner Backported from master: 2021-06-10 Peter Bergner * config/rs6000/rs6000-builtin.def (build_pair): New built-in. (build_acc): Likewise. * config/rs6000/rs6000-call.c (mma_expand_builtin): Swap assemble source operands in little-endian mode. (rs6000_gimple_fold_mma_builtin): Handle VSX_BUILTIN_BUILD_PAIR. (mma_init_builtins): Likewise. * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle endianness ordering for the MMA assemble and build source operands. * doc/extend.texi (__builtin_vsx_build_acc, __builtin_mma_build_pair): Document. (__builtin_mma_assemble_acc, __builtin_mma_assemble_pair): Remove documentation. 2021-06-18 Peter Bergner Backported from master: 2021-05-31 Peter Bergner PR target/99842 * config/rs6000/predicates.md(mma_assemble_input_operand): Allow indexed form addresses. 2021-06-17 Marius Hillenbrand Backported from master: 2021-06-17 Marius Hillenbrand PR target/100871 * config/s390/vecintrin.h (vec_doublee): Fix to use __builtin_s390_vflls. (vec_floate): Fix to use __builtin_s390_vflrd. 2021-06-16 Richard Biener Backported from master: 2021-06-14 Richard Biener PR tree-optimization/100934 * tree-ssa-dom.c (pass_dominator::execute): Properly mark irreducible regions. 2021-06-16 Richard Biener Backported from master: 2021-05-28 Richard Biener PR ipa/100791 * tree-inline.c (copy_bb): When processing __builtin_va_arg_pack copy fntype from original call. 2021-06-16 Richard Biener Backported from master: 2021-05-11 Richard Biener PR ipa/100513 * ipa-param-manipulation.c (ipa_param_body_adjustments::modify_call_stmt): Avoid altering SSA_NAME_DEF_STMT by adjusting the calls LHS via gimple_call_lhs_ptr. 2021-06-16 Richard Biener Backported from master: 2021-05-11 Richard Biener PR middle-end/100509 * gimple-fold.c (fold_gimple_assign): Only call get_symbol_constant_value on register type symbols. 2021-06-16 Richard Biener Backported from master: 2021-05-10 Richard Biener PR tree-optimization/100492 * tree-loop-distribution.c (find_seed_stmts_for_distribution): Find nothing when the loop contains an irreducible region. 2021-06-04 Alex Coplan Backported from master: 2021-05-19 Alex Coplan PR target/100333 * config/arm/arm.md (nonsecure_call_internal): Always ensure callee's address is in a register. 2021-06-02 Vladimir N. Makarov Backported from master: 2021-01-21 Vladimir N. Makarov PR rtl-optimization/98777 * lra-int.h (lra_pmode_pseudo): New extern. * lra.c (lra_pmode_pseudo): New global. (lra): Set it up. * lra-eliminations.c (eliminate_regs_in_insn): Use it. 2021-06-02 Vladimir N. Makarov Backported from master: 2021-01-20 Vladimir N. Makarov PR rtl-optimization/98722 * lra-eliminations.c (eliminate_regs_in_insn): Check that target has no 3-op add insn to transform insns containing two pluses. 2021-06-02 Vladimir N. Makarov Backported from master: 2021-01-12 Vladimir N. Makarov PR target/97969 * lra-eliminations.c (eliminate_regs_in_insn): Add transformation of pattern 'plus (plus (hard reg, const), pseudo)'. 2021-06-02 Uros Bizjak Backported from master: 2021-06-02 Uroš Bizjak * config/i386/sse.md (abs2): Change define_insn to define_expand. 2021-06-01 Alex Coplan Backported from master: 2021-05-11 Alex Coplan PR target/99725 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Avoid emitting CFA adjusts on the sp if we have the fp. 2021-05-25 Alex Coplan Backported from master: 2021-05-10 Alex Coplan PR target/99960 * config/arm/mve.md (*mve_mov): Simplify output code. Use vldrw.u32 and vstrw.32 for V2D[IF]mode loads and stores. 2021-05-20 Alex Coplan Christophe Lyon PR target/99977 * config/arm/arm.c (arm_split_compare_and_swap): Fix up codegen with negative immediates: ensure we expand cbranchsi4_scratch correctly and ensure we satisfy its constraints. * config/arm/sync.md (@atomic_compare_and_swap_1): Don't attempt to tie two output operands together with constraints; collapse two alternatives. (@atomic_compare_and_swap_1): Likewise. * config/arm/thumb1.md (cbranchsi4_neg_late): New. 2021-05-19 Jonathan Wakely Backported from master: 2021-05-19 Jonathan Wakely * doc/cpp.texi (Common Predefined Macros): Update documentation for the __GXX_EXPERIMENTAL_CXX0X__ macro. 2021-05-17 Richard Biener Backported from master: 2021-01-28 Richard Biener PR rtl-optimization/80960 * dse.c (check_mem_read_rtx): Call get_addr on the offsetted address. 2021-05-17 Richard Biener Backported from master: 2021-05-12 Richard Biener PR tree-optimization/100566 * tree-ssa-sccvn.c (dominated_by_p_w_unex): Properly handle allow_back for all edge queries. 2021-05-13 Srinath Parvathaneni Backported from master: 2021-05-11 Srinath Parvathaneni Joe Ramsay PR target/100419 * config/arm/arm_mve.h (__arm_vstrwq_scatter_offset): Fix wrong arguments. (__arm_vcmpneq): Remove duplicate definition. (__arm_vstrwq_scatter_offset_p): Likewise. (__arm_vmaxq_x): Likewise. (__arm_vmlsdavaq): Likewise. (__arm_vmlsdavaxq): Likewise. (__arm_vmlsdavq_p): Likewise. (__arm_vmlsdavxq_p): Likewise. (__arm_vrmlaldavhaq): Likewise. (__arm_vstrbq_p): Likewise. (__arm_vstrbq_scatter_offset): Likewise. (__arm_vstrbq_scatter_offset_p): Likewise. (__arm_vstrdq_scatter_offset): Likewise. (__arm_vstrdq_scatter_offset_p): Likewise. (__arm_vstrdq_scatter_shifted_offset): Likewise. (__arm_vstrdq_scatter_shifted_offset_p): Likewise. 2021-05-13 Richard Earnshaw PR target/100563 * config/arm/arm.c (arm_canonicalize_comparison): Correctly canonicalize DImode inequality comparisons against the maximum integral value. 2021-05-12 Martin Sebor PR middle-end/100571 * calls.c (maybe_warn_rdwr_sizes): Clear object size if it can't be determined. 2021-05-12 Alex Coplan Backported from master: 2021-05-11 Alex Coplan PR target/99988 * config/aarch64/aarch64-bti-insert.c (aarch64_bti_j_insn_p): New. (rest_of_insert_bti): Avoid inserting duplicate bti j insns for jump table targets. 2021-05-11 Geng Qi Backported from master: 2021-04-30 Geng Qi * config/riscv/riscv.opt (march=,mabi=): Negative itself. 2021-05-10 Segher Boessenkool Backported from master: 2021-04-20 Segher Boessenkool PR target/100108 * config/rs6000/rs6000.c (rs6000_machine_from_flags): Do not consider OPTION_MASK_ISEL. 2021-05-06 Roman Zhuykov Backported from master: 2021-04-30 Roman Zhuykov PR rtl-optimization/100225 PR rtl-optimization/84878 * modulo-sched.c (sms_schedule): Use note_stores to skip loops where we have an instruction which touches (writes) any hard register from df->regular_block_artificial_uses set. Allow not-single-set instruction only right before basic block tail. 2021-05-06 Andre Vieira Backported from master: 2020-09-15 Andre Vieira * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Do not check +D32 for CMSE if -mfloat-abi=soft 2021-05-06 Srinath Parvathaneni Backported from master: 2020-06-23 Andre Vieira PR target/95646 * config/arm/arm.c: (cmse_nonsecure_entry_clear_before_return): Use 'callee_saved_reg_p' instead of 'calL_used_or_fixed_reg_p'. 2021-05-05 Eric Botcazou PR target/100402 * config/i386/i386.c (ix86_compute_frame_layout): For a SEH target, always return the establisher frame for __builtin_frame_address (0). 2021-05-05 Stefan Schulze Frielinghaus Backported from master: 2021-05-05 Stefan Schulze Frielinghaus PR rtl-optimization/100263 * postreload.c (move2add_valid_value_p): Ensure register can change mode. 2021-05-05 Richard Biener PR tree-optimization/98786 * tree-ssa-phiopt.c (factor_out_conditional_conversion): Avoid adding new uses of abnormals. 2021-05-05 Richard Biener Backported from master: 2021-04-27 Richard Biener PR tree-optimization/100278 * tree-ssa-pre.c (compute_avail): Give up when we cannot adjust TBAA beacuse of mismatching bases. 2021-05-04 Jakub Jelinek Backported from master: 2021-05-02 Jakub Jelinek PR target/100375 * config/nvptx/nvptx.c (nvptx_sese_pseudo): Use NULL instead of 0 as first argument of pseudo_node_t constructors. 2021-05-04 Jakub Jelinek Backported from master: 2021-04-29 Jakub Jelinek PR target/100302 * config/aarch64/aarch64.c (aarch64_add_offset_1_temporaries): Use absu_hwi instead of abs_hwi. 2021-05-04 Jakub Jelinek Backported from master: 2021-04-27 Jakub Jelinek PR rtl-optimization/100254 * cfgcleanup.c (outgoing_edges_match): Check REG_EH_REGION on last1 and last2 insns rather than BB_END (bb1) and BB_END (bb2) insns. 2021-05-04 Jakub Jelinek Backported from master: 2021-04-26 Jakub Jelinek PR debug/100255 * vmsdbgout.c (ASM_OUTPUT_DEBUG_STRING, vmsdbgout_begin_block, vmsdbgout_end_block, lookup_filename, vmsdbgout_source_line): Remove register keywords. 2021-05-04 Alex Coplan Backported from master: 2021-04-23 Alex Coplan PR rtl-optimization/100230 * early-remat.c (early_remat::sort_candidates): Use delete[] instead of delete for array allocated with new[]. 2021-04-30 David Edelsohn Backported from master: 2021-04-27 David Edelsohn * config/rs6000/aix.h (SUBTARGET_DRIVER_SELF_SPECS): New. * config/rs6000/aix64.opt (m64): New. (m32): New. 2021-04-30 Richard Biener PR tree-optimization/96513 * tree-vect-slp.c (struct vdhs_data): New. (vect_detect_hybrid_slp): New walker. (vect_detect_hybrid_slp): Rewrite. 2021-04-29 Richard Earnshaw Backported from master: 2021-04-28 Richard Earnshaw PR target/100311 * config/arm/arm.c (arm_hard_regno_mode_ok): Only allow VPR to be used in HImode. 2021-04-28 Uros Bizjak Backported from master: 2021-04-23 Uroš Bizjak PR target/100182 * config/i386/sync.md (FILD_ATOMIC/FIST_ATOMIC FP load peephole2): Copy operand 3 to operand 4. Use sse_reg_operand as operand 3 predicate. (FILD_ATOMIC/FIST_ATOMIC FP load peephole2 with mem blockage): Ditto. (LDX_ATOMIC/STX_ATOMIC FP load peephole2): Ditto. (LDX_ATOMIC/LDX_ATOMIC FP load peephole2 with mem blockage): Ditto. (FILD_ATOMIC/FIST_ATOMIC FP store peephole2): Copy operand 1 to operand 0. (FILD_ATOMIC/FIST_ATOMIC FP store peephole2 with mem blockage): Ditto. (LDX_ATOMIC/STX_ATOMIC FP store peephole2): Ditto. (LDX_ATOMIC/LDX_ATOMIC FP store peephole2 with mem blockage): Ditto. 2021-04-26 Alex Coplan Backported from master: 2021-04-08 Alex Coplan PR target/99647 * config/arm/iterators.md (MVE_vecs): New. (V_elem): Also handle V2DF. * config/arm/mve.md (*mve_mov): Rename to ... (*mve_vdup): ... this. Remove second alternative since vec_duplicate of const_int is not canonical RTL, and we don't want to match symbol_refs. (*mve_vec_duplicate): Delete (pattern is redundant). 2021-04-26 Richard Biener Backported from master: 2021-04-13 Richard Biener PR tree-optimization/100053 * tree-ssa-sccvn.c (vn_nary_op_get_predicated_value): Do not use optimistic dominance queries for backedges to validate predicated values. (dominated_by_p_w_unex): Add parameter to ignore executable state on backedges. (rpo_elim::eliminate_avail): Adjust. 2021-04-26 Richard Biener Backported from master: 2021-04-07 Richard Biener PR tree-optimization/99954 * tree-loop-distribution.c: Include tree-affine.h. (generate_memcpy_builtin): Try using tree-affine to prove non-overlap. (loop_distribution::classify_builtin_ldst): Always classify as PKIND_MEMMOVE. 2021-04-26 Richard Biener Backported from master: 2021-04-06 Richard Biener PR tree-optimization/99880 * tree-vect-loop.c (maybe_set_vectorized_backedge_value): Only set vectorized defs of relevant PHIs. 2021-04-24 Richard Sandiford PR rtl-optimization/96796 * lra-constraints.c (in_class_p): Add a default-false allow_all_reload_class_changes_p parameter. Do not treat reload moves specially when the parameter is true. (get_reload_reg): Try to narrow the class of an existing OP_OUT reload if we're reloading a reload pseudo in a reload instruction. 2021-04-23 YiFei Zhu Backported from master: 2021-04-23 YiFei Zhu * config/bpf/bpf.h (ASM_OUTPUT_ALIGNED_BSS): Use .type and .lcomm. 2021-04-23 YiFei Zhu Backported from master: 2021-04-23 YiFei Zhu * config/bpf/bpf.h (FUNCTION_BOUNDARY): Set to 64. 2021-04-23 Richard Sandiford Backported from master: 2021-04-14 Richard Sandiford PR rtl-optimization/99929 * rtl.h (same_vector_encodings_p): New function. * cse.c (exp_equiv_p): Check that CONST_VECTORs have the same encoding. * cselib.c (rtx_equal_for_cselib_1): Likewise. * jump.c (rtx_renumbered_equal_p): Likewise. * lra-constraints.c (operands_match_p): Likewise. * reload.c (operands_match_p): Likewise. * rtl.c (rtx_equal_p_cb, rtx_equal_p): Likewise. 2021-04-23 Richard Sandiford Backported from master: 2021-03-31 Richard Sandiford PR target/98119 * config/aarch64/aarch64.c (aarch64_vectorize_preferred_vector_alignment): Query the size of the provided SVE vector; do not assume that all SVE vectors have the same size. 2021-04-23 Bin Cheng Backported from master: 2021-04-07 Bin Cheng PR tree-optimization/98736 * tree-loop-distribution.c * (loop_distribution::bb_top_order_init): Compute RPO with programing order preserved by calling function rev_post_order_and_mark_dfs_back_seme. 2021-04-23 Richard Biener Backported from master: 2020-07-31 Richard Biener * cfganal.h (rev_post_order_and_mark_dfs_back_seme): Adjust prototype. * cfganal.c (rpoamdbs_bb_data): New struct with pre BB data. (tag_header): New helper. (cmp_edge_dest_pre): Likewise. (rev_post_order_and_mark_dfs_back_seme): Compute SCCs, find SCC exits and perform a DFS walk with extra edges to compute a RPO with adjacent SCC members when requesting an iteration optimized order and populate the toplevel SCC array. * tree-ssa-sccvn.c (do_rpo_vn): Remove ad-hoc computation of max_rpo and fill it in from SCC extent info instead. 2021-04-23 Richard Biener Backported from master: 2020-07-20 Richard Biener * cfganal.c (rev_post_order_and_mark_dfs_back_seme): Remove write-only post array. 2021-04-23 Alex Coplan Backported from master: 2021-04-06 Alex Coplan PR target/99748 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Also use base PCS for [su]fix_optab. 2021-04-23 Richard Sandiford Backported from master: 2021-04-14 Richard Sandiford PR target/99249 * config/aarch64/aarch64.c (aarch64_expand_sve_const_vector_sel): New function. (aarch64_expand_sve_const_vector): Use it for nelts_per_pattern==2. 2021-04-23 Richard Sandiford Backported from master: 2021-03-31 Richard Sandiford PR rtl-optimization/97141 PR rtl-optimization/98726 * emit-rtl.c (valid_for_const_vector_p): Return true for CONST_POLY_INT_P. * rtx-vector-builder.h (rtx_vector_builder::step): Return a poly_wide_int instead of a wide_int. (rtx_vector_builder::apply_set): Take a poly_wide_int instead of a wide_int. * rtx-vector-builder.c (rtx_vector_builder::apply_set): Likewise. * config/aarch64/aarch64.c (aarch64_legitimate_constant_p): Return false for CONST_VECTORs that cannot be forced to memory. * config/aarch64/aarch64-simd.md (mov): If a CONST_VECTOR is too complex to force to memory, build it up from individual elements instead. 2021-04-23 Richard Biener Backported from master: 2021-01-26 Richard Biener PR middle-end/98726 * tree.h (vector_cst_int_elt): Remove. * tree.c (vector_cst_int_elt): Use poly_wide_int for computations, make static. 2021-04-23 Richard Sandiford Backported from master: 2021-03-30 Richard Sandiford PR target/98136 * config/aarch64/aarch64.md (mov): Pass multi-instruction CONST_INTs to aarch64_expand_mov_immediate when called after RA. 2021-04-23 Richard Sandiford Backported from master: 2021-03-31 Richard Sandiford PR tree-optimization/98268 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Call recompute_tree_invariant_for_addr_expr after successfully folding a TARGET_MEM_REF that occurs inside an ADDR_EXPR. 2021-04-23 Richard Sandiford Backported from master: 2021-03-31 Richard Sandiford PR tree-optimization/99726 * tree-data-ref.c (create_intersect_range_checks_index): Bail out if there is more than one access function SCEV for the loop being versioned. 2021-04-22 Alex Coplan PR target/99216 * config/aarch64/aarch64-sve-builtins.cc (function_builder::add_function): Add placeholder_p argument, use placeholder decls if this is set. (function_builder::add_unique_function): Instead of conditionally adding direct overloads, unconditionally add either a direct overload or a placeholder. (function_builder::add_overloaded_function): Set placeholder_p if we're using C++ overloads. Use the obstack for string storage instead of relying on the tree nodes. (function_builder::add_overloaded_functions): Don't return early for m_direct_overloads: we need to add placeholders. * config/aarch64/aarch64-sve-builtins.h (function_builder::add_function): Add placeholder_p argument. * lto-streamer.h (LTO_minor_version): Bump. 2021-04-21 Jakub Jelinek Backported from master: 2021-04-21 Jakub Jelinek PR rtl-optimization/100148 * cprop.c (constprop_register): Use next_nondebug_insn instead of NEXT_INSN. 2021-04-20 Jakub Jelinek Backported from master: 2021-04-16 Jakub Jelinek PR target/99767 * tree-vect-loop.c (vect_transform_loop): Don't remove just dead scalar .MASK_LOAD calls, but also dead .COND_* calls - replace them by their last argument. 2021-04-20 Jakub Jelinek Backported from master: 2021-04-12 Jakub Jelinek PR rtl-optimization/99905 * combine.c (expand_compound_operation): If pos + len > modewidth, perform the right shift by pos in inner_mode and then convert to mode, instead of trying to simplify a shift of rtx with inner_mode by pos as if it was a shift in mode. 2021-04-20 Jakub Jelinek Backported from master: 2021-04-12 Jakub Jelinek PR debug/99830 * combine.c (simplify_and_const_int_1): Don't optimize varop away if it has side-effects. 2021-04-20 Jakub Jelinek Backported from master: 2021-04-10 Jakub Jelinek PR lto/99849 * expr.c (expand_expr_addr_expr_1): Test is_global_var rather than just TREE_STATIC on COMPOUND_LITERAL_EXPR_DECLs. 2021-04-20 Jakub Jelinek Backported from master: 2021-04-10 Jakub Jelinek PR rtl-optimization/98601 * rtlanal.c (rtx_addr_can_trap_p_1): Allow in assert unknown size not just for BLKmode, but also for VOIDmode. For STRICT_ALIGNMENT unaligned_mems handle VOIDmode like BLKmode. 2021-04-20 Jakub Jelinek Backported from master: 2021-04-03 Jakub Jelinek PR rtl-optimization/99863 * dse.c (replace_read): Drop regs_live argument. Instead of regs_live, use store_insn->fixed_regs_live if non-NULL, otherwise punt if insns sequence clobbers or sets any hard registers. 2021-04-19 Tobias Burnus Backported from master: 2020-11-27 Tobias Burnus PR c/97880 * omp-expand.c (expand_oacc_collapse_init, expand_oacc_collapse_vars): Use now passed diff_type. (expand_oacc_for): Take largest type for diff_type, taking tiling and collapsing into account. 2021-04-19 Eric Botcazou * config/i386/winnt.c (i386_pe_seh_cold_init): Properly deal with frames larger than the SEH maximum frame size. 2021-04-18 Hafiz Abid Qadeer Backported from master: 2021-04-11 Hafiz Abid Qadeer PR middle-end/98088 * omp-expand.c (expand_oacc_collapse_init): Update condition in a gcc_assert. 2021-04-16 Tamar Christina Backported from master: 2021-04-16 Tamar Christina PR target/100048 * config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv): New. * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_trn): Use new TRN optab. * config/aarch64/iterators.md (UNSPEC_TRN1_CONV): New. 2021-04-08 Richard Biener PR lto/99898 * lto-streamer.h (LTO_minor_version): Bump. 2021-04-08 Release Manager * GCC 10.3.0 released. 2021-04-04 Iain Sandoe Backported from master: 2021-04-03 Iain Sandoe * config/darwin.c (machopic_legitimize_pic_address): Check that the current pic register is one of the hard reg set before setting liveness. 2021-04-02 Jakub Jelinek Backported from master: 2020-10-23 Jakub Jelinek * Makefile.in (PLUGIN_HEADERS): Add gomp-constants.h and $(EXPR_H). (s-header-vars): Accept not just spaces but also tabs between *_H name and =. Handle common/config/ headers similarly to config. Don't throw away everything from first ... to last / on the remaining string, instead skip just ... to corresponding last / without intervening spaces and tabs. (install-plugin): Treat common/config headers like config headers. * config/i386/t-i386 (TM_H): Add $(srcdir)/common/config/i386/i386-cpuinfo.h. 2021-04-01 Jakub Jelinek PR c++/98481 * common.opt (fabi-version): Default to 14. 2021-04-01 Martin Jambor Backported from master: 2021-04-01 Martin Jambor PR tree-optimization/97009 * tree-sra.c (access_or_its_child_written): New function. (propagate_subaccesses_from_rhs): Use it instead of a simple grp_write test. 2021-04-01 Richard Biener PR tree-optimization/99856 * tree-vect-patterns.c (vect_recog_over_widening_pattern): Promote precision to vector element precision. 2021-03-31 Jan Hubicka Backported from master: 2021-03-31 Jan Hubicka PR ipa/98265 * cif-code.def (USES_COMDAT_LOCAL): Make CIF_FINAL_NORMAL. 2021-03-31 Vladimir N. Makarov PR rtl-optimization/96264 * lra-remat.c (reg_overlap_for_remat_p): Check also output insn hard regs. 2021-03-31 Prathamesh Kulkarni PR tree-optimization/97849 * tree-if-conv.c (tree_if_conversion): Move ssa_name replacement code from ifcvt_local_dce to this function before calling do_rpo_vn. 2021-03-31 Jakub Jelinek Backported from master: 2021-03-31 Jakub Jelinek Richard Sandiford PR target/99813 * config/aarch64/aarch64.md (*add3_poly_1): Swap Uai and Uav constraints on operands[2] and similarly 0 and rk constraints on operands[1] corresponding to that. 2021-03-31 Jan Hubicka * common/config/i386/i386-common.c (ARRAY_SIZE): Make pta_size signed. 2021-03-31 Martin Liska Backported from master: 2021-03-24 Martin Liska PR target/99753 * common/config/i386/i386-common.c (ARRAY_SIZE): Fix off-by-one error. * config/i386/i386-options.c (ix86_option_override_internal): Add run-time assert. 2021-03-31 Jan Hubicka Backported from master: 2021-03-18 Jan Hubicka * config/i386/x86-tune-costs.h (struct processor_costs): Fix costs of integer divides1. 2021-03-31 Jan Hubicka * config/i386/x86-tune-costs.h (struct processor_costs): Remove mask register costs. 2021-03-31 Jan Hubicka Backported from master: 2021-03-15 Jan Hubicka * config/i386/i386-options.c (processor_cost_table): Add znver3_cost. * config/i386/x86-tune-costs.h (znver3_cost): New gobal variable; copy of znver2_cost. 2021-03-31 Jan Hubicka * common/config/i386/i386-common.c: Add znver3. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add AMDFAM19H (enum processor_subtypes): Add AMDFAM19H_ZNVER3. (processor_alias_table): Add znver3 and AMDFAM19H entry. * common/config/i386/i386-cpuinfo.h (processor_types): Add AMDFAM19H. (processor_subtypes): AMDFAM19H_ZNVER3. * config.gcc (i[34567]86-*-linux* | ...): Likewise. * config/i386/driver-i386.c: (host_detect_local_cpu): Let -march=native recognize znver3 processors. * config/i386/i386-c.c (ix86_target_macros_internal): Add znver3. * config/i386/i386-options.c (m_znver3): New definition. (m_ZNVER): Include m_znver3. (processor_cost_table): Add znver3. * config/i386/i386.c (ix86_reassociation_width): Likewise. * config/i386/i386.h (TARGET_znver3): New definition. (enum processor_type): Add PROCESSOR_ZNVER3. * config/i386/i386.md (define_attr "cpu"): Add znver3. * config/i386/x86-tune-sched.c: (ix86_issue_rate): Likewise. (ix86_adjust_cost): Likewise. * config/i386/x86-tune.def (X86_TUNE_AVOID_256FMA_CHAINS): Likewise. * config/i386/znver1.md: Add new reservations for znver3. * doc/extend.texi: Add details about znver3. * doc/invoke.texi: Likewise. 2021-03-31 H.J. Lu Backported from master: 2020-06-24 H.J. Lu PR target/95842 * common/config/i386/i386-common.c (processor_alias_table): Add processor model and priority to each entry. (pta_size): Updated with -6. (num_arch_names): New. * common/config/i386/i386-cpuinfo.h: New file. * config/i386/i386-builtins.c (feature_priority): Removed. (processor_model): Likewise. (_arch_names_table): Likewise. (arch_names_table): Likewise. (_isa_names_table): Replace P_ZERO with P_NONE. (get_builtin_code_for_version): Replace P_ZERO with P_NONE. Use processor_alias_table. (fold_builtin_cpu): Replace arch_names_table with processor_alias_table. * config/i386/i386.h: Include "common/config/i386/i386-cpuinfo.h". (pta): Add model and priority. (num_arch_names): New. 2021-03-31 Kyrylo Tkachov PR target/99037 * config/aarch64/aarch64-simd.md (move_lo_quad_internal_): Use aarch64_simd_or_scalar_imm_zero to match zeroes. Remove pattern matching const_int 0. (move_lo_quad_internal_be_): Likewise. (move_lo_quad_): Update for the above. * config/aarch64/iterators.md (VQ_2E): Delete. 2021-03-30 Jakub Jelinek PR tree-optimization/99777 * fold-const.c (extract_muldiv_1): For conversions, punt on casts from types other than scalar integral types. 2021-03-30 Jakub Jelinek PR debug/99334 * dwarf2out.h (struct dw_fde_node): Add rule18 member. * dwarf2cfi.c (dwarf2out_frame_debug_expr): When handling (set hfp sp) assignment with drap_reg active, queue reg save for hfp with offset 0 and flush queued reg saves. When handling a push with rule18, defer queueing reg save for hfp and just assert the offset is 0. (scan_trace): Assert that fde->rule18 is false. 2021-03-30 Jakub Jelinek PR debug/99388 * dwarf2out.c (insert_float): Change return type from void to unsigned, handle GET_MODE_SIZE (mode) == 2 and return element size. (mem_loc_descriptor, loc_descriptor, add_const_value_attribute): Adjust callers. 2021-03-30 Richard Biener PR tree-optimization/99824 * stor-layout.c (set_min_and_max_values_for_integral_type): Assert the precision is within the bounds of WIDE_INT_MAX_PRECISION. * tree-ssa-sccvn.c (ao_ref_init_from_vn_reference): Use the outermost component ref only to lower the access size and initialize that from the access type. 2021-03-29 Alex Coplan Backported from master: 2021-03-22 Alex Coplan PR target/97252 * config/arm/arm-protos.h (neon_make_constant): Add generate argument to guard emitting insns, default to true. * config/arm/arm.c (arm_legitimate_constant_p_1): Reject CONST_VECTORs which neon_make_constant can't handle. (neon_vdup_constant): Add generate argument, avoid emitting insns if it's not set. (neon_make_constant): Plumb new generate argument through. * config/arm/constraints.md (Ui): New. Use it... * config/arm/mve.md (*mve_mov): ... here. * config/arm/vec-common.md (movv8hf): Use neon_make_constant to synthesize constants. 2021-03-28 David Edelsohn Backported from master: 2021-03-28 David Edelsohn * config/rs6000/rs6000.c (rs6000_output_dwarf_dtprel): Do not add XCOFF TLS reloc decorations. 2021-03-26 Iain Buclaw Backported from master: 2021-03-26 Iain Buclaw PR ipa/99466 * tree-emutls.c (get_emutls_init_templ_addr): Mark initializer of weak TLS declarations as public. 2021-03-25 Stam Markianos-Wright PR tree-optimization/96974 * tree-vect-stmts.c (vect_get_vector_types_for_stmt): Replace assert with graceful exit. 2021-03-25 Xionghu Luo Backported from master: 2021-03-25 Xionghu Luo PR target/97329 * config/rs6000/rs6000.c (power8_costs): Change l2 cache from 256 to 512. 2021-03-24 Iain Sandoe * config/darwin.c (output_objc_section_asm_op): Avoid extra objective-c section switches unless the linker needs them. * config/darwin.c (darwin_objc2_section): Allow for values > 1 to represent the next runtime. (darwin_objc1_section): Likewise. * config/darwin.c (darwin_globalize_label): Add protocol meta-data labels to the set that are global. Make a subset of metadate symbols global. (darwin_label_is_anonymous_local_objc_name): Make a subset of metadata symbols linker-visible. (darwin_override_options): Track more target OS versions, make the next_runtime version track this (unless it's set to 0 for GNU runtime). * config/darwin.h (NEXT_OBJC_RUNTIME): Set the default next runtime value to be 10.5.8. 2021-03-24 Jakub Jelinek PR target/99540 * config/aarch64/aarch64.c (aarch64_add_offset): Tell expand_mult to perform an unsigned rather than a signed multiplication. 2021-03-24 Richard Biener Backported from master: 2021-03-15 Richard Biener PR tree-optimization/98834 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle missing subsetting by truncating the access size. 2021-03-24 Richard Biener Backported from master: 2021-02-08 Richard Biener PR lto/96591 * tree.c (walk_tree_1): Walk VECTOR_CST elements. 2021-03-24 Richard Biener Backported from master: 2021-03-22 Richard Biener PR tree-optimization/99694 * tree-ssa-sccvn.c (visit_phi): Ignore edges with the PHI result. 2021-03-23 H.J. Lu Backported from master: 2021-03-23 H.J. Lu PR target/99704 * config/i386/cpuid.h (__cpuid): Add __volatile__. (__cpuid_count): Likewise. 2021-03-22 Iain Sandoe Backported from master: 2020-10-10 Iain Sandoe * config/darwin-sections.def (objc2_data_section): New. (objc2_ivar_section): New. * config/darwin.c (darwin_objc2_section): Act on Protocol and ivar refs. 2021-03-22 Iain Sandoe Backported from master: 2020-10-10 Iain Sandoe * config/darwin-sections.def (objc2_class_names_section, objc2_method_names_section, objc2_method_types_section): New * config/darwin.c (output_objc_section_asm_op): Output new sections. (darwin_objc2_section): Select new sections where used. 2021-03-22 David Edelsohn Backported from master: 2021-01-30 David Edelsohn * config/rs6000/rs6000.opt (mabi=vec-extabi): New. (mabi=vec-default): New. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define __EXTABI__ for AIX Vector extended ABI. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print AIX Vector extabi info. (conditional_register_usage): If AIX vec_extabi enabled, vs20-vs31 are non-volatile. * doc/invoke.texi (PowerPC mabi): Add AIX vec-extabi and vec-default. 2021-03-22 Kito Cheng Backported from master: 2021-03-22 Kito Cheng PR target/99702 * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value after type checking. 2021-03-21 Iain Sandoe Backported from master: 2021-03-01 Iain Sandoe PR target/44107 PR target/48097 * config/darwin-protos.h (darwin_should_restore_cfa_state): New. * config/darwin.c (darwin_should_restore_cfa_state): New. * config/darwin.h (TARGET_ASM_SHOULD_RESTORE_CFA_STATE): New. * doc/tm.texi: Regenerated. * doc/tm.texi.in: Document TARGET_ASM_SHOULD_RESTORE_CFA_STATE. * dwarf2cfi.c (connect_traces): If the target requests, restore the CFA expression after a DW_CFA_restore. * target.def (TARGET_ASM_SHOULD_RESTORE_CFA_STATE): New hook. 2021-03-21 Iain Sandoe * config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Move the spec for the Darwin10 unwinder stub from here .. * config/darwin.h (LINK_COMMAND_SPEC_A): ... to here. here... * config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Move from here.. * config/darwin.h (LINK_GCC_C_SEQUENCE_SPEC): ... to here. * config/darwin9.h (STACK_CHECK_STATIC_BUILTIN): Move from here.. * config/darwin.h (STACK_CHECK_STATIC_BUILTIN): .. to here. * config.gcc: Compute default version information from the configured target. Likewise defaults for ld64. Delete reference to the now removed darwin8.h * config/darwin10.h: Removed. * config/darwin12.h: Removed. * config/darwin9.h: Removed. * config/rs6000/darwin8.h: Removed. 2021-03-21 Iain Sandoe Backported from master: 2021-01-02 Iain Sandoe * config/darwin.h (DSYMUTIL_SPEC): Default to DWARF (ASM_DEBUG_SPEC):Only define if the assembler supports stabs. (PREFERRED_DEBUGGING_TYPE): Default to DWARF. (DARWIN_PREFER_DWARF): Define. * config/darwin9.h (PREFERRED_DEBUGGING_TYPE): Remove. (DARWIN_PREFER_DWARF): Likewise (DSYMUTIL_SPEC): Likewise. (COLLECT_RUN_DSYMUTIL): Likewise. (ASM_DEBUG_SPEC): Likewise. (ASM_DEBUG_OPTION_SPEC): Likewise. 2021-03-21 Iain Sandoe Backported from master: 2020-08-03 Iain Sandoe * config/darwin.h (ASM_DECLARE_FUNCTION_NAME): UNDEF before use. (DEF_MIN_OSX_VERSION): Only define if there's no existing def. 2021-03-21 Iain Sandoe Backported from master: 2020-11-22 Iain Sandoe * config/darwin-c.c (struct f_align_stack): Rename to type from align_stack to f_align_stack. (push_field_alignment): Likewise. (pop_field_alignment): Likewise. 2021-03-21 Iain Sandoe Backported from master: 2020-10-10 Iain Sandoe * config/darwin.c (darwin_emit_local_bss): Amend section names to match system tools. (darwin_output_aligned_bss): Likewise. 2021-03-21 Iain Sandoe Backported from master: 2020-09-07 Iain Sandoe * config/darwin.c (darwin_libc_has_function): Report sincos available from 10.9. 2021-03-21 Iain Sandoe Backported from master: 2020-08-03 Iain Sandoe * config/darwin.c (IN_TARGET_CODE): Remove. (darwin_mergeable_constant_section): Handle poly-int machine modes. (machopic_select_rtx_section): Likewise. 2021-03-20 John David Anglin * config/pa/pa.c (import_milli): Use memcpy instead of strncpy. 2021-03-19 Jakub Jelinek Backported from master: 2021-03-16 Jakub Jelinek PR target/99563 * config/i386/i386.h (struct machine_function): Add has_explicit_vzeroupper bitfield. * config/i386/i386-expand.c (ix86_expand_builtin): Set cfun->machine->has_explicit_vzeroupper when expanding IX86_BUILTIN_VZEROUPPER. * config/i386/i386-features.c (rest_of_handle_insert_vzeroupper): Do the mode switching only when TARGET_VZEROUPPER, expensive optimizations turned on and not optimizing for size. (pass_insert_vzeroupper::gate): Enable even when cfun->machine->has_explicit_vzeroupper is set. 2021-03-19 Jakub Jelinek Backported from master: 2021-03-16 Jakub Jelinek PR target/99542 * config/aarch64/aarch64.c (aarch64_simd_clone_compute_vecsize_and_simdlen): If not a function definition, walk TYPE_ARG_TYPES list if non-NULL for argument types instead of DECL_ARGUMENTS. Ignore types for uniform arguments. 2021-03-19 Jakub Jelinek Backported from master: 2021-03-11 Jakub Jelinek PR ipa/99517 * ipa-icf-gimple.c (func_checker::compare_gimple_call): For internal function calls with lhs fail if the lhs don't have compatible types. 2021-03-19 Jakub Jelinek Backported from master: 2021-03-04 Jakub Jelinek PR middle-end/93235 * expmed.c (store_bit_field_using_insv): Return false of xop0 is a SUBREG and a SUBREG to op_mode can't be created. 2021-03-19 Jakub Jelinek Backported from master: 2021-03-03 Jakub Jelinek PR target/99085 * cfgrtl.c (fixup_partitions): When changing some bbs from hot to cold partitions, if in non-layout mode after reorder_blocks also move affected blocks to ensure a single partition transition. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-24 Jakub Jelinek PR tree-optimization/99225 * fold-const.c (fold_binary_loc) : In (x & (1 << y)) != 0 to ((x >> y) & 1) != 0 simplifications use build_one_cst instead of build_int_cst (..., 1). Formatting fixes. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-23 Jakub Jelinek PR tree-optimization/99204 * fold-const.c (fold_read_from_constant_string): Check that tree_fits_uhwi_p (index) rather than just that index is INTEGER_CST. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-19 Jakub Jelinek PR ipa/99034 * tree-cfg.c (gimple_merge_blocks): If bb a starts with eh landing pad or non-local label, put FORCED_LABELs from bb b after that label rather than before it. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-15 Jakub Jelinek PR tree-optimization/99079 * match.pd (A % (pow2pcst << N) -> A & ((pow2pcst << N) - 1)): Remove useless tree_nop_conversion_p (type, TREE_TYPE (@3)) check. Instead require both type and TREE_TYPE (@1) to be integral types and either type having smaller or equal precision, or TREE_TYPE (@1) being unsigned type, or type being signed type. If TREE_TYPE (@1) doesn't have wrapping overflow, perform the subtraction of one in unsigned type. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-10 Jakub Jelinek PR c++/99035 * varasm.c (declare_weak): For -fsyntax-only, allow even TREE_ASM_WRITTEN function decls. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-10 Jakub Jelinek PR middle-end/99007 * gimplify.c (gimplify_scan_omp_clauses): For MEM_REF on reductions, temporarily disable gimplify_ctxp->into_ssa around gimplify_expr calls. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-03 Jakub Jelinek PR middle-end/97487 * ifcvt.c (noce_can_force_operand): New function. (noce_emit_move_insn): Use it. (noce_try_sign_mask): Likewise. Formatting fix. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-03 Jakub Jelinek PR middle-end/97971 * lra-constraints.c (process_alt_operands): For inline asm, don't call fatal_insn, but instead return false. 2021-03-19 Jakub Jelinek Backported from master: 2021-02-03 Jakub Jelinek PR tree-optimization/98287 * config/i386/mmx.md (3): For shifts don't enable expander for V1DImode. 2021-03-19 Eric Botcazou PR middle-end/99641 * fold-const.c (native_encode_initializer) : For an array type, do the computation of the current position in sizetype. 2021-03-18 Sinan Lin Backported from master: 2021-03-18 Sinan Lin Kito Cheng * config/riscv/riscv.c (riscv_block_move_straight): Change type to unsigned HOST_WIDE_INT for parameter and local variable with HOST_WIDE_INT type. (riscv_adjust_block_mem): Ditto. (riscv_block_move_loop): Ditto. (riscv_expand_block_move): Ditto. 2021-03-18 Kyrylo Tkachov Backported from master: 2021-03-18 Kyrylo Tkachov * config/aarch64/aarch64.c (aarch64_adjust_generic_arch_tuning): Define. (aarch64_override_options_internal): Use it. (generic_tunings): Add AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS to tune_flags. 2021-03-17 Kyrylo Tkachov Backported from master: 2021-03-17 Kyrylo Tkachov * config/aarch64/aarch64-builtins.c (aarch64_expand_rng_builtin): Use EQ to compare against CC_REG rather than NE. 2021-03-17 Peter Bergner * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Handle disassembling a vector pair vector by vector in little-endian mode. 2021-03-16 Martin Jambor Backported from master: 2021-03-05 Martin Jambor PR ipa/98078 * cgraph.c (cgraph_edge::set_call_stmt): Do not update all corresponding speculative edges if we are about to resolve sepculation. Make edge direct (and so resolve speculations) before removing it from call_site_hash. (cgraph_edge::make_direct): Relax the initial assert to allow calling the function on speculative direct edges. 2021-03-16 Richard Biener Backported from master: 2021-02-24 Richard Biener PR c/99224 * builtins.c (fold_builtin_next_arg): Avoid NULL arg. 2021-03-16 Richard Biener Backported from master: 2021-02-25 Richard Biener PR tree-optimization/99253 * tree-vect-loop.c (check_reduction_path): First compute code, then verify out-of-loop uses. 2021-03-15 Tobias Burnus Backported from master: 2021-03-08 Tobias Burnus PR fortran/97927 * tree-nested.c (convert_local_reference_stmt): Avoid calling lookup_field_for_decl for Fortran module (= namespace context). 2021-03-15 Andre Vieira Backported from master: 2021-02-22 Andre Vieira PR rtl-optimization/98791 * ira-conflicts.c (process_regs_for_copy): Don't create allocno copies for unordered modes. 2021-03-12 Kyrylo Tkachov * config/aarch64/aarch64.c (neoversen2_tunings): Set AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune_flags. 2021-03-11 Alex Coplan Backported from master: 2021-03-04 Alex Coplan PR target/99381 * config/aarch64/aarch64-sve-builtins.cc (function_resolver::require_vector_type): Handle error_mark_node. 2021-03-10 Peter Bergner Backported from master: 2021-03-08 Peter Bergner PR target/98959 * config/rs6000/rs6000.c (rs6000_emit_le_vsx_permute): Add an assert to ensure we do not have an Altivec style address. * config/rs6000/vsx.md (*vsx_le_perm_load_): Disable if passed an Altivec style address. (*vsx_le_perm_store_): Likewise. (splitters after *vsx_le_perm_store_): Likewise. (vsx_load_): Disable special expander if passed an Altivec style address. (vsx_store_): Likewise. 2021-03-10 Peter Bergner Backported from master: 2021-02-26 Peter Bergner PR target/99279 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Replace assert with an "if" test. 2021-03-10 Peter Bergner Backported from master: 2021-02-23 Peter Bergner * config/rs6000/mma.md (mma_assemble_pair): Rename from this... (vsx_assemble_pair): ...to this. * config/rs6000/rs6000-builtin.def (BU_MMA_V2, BU_MMA_V3, BU_COMPAT): New macros. (mma_assemble_pair): Rename from this... (vsx_assemble_pair): ...to this. (mma_disassemble_pair): Rename from this... (vsx_disassemble_pair): ...to this. (mma_assemble_pair): New compatibility built-in. (mma_disassemble_pair): Likewise. * config/rs6000/rs6000-call.c (struct builtin_compatibility): New. (RS6000_BUILTIN_COMPAT): Define. (bdesc_compat): New. (rs6000_gimple_fold_mma_builtin): Use VSX_BUILTIN_ASSEMBLE_PAIR. (rs6000_init_builtins): Register compatibility built-ins. (mma_init_builtins): Use VSX_BUILTIN_ASSEMBLE_PAIR, and VSX_BUILTIN_DISASSEMBLE_PAIR. * doc/extend.texi (__builtin_mma_assemble_pair): Rename from this... (__builtin_vsx_assemble_pair): ...to this. (__builtin_mma_disassemble_pair): Rename from this... (__builtin_vsx_disassemble_pair): ...to this. 2021-03-10 Peter Bergner Backported from master: 2021-02-11 Peter Bergner PR target/99041 * config/rs6000/predicates.md (mma_assemble_input_operand): Restrict memory addresses that are legal for quad word accesses. 2021-03-09 Eric Botcazou PR c++/90448 * calls.c (initialize_argument_information): When the argument is passed by reference, do not make a copy in a thunk only if the argument is already in memory. Remove redundant test for the case of callee copy. 2021-03-08 Kyrylo Tkachov * config/aarch64/aarch64-tuning-flags.def (cse_sve_vl_constants): Define. * config/aarch64/aarch64.md (add3): Force CONST_POLY_INT immediates into a register when the above is enabled. * config/aarch64/aarch64.c (neoversev1_tunings): AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. (aarch64_rtx_costs): Use AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. 2021-03-04 Jason Merrill PR c++/96078 * cgraphunit.c (process_function_and_variable_attributes): Don't warn about flatten on an alias if the target also has it. * cgraph.h (symtab_node::get_alias_target_tree): New. 2021-03-03 Eric Botcazou PR target/99234 * config/i386/i386.c (ix86_compute_frame_layout): For a SEH target, point back the hard frame pointer to its default location when the frame is larger than SEH_MAX_FRAME_SIZE. 2021-03-03 Richard Biener Backported from master: 2021-01-20 Richard Biener PR tree-optimization/98758 * tree-data-ref.c (int_divides_p): Use lambda_int arguments. (lambda_matrix_right_hermite): Avoid undefinedness with signed integer abs and multiplication. (analyze_subscript_affine_affine): Use lambda_int. 2021-03-03 Richard Biener Backported from master: 2021-01-13 Richard Biener PR tree-optimization/98640 * tree-ssa-sccvn.c (visit_nary_op): Do not try to handle plus or minus from a truncated operand to be sign-extended. 2021-03-03 Richard Biener Backported from master: 2021-01-11 Richard Biener PR tree-optimization/98526 * tree-vect-loop.c (vect_model_reduction_cost): Remove costing of the actual reduction op for the regular case. (vectorizable_reduction): Cost the stmts vect_transform_reduction produces here. 2021-03-03 Richard Biener PR tree-optimization/97897 * tree-complex.c (complex_propagate::visit_stmt): Make sure abnormally used SSA names are VARYING. (complex_propagate::visit_phi): Likewise. 2021-03-03 Tom de Vries Backported from master: 2021-02-05 Tom de Vries PR debug/98656 * tree-switch-conversion.c (jump_table_cluster::emit): Add loc argument. (bit_test_cluster::emit): Reuse location_t for newly created gswitch statement. (switch_decision_tree::try_switch_expansion): Preserve location_t. * tree-switch-conversion.h: Change function signatures. 2021-03-02 Jan Hubicka Backported from master: 2021-03-01 Jan Hubicka PR ipa/98338 * ipa-fnsummary.c (compute_fn_summary): Fix sanity check. 2021-03-02 Kito Cheng Backported from master: 2020-07-09 Kito Cheng * config/riscv/riscv.md (get_thread_pointer): New. (TP_REGNUM): Ditto. * doc/extend.texi (Target Builtins): Add RISC-V built-in section. Document __builtin_thread_pointer. 2021-03-01 Richard Earnshaw PR target/99271 * config/arm/thumb2.md (nonsecure_call_reg_thumb2_fpcxt): New pattern. (nonsecure_call_value_reg_thumb2_fpcxt): Likewise. (nonsecure_call_reg_thumb2): Restrict to using r4 for the callee address and disable when the FPCXT is not available. (nonsecure_call_value_reg_thumb2): Likewise. 2021-03-01 Eric Botcazou PR target/99234 * config/i386/i386.c (ix86_compute_frame_layout): For a SEH target, point the hard frame pointer to the SSE register save area instead of the general register save area. Perform only minimal adjustment for small frames if it is initially not correctly aligned. (ix86_expand_prologue): Remove early saves for a SEH target. * config/i386/winnt.c (struct seh_frame_state): Document constraint. 2021-02-23 Qian Jianhua * config/aarch64/aarch64-cost-tables.h (a64fx_extra_costs): New. * config/aarch64/aarch64.c (a64fx_addrcost_table): New. (a64fx_regmove_cost, a64fx_vector_cost): New. (a64fx_tunings): Use the new added cost tables. 2021-02-22 John David Anglin PR target/85074 * config/pa/pa.c (TARGET_ASM_CAN_OUTPUT_MI_THUNK): Define as hook_bool_const_tree_hwi_hwi_const_tree_true. (pa_asm_output_mi_thunk): Add support for nonzero vcall_offset. 2021-02-19 Kyrylo Tkachov * config/aarch64/aarch64-tuning-flags.def (prefer_advsimd_autovec): Define. * config/aarch64/aarch64.c (neoversev1_tunings): Use it. (aarch64_override_options_internal): Adjust aarch64_autovec_preference param when prefer_advsimd_autovec is enabled. 2021-02-15 Eric Botcazou * df-core.c (df_worklist_dataflow_doublequeue): Use proper cast. 2021-02-11 Eric Botcazou * config/i386/winnt.c (i386_pe_seh_unwind_emit): When switching to the cold section, emit a nop before the directive if the previous active instruction can throw. 2021-02-09 Eric Botcazou PR rtl-optimization/96015 * reorg.c (skip_consecutive_labels): Minor comment tweaks. (relax_delay_slots): When deleting a jump to the next active instruction over a barrier, first delete the barrier if the jump is the only way to reach the target label. 2021-02-04 Vladimir N. Makarov PR target/97701 * lra-constraints.c (in_class_p): Don't narrow class only for REG or MEM. 2021-02-03 Richard Biener Jakub Jelinek PR rtl-optimization/98863 * config/i386/i386-features.c (remove_partial_avx_dependency): Do not perform DF analysis. (pass_data_remove_partial_avx_dependency): Remove TODO_df_finish. 2021-02-03 Richard Biener Backported from master: 2021-02-01 Richard Biener PR rtl-optimization/98863 * config/i386/i386-features.c (convert_scalars_to_vector): Set DF_RD_PRUNE_DEAD_DEFS. 2021-02-03 Richard Biener Backported from master: 2021-01-29 Richard Biener PR rtl-optimization/98144 * df.h (df_mir_bb_info): Add con_visited member. * df-problems.c (df_mir_alloc): Initialize con_visited, do not fully populate IN and OUT. (df_mir_reset): Likewise. (df_mir_confluence_0): Set con_visited. (df_mir_confluence_n): Properly handle implicitely fully populated IN and OUT as designated by con_visited and update con_visited accordingly. 2021-02-01 Richard Biener Backported from master: 2021-01-29 Richard Biener PR rtl-optimization/98863 * gcse.c (gcse_or_cprop_is_too_expensive): Use unsigned HOST_WIDE_INT for the memory estimate. 2021-02-01 Kito Cheng Backported from master: 2020-11-06 Kito Cheng PR target/96307 * toplev.c (process_options): Remove param_asan_stack checking for kasan option checking. 2021-01-31 Eric Botcazou * system.h (SIZE_MAX): Define if not already defined. 2021-01-29 Jakub Jelinek PR debug/98331 * cfgbuild.c (find_bb_boundaries): Reset debug_insn when seeing a BARRIER. 2021-01-29 Jakub Jelinek PR target/98853 * config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use %w0, %w1 and %2 instead of %0, %1 and %2. 2021-01-29 Jakub Jelinek PR target/98681 * config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p): Use UINTVAL (shft_amnt) and UINTVAL (mask) instead of INTVAL (shft_amnt) and INTVAL (mask). Add && INTVAL (mask) > 0 condition. 2021-01-29 Jakub Jelinek PR testsuite/98771 * fold-const-call.c (host_size_t_cst_p): Renamed to ... (size_t_cst_p): ... this. Check and store unsigned HOST_WIDE_INT value rather than host size_t. (fold_const_call): Change type of s2 from size_t to unsigned HOST_WIDE_INT. Use size_t_cst_p instead of host_size_t_cst_p. For strncmp calls, pass MIN (s2, SIZE_MAX) instead of s2 as last argument. 2021-01-29 Jakub Jelinek PR testsuite/97301 * config/rs6000/mmintrin.h (__m64): Add __may_alias__ attribute. 2021-01-29 Jakub Jelinek PR tree-optimization/90248 * match.pd (X cmp 0.0 ? 1.0 : -1.0 -> copysign(1, +-X), X cmp 0.0 ? -1.0 : +1.0 -> copysign(1, -+X)): Remove simplifications. (X * (X cmp 0.0 ? 1.0 : -1.0) -> +-abs(X), X * (X cmp 0.0 ? -1.0 : 1.0) -> +-abs(X)): New simplifications. 2021-01-29 Jakub Jelinek PR tree-optimization/98255 * tree-dfa.c (get_ref_base_and_extent): For ARRAY_REFs, sign extend index - low_bound from sizetype's precision rather than index precision. (get_addr_base_and_unit_offset_1): Likewise. * tree-ssa-sccvn.c (ao_ref_init_from_vn_reference): Likewise. * gimple-fold.c (fold_const_aggregate_ref_1): Likewise. 2021-01-29 Bin Cheng Richard Biener PR tree-optimization/97627 * tree-ssa-loop-niter.c (number_of_iterations_exit_assumptions): Do not analyze fake edges. 2021-01-27 Kyrylo Tkachov Backported from master: 2021-01-22 Kyrylo Tkachov PR tree-optimization/98766 * tree-ssa-math-opts.c (convert_mult_to_fma): Use maybe_le when comparing against type size with param_avoid_fma_max_bits. 2021-01-26 Martin Liska PR gcov-profile/98739 * common.opt: Add missing equal symbol. 2021-01-25 Sebastian Huber Backported from master: 2021-01-25 Sebastian Huber * config/rtems.h (STARTFILE_SPEC): Remove qnolinkcmds. (ENDFILE_SPEC): Evaluate qnolinkcmds. 2021-01-25 Sebastian Huber Backported from master: 2021-01-25 Sebastian Huber * config/rtems.h (STARTFILE_SPEC): Remove nostdlib and nostartfiles handling since this is already done by LINK_COMMAND_SPEC. Evaluate qnolinkcmds. (ENDFILE_SPEC): Remove nostdlib and nostartfiles handling since this is already done by LINK_COMMAND_SPEC. (LIB_SPECS): Remove nostdlib and nodefaultlibs handling since this is already done by LINK_COMMAND_SPEC. Remove qnolinkcmds evaluation. 2021-01-25 Claudiu Zissulescu Backported from master: 2020-12-11 Claudiu Zissulescu * config/arc/arc.md (mpyd_arcv2hs): New template pattern. (*pmpyd_arcv2hs): Likewise. (*pmpyd_imm_arcv2hs): Likewise. (mpyd_arcv2hs): Moved into above template. (mpyd_imm_arcv2hs): Moved into above template. (mpydu_arcv2hs): Likewise. (mpydu_imm_arcv2hs): Likewise. (su_optab): New optab prefix for sign/zero-extending operations. 2021-01-22 Richard Sandiford Backported from master: 2021-01-20 Richard Sandiford PR tree-optimization/98535 * tree-vect-slp.c (duplicate_and_interleave): Use quick_grow_cleared. If the high and low permutes are the same, remove the high permutes from the working set and only continue with the low ones. 2021-01-21 Christophe Lyon * config/arm/arm_mve.h (__arm_vcmpneq_s8): Fix return type. 2021-01-19 Martin Jambor Backported from master: 2021-01-19 Martin Jambor PR ipa/98690 * ipa-sra.c (ssa_name_only_returned_p): New parameter fun. Check whether non-call exceptions allow removal of a statement. (isra_analyze_call): Pass the appropriate function to ssa_name_only_returned_p. 2021-01-19 Daniel Hellstrom Backported from master: 2021-01-19 Daniel Hellstrom * config/sparc/rtemself.h (TARGET_OS_CPP_BUILTINS): Add built-in define __FIX_LEON3FT_TN0018. 2021-01-14 Thomas Schwinge Backported from master: 2021-01-14 Thomas Schwinge * config/gcn/mkoffload.c (main): Create an offload image only in 64-bit configurations. 2021-01-13 Samuel Thibault Backported from master: 2021-01-13 Samuel Thibault * config.gcc [$target == *-*-gnu*]: Enable 'default_gnu_indirect_function'. 2021-01-12 Richard Biener Backported from master: 2021-01-06 Richard Biener PR tree-optimization/98513 * value-range.cc (intersect_ranges): Compare the upper bounds for the expected relation. 2021-01-12 Richard Biener Backported from master: 2021-01-04 Richard Biener PR tree-optimization/98282 * tree-ssa-sccvn.c (vn_get_stmt_kind): Classify tcc_reference on invariants as VN_NARY. 2021-01-12 Richard Sandiford Backported from master: 2020-12-31 Richard Sandiford PR tree-optimization/94994 * tree-vect-data-refs.c (vect_vfa_align): Use dr_alignment. 2021-01-12 Richard Sandiford Backported from master: 2021-01-04 Richard Sandiford PR tree-optimization/95401 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::load_store_cookie): Use bits rather than bytes for the alignment argument to IFN_MASK_LOAD and IFN_MASK_STORE. * gimple-fold.c (gimple_fold_mask_load_store_mem_ref): Likewise. * tree-vect-stmts.c (vectorizable_store): Likewise. (vectorizable_load): Likewise. 2021-01-12 Richard Sandiford Backported from master: 2021-01-05 Richard Sandiford PR rtl-optimization/97144 * recog.c (constrain_operands): Initialize matching_operand for each alternative, rather than only doing it once. 2021-01-12 Richard Sandiford Backported from master: 2020-12-31 Richard Sandiford PR rtl-optimization/98214 * genmodes.c (emit_insn_modes_h): Emit a definition of CONST_MODE_MASK. (emit_mode_mask): Treat mode_mask_array as non-constant if adj_nunits. (emit_mode_adjustments): Update GET_MODE_MASK when updating GET_MODE_NUNITS. * machmode.h (mode_mask_array): Use CONST_MODE_MASK. 2021-01-12 Richard Sandiford Backported from master: 2020-12-31 Richard Sandiford PR tree-optimization/98302 * tree-vect-patterns.c (vect_determine_precisions_from_users): Make sure that the precision remains greater than the shift count. 2021-01-12 Richard Sandiford Backported from master: 2021-01-05 Richard Sandiford PR tree-optimization/98371 * tree-vect-loop.c (vect_reanalyze_as_main_loop): New function. (vect_analyze_loop): If an epilogue loop appears to be cheaper than the main loop, re-analyze it as a main loop before adopting it as a main loop. 2021-01-12 Richard Sandiford Backported from master: 2021-01-04 Richard Sandiford PR target/89057 * config/aarch64/aarch64-simd.md (aarch64_combine): Accept aarch64_simd_reg_or_zero for operand 2. Use the combinez patterns to handle zero operands. 2021-01-12 Richard Sandiford Backported from master: 2020-12-18 Richard Sandiford * config/aarch64/aarch64.c (aarch64_preferred_simd_mode): Use aarch64_full_sve_mode and aarch64_vq_mode directly, instead of going via aarch64_simd_container_mode. 2021-01-12 Andreas Krebbel Backported from master: 2021-01-11 Andreas Krebbel PR tree-optimization/98221 * tree-ssa-forwprop.c (simplify_vector_constructor): For big-endian, use UNPACK[_FLOAT]_HI. 2021-01-11 Richard Biener Backported from master: 2020-12-07 Richard Biener PR tree-optimization/98117 * tree-vect-loop-manip.c (vect_gen_vector_loop_niters): Properly handle degenerate niter when setting the vector loop IV range. 2021-01-11 Richard Biener PR tree-optimization/97623 * tree-ssa-pre.c (insert): Move hoist insertion after PRE insertion iteration and do not iterate it. (create_expression_by_pieces): Guard NEW_SETS access. (insert_into_preds_of_block): Likewise. 2021-01-11 Richard Biener Backported from master: 2020-10-30 Richard Biener PR tree-optimization/97623 * tree-ssa-pre.c (insert): First do hoist insertion in a backward walk. 2021-01-09 Jakub Jelinek Backported from master: 2021-01-09 Jakub Jelinek PR c++/98556 * tree-cfg.c (verify_gimple_assign_binary): Allow lhs of POINTER_DIFF_EXPR to be any integral type. 2021-01-07 Claudiu Zissulescu Backported from master: 2020-12-11 Claudiu Zissulescu * config/arc/arc-protos.h (arc_scheduling_not_expected): Remove it. (arc_sets_cc_p): Likewise. (arc_need_delay): Likewise. * config/arc/arc.c (arc_sets_cc_p): Likewise. (arc_need_delay): Likewise. (arc_scheduling_not_expected): Likewise. * config/arc/arc.md: Convert adc/sbc patterns to simple instruction definitions. 2021-01-06 Jakub Jelinek Backported from master: 2021-01-05 Jakub Jelinek PR tree-optimization/98514 * tree-ssa-reassoc.c (bb_rank): Change type from long * to int64_t *. (operand_rank): Change type from hash_map to hash_map. (phi_rank): Change return type from long to int64_t. (loop_carried_phi): Change block_rank variable type from long to int64_t. (propagate_rank): Change return type, rank parameter type and op_rank variable type from long to int64_t. (find_operand_rank): Change return type from long to int64_t and change slot variable type from long * to int64_t *. (insert_operand_rank): Change rank parameter type from long to int64_t. (get_rank): Change return type and rank variable type from long to int64_t. Use PRId64 instead of ld to print the rank. (init_reassoc): Change rank variable type from long to int64_t and adjust correspondingly bb_rank and operand_rank initialization. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-31 Jakub Jelinek PR tree-optimization/98474 * wide-int.cc (wi::to_mpz): If wide_int has MSB set, but type is unsigned and excess negative, append set bits after len until precision. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-21 Jakub Jelinek PR c++/98353 * gimplify.c (gimplify_init_ctor_eval_range): Gimplify value before storing it into cref. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-21 Jakub Jelinek PR c++/98383 * gimplify.c (struct gimplify_omp_ctx): Add in_for_exprs flag. (gimple_add_tmp_var): For addressable temporaries appearing in simd lb, b or incr expressions, don't add a private clause unless it is seen also outside of those expressions in the simd body. (omp_notice_variable): Likewise. (gimplify_omp_for): Set and reset in_for_exprs around gimplification of lb, b or incr expressions. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-18 Jakub Jelinek * gimplify.c (struct gimplify_omp_ctx): Add has_depend member. (gimplify_scan_omp_clauses): Set it to true if OMP_CLAUSE_DEPEND appears on OMP_TASK. (gimplify_adjust_omp_clauses_1, gimplify_adjust_omp_clauses): Force GOVD_WRITTEN on shared variables if task construct has depend clause. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-12 Jakub Jelinek PR middle-end/98183 * omp-low.c (lower_omp_target): Don't add OMP_RETURN for data regions. * omp-expand.c (expand_omp_target): Don't try to remove OMP_RETURN for data regions. (build_omp_regions_1, omp_make_gimple_edges): Don't expect OMP_RETURN for data regions. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-10 Jakub Jelinek PR middle-end/98205 * omp-expand.c (expand_omp_for_generic): Fix up broken_loop handling. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-08 Jakub Jelinek PR target/94440 * config/i386/i386.opt (ix86_excess_precision, ix86_unsafe_math_optimizations): New TargetVariables. * config/i386/i386.h (X87_ENABLE_ARITH, X87_ENABLE_FLOAT): Use ix86_unsafe_math_optimizations instead of flag_unsafe_math_optimizations and ix86_excess_precision instead of flag_excess_precision. * config/i386/i386.c (ix86_excess_precision): Rename to ... (ix86_get_excess_precision): ... this. (TARGET_C_EXCESS_PRECISION): Define to ix86_get_excess_precision. * config/i386/i386-options.c (ix86_valid_target_attribute_tree, ix86_option_override_internal): Update ix86_unsafe_math_optimization from flag_unsafe_math_optimizations and ix86_excess_precision from flag_excess_precision when constructing target option nodes. (ix86_set_current_function): If flag_unsafe_math_optimizations or flag_excess_precision is different from the one recorded in TARGET_OPTION_NODE, create a new target option node for the current function and switch to that. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-04 Jakub Jelinek PR target/98100 * cfgexpand.c (expand_gimple_basic_block): For vars with vector type, use TYPE_MODE rather than DECL_MODE. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-02 Jakub Jelinek * dwarf2out.c (add_scalar_info): Only use add_AT_wide for 128-bit constants and only in dwarf-5 or later, where DW_FORM_data16 is available. Otherwise use DW_FORM_block*/DW_FORM_exprloc with DW_OP_implicit_value to describe the constant. 2021-01-06 Scott Snyder Backported from master: 2020-12-02 Scott Snyder PR plugins/98059 * vec.h (auto_delete_vec): Use DISABLE_COPY_AND_ASSIGN(auto_delete_vec) instead of DISABLE_COPY_AND_ASSIGN(auto_delete_vec) to make it valid C++20 after DR2237. 2021-01-06 Jakub Jelinek Backported from master: 2020-12-01 Jakub Jelinek PR target/98063 * config/i386/i386-expand.c (ix86_expand_call): Handle non-plt CM_LARGE_PIC calls. 2021-01-05 Uroš Bizjak PR target/98522 * config/i386/sse.md (sse_cvtps2pi): Redefine as define_insn_and_split. Clear the top 64 bytes of the input XMM register. (sse_cvttps2pi): Ditto. 2021-01-05 Uroš Bizjak PR target/98521 * config/i386/xopintrin.h (_mm256_cmov_si256): New. 2021-01-03 Iain Sandoe Jakub Jelinek PR target/97865 * configure: Regenerate. 2021-01-01 Iain Sandoe * config/darwin-driver.c (validate_macosx_version_min): Allow MACOSX_DEPLOYMENT_TARGET=11. (darwin_default_min_version): Adjust warning spelling to avoid an apostrophe. 2021-01-01 Iain Sandoe * config/darwin-driver.c (darwin_find_version_from_kernel): Compute the minor OS version from the minor kernel version. 2021-01-01 Iain Sandoe Backported from master: 2020-11-06 Iain Sandoe * config/darwin-c.c: Allow for Darwin20 to correspond to macOS 11. * config/darwin-driver.c: Likewise. 2021-01-01 Iain Sandoe Backported from master: 2020-11-01 Iain Sandoe * config/host-darwin.c: Align pch_address_space to 16384. 2021-01-01 Francois-Xavier Coudert * config/aarch64/aarch64-builtins.c (aarch64_init_memtag_builtins): Manually initialize instead of using a C++11 brace-init-list. 2021-01-01 Francois-Xavier Coudert * config/aarch64/driver-aarch64.c (aarch64_get_extension_string_for_isa_flags): Adjust signature. 2020-12-28 Uroš Bizjak PR target/96793 * config/i386/i386-expand.c (ix86_expand_rint): Remove the sign of the intermediate value for flag_rounding_math. 2020-12-28 Piotr Kubaj Backported from master: 2020-12-16 Piotr Kubaj * config.gcc (powerpc*le-*-freebsd*): Add. * configure.ac (powerpc*le-*-freebsd*): Ditto. * configure: Regenerate. * config/rs6000/freebsd64.h (ASM_SPEC_COMMON): Use ENDIAN_SELECT. (DEFAULT_ASM_ENDIAN): Add little endian support. (LINK_OS_FREEBSD_SPEC64): Ditto. 2020-12-24 Roman Zhuykov Backported from master: 2020-12-05 Roman Zhuykov PR rtl-optimization/97421 * modulo-sched.c (generate_prolog_epilog): Remove forward declaration, adjust last argument name and type. (const_iteration_count): Add bool pointer parameter to return whether count register is read in pre-header after its initialization. (sms_schedule): Fix count register initialization adjustment procedure according to what const_iteration_count said. 2020-12-23 Piotr Kubaj Gerald Pfeifer * config/rs6000/freebsd64.h (PROCESSOR_DEFAULT): Update to PROCESSOR_PPC7450. (PROCESSOR_DEFAULT64): Update to PROCESSOR_POWER8. 2020-12-23 Uroš Bizjak PR target/96793 * config/i386/i386-expand.c (ix86_expand_truncdf_32): Remove the sign of the intermediate value for flag_rounding_math. 2020-12-22 Uroš Bizjak PR target/96793 * config/i386/i386-expand.c (ix86_expand_floorceil): Remove the sign of the intermediate value for flag_rounding_math. (ix86_expand_floorceildf_32): Ditto. 2020-12-15 Andrea Corallo PR rtl-optimization/97092 * ira-color.c (update_costs_from_allocno): Do not carry over mode between subsequent iterations. 2020-12-14 Wilco Dijkstra * config.gcc (aarch64*-*-*): Add --with-tune. Support --with-cpu=native. * config/aarch64/aarch64.h (OPTION_DEFAULT_SPECS): Add --with-tune. 2020-12-14 Sebastian Pop * config.gcc (aarch64*-*-*): Remove --with-{cpu,arch,tune}-32 flags. 2020-12-11 Dennis Zhang Backported from master: 2020-11-03 Dennis Zhang * config/aarch64/aarch64-simd-builtins.def (vget_lo_half): New entry. (vget_hi_half): Likewise. * config/aarch64/aarch64-simd.md (aarch64_vget_lo_halfv8bf): New entry. (aarch64_vget_hi_halfv8bf): Likewise. * config/aarch64/arm_neon.h (vget_low_bf16): New intrinsic. (vget_high_bf16): Likewise. 2020-12-11 Dennis Zhang Backported from master: 2020-11-03 Dennis Zhang * config/aarch64/aarch64-simd-builtins.def(vbfcvt): New entry. (vbfcvt_high, bfcvt): Likewise. * config/aarch64/aarch64-simd.md(aarch64_vbfcvt): New entry. (aarch64_vbfcvt_highv8bf, aarch64_bfcvtsf): Likewise. * config/aarch64/arm_bf16.h (vcvtah_f32_bf16): New intrinsic. * config/aarch64/arm_neon.h (vcvt_f32_bf16): Likewise. (vcvtq_low_f32_bf16, vcvtq_high_f32_bf16): Likewise. 2020-12-11 Andrea Corallo * config/arm/arm_neon.h (vst2_lane_bf16, vst2q_lane_bf16) (vst3_lane_bf16, vst3q_lane_bf16, vst4_lane_bf16) (vst4q_lane_bf16): New intrinsics. * config/arm/arm_neon_builtins.def: Touch it for: __builtin_neon_vst2_lanev4bf, __builtin_neon_vst2_lanev8bf, __builtin_neon_vst3_lanev4bf, __builtin_neon_vst3_lanev8bf, __builtin_neon_vst4_lanev4bf,__builtin_neon_vst4_lanev8bf. 2020-12-11 Andrea Corallo * config/arm/arm_neon.h (vld2_lane_bf16, vld2q_lane_bf16) (vld3_lane_bf16, vld3q_lane_bf16, vld4_lane_bf16) (vld4q_lane_bf16): Add intrinsics. * config/arm/arm_neon_builtins.def: Touch for: __builtin_neon_vld2_lanev4bf, __builtin_neon_vld2_lanev8bf, __builtin_neon_vld3_lanev4bf, __builtin_neon_vld3_lanev8bf, __builtin_neon_vld4_lanev4bf, __builtin_neon_vld4_lanev8bf. * config/arm/iterators.md (VQ_HS): Add V8BF to the iterator. 2020-12-11 Andrea Corallo * config/arm/arm_neon.h (vst1_bf16, vst1q_bf16): Add intrinsics. * config/arm/arm_neon_builtins.def : Touch for: __builtin_neon_vst1v4bf, __builtin_neon_vst1v8bf. 2020-12-11 Andrea Corallo * config/arm/arm-builtins.c (VAR14): Define macro. * config/arm/arm_neon_builtins.def: Touch for: __builtin_neon_vld1v4bf, __builtin_neon_vld1v8bf. * config/arm/arm_neon.h (vld1_bf16, vld1q_bf16): Add intrinsics. 2020-12-11 Andrea Corallo * config/arm/arm_neon.h (vst1_lane_bf16, vst1q_lane_bf16): Add intrinsics. * config/arm/arm_neon_builtins.def (STORE1LANE): Add v4bf, v8bf. 2020-12-11 Andrea Corallo * config/arm/arm_neon_builtins.def: Add to LOAD1LANE v4bf, v8bf. * config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add intrinsics. 2020-12-09 Kewen Lin Backported from master: 2020-08-19 Kewen Lin * opts-global.c (decode_options): Call target_option_override_hook before it prints for --help=*. 2020-12-08 Andrea Corallo * config/arm/arm.c (mve_vector_mem_operand): Fix unwanted fall-throughs. 2020-12-04 Hans-Peter Nilsson Backported from master: 2020-12-04 Hans-Peter Nilsson Martin Sebor PR middle-end/94600 * doc/implement-c.texi (Qualifiers implementation): Add blurb about access to the whole of a volatile aggregate object, only for same-size as a scalar object. 2020-12-04 Eric Botcazou * ipa-sra.c (verify_access_tree_1): Relax assertion on the size. 2020-12-03 Uros Bizjak Backported from master: 2020-12-03 Uroš Bizjak Jakub Jelinek PR target/98086 * config/i386/i386.c (ix86_md_asm_adjustmd): Rewrite zero-extension part to use convert_to_mode. 2020-12-03 Sebastian Huber Backported from master: 2020-12-03 Sebastian Huber * config/arm/t-rtems: Add "-mthumb -mcpu=cortex-r52 -mfloat-abi=hard" multilib. 2020-12-03 Richard Sandiford Backported from master: 2020-07-08 Richard Sandiford PR middle-end/95694 * expr.c (expand_expr_real_2): Get the mode from the type rather than the rtx, and assert that it is consistent with the mode of the rtx (where known). Optimize all constant integers, not just those that can be represented in poly_int64. 2020-12-02 Richard Sandiford Backported from master: 2020-10-28 Richard Sandiford PR tree-optimization/97457 * value-range.cc (irange::set): Don't decay POLY_INT_CST ranges to integer ranges. 2020-12-02 Richard Sandiford Backported from master: 2020-10-02 Richard Sandiford * config/aarch64/aarch64-protos.h (aarch64_sve_pred_dominates_p): Delete. * config/aarch64/aarch64.c (aarch64_sve_pred_dominates_p): Likewise. * config/aarch64/aarch64-sve.md: Add banner comment describing how merging predicated FP operations are represented. (*cond__2): Split into... (*cond__2_relaxed): ...this and... (*cond__2_strict): ...this. (*cond__any): Split into... (*cond__any_relaxed): ...this and... (*cond__any_strict): ...this. (*cond__2): Split into... (*cond__2_relaxed): ...this and... (*cond__2_strict): ...this. (*cond__any): Split into... (*cond__any_relaxed): ...this and... (*cond__any_strict): ...this. (*cond__2): Split into... (*cond__2_relaxed): ...this and... (*cond__2_strict): ...this. (*cond__2_const): Split into... (*cond__2_const_relaxed): ...this and... (*cond__2_const_strict): ...this. (*cond__3): Split into... (*cond__3_relaxed): ...this and... (*cond__3_strict): ...this. (*cond__any): Split into... (*cond__any_relaxed): ...this and... (*cond__any_strict): ...this. (*cond__any_const): Split into... (*cond__any_const_relaxed): ...this and... (*cond__any_const_strict): ...this. (*cond_add_2_const): Split into... (*cond_add_2_const_relaxed): ...this and... (*cond_add_2_const_strict): ...this. (*cond_add_any_const): Split into... (*cond_add_any_const_relaxed): ...this and... (*cond_add_any_const_strict): ...this. (*cond__2): Split into... (*cond__2_relaxed): ...this and... (*cond__2_strict): ...this. (*cond__any): Split into... (*cond__any_relaxed): ...this and... (*cond__any_strict): ...this. (*cond_sub_3_const): Split into... (*cond_sub_3_const_relaxed): ...this and... (*cond_sub_3_const_strict): ...this. (*aarch64_pred_abd): Split into... (*aarch64_pred_abd_relaxed): ...this and... (*aarch64_pred_abd_strict): ...this. (*aarch64_cond_abd_2): Split into... (*aarch64_cond_abd_2_relaxed): ...this and... (*aarch64_cond_abd_2_strict): ...this. (*aarch64_cond_abd_3): Split into... (*aarch64_cond_abd_3_relaxed): ...this and... (*aarch64_cond_abd_3_strict): ...this. (*aarch64_cond_abd_any): Split into... (*aarch64_cond_abd_any_relaxed): ...this and... (*aarch64_cond_abd_any_strict): ...this. (*cond__2): Split into... (*cond__2_relaxed): ...this and... (*cond__2_strict): ...this. (*cond__4): Split into... (*cond__4_relaxed): ...this and... (*cond__4_strict): ...this. (*cond__any): Split into... (*cond__any_relaxed): ...this and... (*cond__any_strict): ...this. (*cond__4): Split into... (*cond__4_relaxed): ...this and... (*cond__4_strict): ...this. (*cond__any): Split into... (*cond__any_relaxed): ...this and... (*cond__any_strict): ...this. (*aarch64_pred_fac): Split into... (*aarch64_pred_fac_relaxed): ...this and... (*aarch64_pred_fac_strict): ...this. (*cond__nontrunc): Split into... (*cond__nontrunc_relaxed): ...this and... (*cond__nontrunc_strict): ...this. (*cond__nonextend): Split into... (*cond__nonextend_relaxed): ...this and... (*cond__nonextend_strict): ...this. * config/aarch64/aarch64-sve2.md (*cond_): Split into... (*cond__relaxed): ...this and... (*cond__strict): ...this. (*cond__any): Split into... (*cond__any_relaxed): ...this and... (*cond__any_strict): ...this. (*cond_): Split into... (*cond__relaxed): ...this and... (*cond__strict): ...this. 2020-12-02 Richard Sandiford Backported from master: 2020-11-25 Richard Sandiford * config/aarch64/aarch64.c (aarch64_maybe_expand_sve_subreg_move): Do not optimize LRA subregs. * config/aarch64/aarch64-sve.md (@aarch64_pred_): Tie the input to the output. (@aarch64_sve_revbhw_): Likewise. (*2): Likewise. (@aarch64_pred_sxt): Likewise. (*cnot): Likewise. (@aarch64_pred_): Likewise. (@aarch64_sve__nontrunc): Likewise. (@aarch64_sve__trunc): Likewise. (@aarch64_sve__nonextend): Likewise. (@aarch64_sve__extend): Likewise. (@aarch64_sve__trunc): Likewise. (@aarch64_sve__trunc): Likewise. (@aarch64_sve__nontrunc): Likewise. * config/aarch64/aarch64-sve2.md (@aarch64_pred_): Likewise. (@aarch64_pred_): Likewise. (@aarch64_pred_): Likewise. (@aarch64_pred_): Likewise. 2020-12-02 Richard Sandiford Backported from master: 2020-11-30 Richard Sandiford PR rtl-optimization/98037 * dse.c (find_shift_sequence): Iterate over all integers and skip modes that are too small. 2020-12-02 Richard Biener Backported from master: 2020-09-04 Richard Biener PR tree-optimization/96698 PR tree-optimization/96920 * tree-vectorizer.h (loop_vec_info::reduc_latch_defs): Remove. (loop_vec_info::reduc_latch_slp_defs): Likewise. * tree-vect-stmts.c (vect_transform_stmt): Remove vectorized cycle PHI latch code. * tree-vect-loop.c (maybe_set_vectorized_backedge_value): New helper to set vectorized cycle PHI latch values. (vect_transform_loop): Walk over all PHIs again after vectorizing them, calling maybe_set_vectorized_backedge_value. Call maybe_set_vectorized_backedge_value for each vectorized stmt. Remove delayed update code. * tree-vect-slp.c (vect_analyze_slp_instance): Initialize SLP instance reduc_phis member. (vect_schedule_slp): Set vectorized cycle PHI latch values. 2020-12-02 Richard Biener Backported from master: 2020-08-26 Richard Biener PR tree-optimization/96698 * tree-vectorizer.h (loop_vec_info::reduc_latch_defs): New. (loop_vec_info::reduc_latch_slp_defs): Likewise. * tree-vect-stmts.c (vect_transform_stmt): Only record stmts to update PHI latches from, perform the update ... * tree-vect-loop.c (vect_transform_loop): ... here after vectorizing those PHIs. (info_for_reduction): Properly handle non-reduction PHIs. 2020-12-01 Richard Biener Backported from master: 2020-11-13 Richard Biener PR tree-optimization/97812 * tree-vrp.c (register_edge_assert_for_2): Extend the range according to its sign before seeing whether it fits. 2020-12-01 Richard Biener Backported from master: 2020-11-10 Richard Biener PR tree-optimization/97760 * tree-vect-loop.c (check_reduction_path): Reject reduction paths we do not handle in epilogue generation. 2020-12-01 Richard Biener Backported from master: 2020-10-26 Richard Biener PR tree-optimization/97539 * tree-vect-loop-manip.c (vect_do_peeling): Reset out-of-loop debug uses before peeling. 2020-12-01 Richard Biener Backported from master: 2020-05-18 Richard Biener PR middle-end/95171 * tree-inline.c (remap_gimple_stmt): Split out trapping compares when inlining into a non-call EH function. 2020-12-01 Richard Biener Backported from master: 2020-10-26 Richard Biener PR middle-end/97554 * sbitmap.c (sbitmap_vector_alloc): Use size_t for byte quantities to avoid overflow. 2020-11-28 Eric Botcazou PR target/97939 * config/sparc/predicates.md (arith_double_add_operand): Comment. * config/sparc/sparc.md (uaddvdi4): Use arith_double_operand. (addvdi4): Use arith_double_add_operand. (addsi3): Remove useless attributes. (addvsi4): Use arith_add_operand. (*cmp_ccv_plus): Likewise and add second alternative accordingly. (*cmp_ccxv_plus): Likewise. (*cmp_ccv_plus_set): Likewise. (*cmp_ccxv_plus_set): Likewise. (*cmp_ccv_plus_sltu_set): Likewise. (usubvdi4): Use arith_double_operand. (subvdi4): Use arith_double_add_operand. (subsi3): Remove useless attributes. (subvsi4): Use arith_add_operand. (*cmp_ccv_minus): Likewise and add second alternative accordingly. (*cmp_ccxv_minus): Likewise. (*cmp_ccv_minus_set): Likewise. (*cmp_ccxv_minus_set): Likewise. (*cmp_ccv_minus_sltu_set): Likewise. (negsi2): Use register_operand. (unegvsi3): Likewise. (negvsi3) Likewise. (*cmp_ccnz_neg): Likewise. (*cmp_ccxnz_neg): Likewise. (*cmp_ccnz_neg_set): Likewise. (*cmp_ccxnz_neg_set): Likewise. (*cmp_ccc_neg_set): Likewise. (*cmp_ccxc_neg_set): Likewise. (*cmp_ccc_neg_sltu_set): Likewise. (*cmp_ccv_neg): Likewise. (*cmp_ccxv_neg): Likewise. (*cmp_ccv_neg_set): Likewise. (*cmp_ccxv_neg_set): Likewise. (*cmp_ccv_neg_sltu_set): Likewise. 2020-11-28 Eric Botcazou PR target/96607 * config/sparc/sparc-protos.h (eligible_for_call_delay): Delete. * config/sparc/sparc.c (eligible_for_call_delay): Likewise. * config/sparc/sparc.md (in_call_delay): Likewise. (tls_delay_slot): New attribute. (define_delay [call]): Use in_branch_delay. (tgd_call): Set type to call_no_delay_slot when tls_delay_slot is false. (tldm_call): Likewise. 2020-11-27 Kyrylo Tkachov Backported from master: 2020-11-27 Kyrylo Tkachov * config/aarch64/aarch64.opt (-param=aarch64-autovec-preference): Define. * config/aarch64/aarch64.c (aarch64_override_options_internal): Set aarch64_sve_compare_costs to 0 when preferring only Advanced SIMD. (aarch64_cmp_autovec_modes): Define. (aarch64_preferred_simd_mode): Adjust to use the above. (aarch64_autovectorize_vector_modes): Likewise. * doc/invoke.texi: Document aarch64-autovec-preference param. 2020-11-25 Jakub Jelinek Backported from master: 2020-11-20 Jakub Jelinek PR target/97528 * config/arm/arm.c (neon_vector_mem_operand): For POST_MODIFY, require first POST_MODIFY operand is a REG and is equal to the first operand of PLUS. 2020-11-25 Jakub Jelinek Backported from master: 2020-11-14 Jakub Jelinek PR debug/97599 * dwarf2out.c (gen_subprogram_die): Call gen_unspecified_parameters_die even if not early dwarf, but only if subr_die is a newly created DIE. 2020-11-24 Jason Merrill PR c++/97918 * dwarf2out.c (dwarf2out_early_finish): flush_limbo_die_list after gen_scheduled_generic_parms_dies. 2020-11-24 Jason Merrill PR debug/97060 * dwarf2out.c (gen_subprogram_die): It's a declaration if DECL_INITIAL isn't set. 2020-11-24 Richard Earnshaw PR target/97534 * config/arm/arm.c (arm_split_atomic_op): Use gen_int_mode when negating a const_int. 2020-11-24 Thomas Schwinge Backported from master: 2020-11-24 Thomas Schwinge * omp-expand.c (expand_oacc_for): More explicit checking of which OMP constructs we're expecting. 2020-11-23 Matthew Malcomson * doc/install.texi: Document bootstrap-asan option. 2020-11-19 Alex Coplan Backported from master: 2020-11-12 Alex Coplan PR target/97730 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_bcax): Change to define_expand, add missing (trivially-predicated) not rtx to fix wrong code bug. (*aarch64_sve2_bcax): New. 2020-11-19 Uroš Bizjak PR target/97887 * config/i386/i386.md (*2_i387_1): Disable for TARGET_SSE_MATH modes. 2020-11-17 Sebastian Pop Backported from master: 2020-11-17 Sebastian Pop * config.gcc: add configure flags --with-{cpu,arch,tune}-{32,64} as alias flags for --with-{cpu,arch,tune} on AArch64. * doc/install.texi: Document new flags for aarch64. 2020-11-17 Sebastian Pop Backported from master: 2020-11-17 Sebastian Pop * config.gcc: Add --with-tune to AArch64 configure flags. 2020-11-17 Tamar Christina PR target/97535 * config/aarch64/aarch64.c (aarch64_expand_cpymem): Use unsigned arithmetic in check. 2020-11-17 Monk Chiang Backported from master: 2020-11-14 Monk Chiang PR target/97682 * config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Change register to t0. (RISCV_CALL_ADDRESS_TEMP_REGNUM): New Marco, define t1 register. (RISCV_CALL_ADDRESS_TEMP): Use it for call instructions. * config/riscv/riscv.c (riscv_legitimize_call_address): Use RISCV_CALL_ADDRESS_TEMP. (riscv_compute_frame_info): Change temporary register to t0 form t1. (riscv_trampoline_init): Adjust comment. 2020-11-16 Cui,Lili * config/i386/i386.h: Add PREFETCHW to march=broadwell. * doc/invoke.texi: Put PREFETCHW back to relation arch. 2020-11-13 Thomas Schwinge Backported from master: 2020-11-13 Thomas Schwinge * omp-low.c (scan_sharing_clauses, scan_omp_for) (lower_oacc_reductions, lower_omp_target): More explicit checking of which OMP constructs we're expecting. 2020-11-13 Thomas Schwinge Backported from master: 2020-11-13 Thomas Schwinge * omp-expand.c (expand_omp_target): Attach an attribute to all outlined OpenACC compute regions. * omp-offload.c (execute_oacc_device_lower): Adjust. 2020-11-12 Peter Bergner Backported from master: 2020-11-06 Peter Bergner * config/rs6000/rs6000.h (BIGGEST_ALIGNMENT): Revert previous commit so as not to break the ABI. * config/rs6000/rs6000-call.c (rs6000_init_builtins): Set the ABI mandated alignment for __vector_pair and __vector_quad types. 2020-11-11 liuhongt * config/i386/i386-options.c (ix86_option_override_internal): Handle PTA_CLDEMOTE. * config/i386/i386.h (PTA_CLDEMOTE): Define. 2020-11-10 Jakub Jelinek PR tree-optimization/97764 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): For little-endian stores with negative pd.offset, subtract BITS_PER_UNIT - amnt from size if amnt is non-zero. 2020-11-09 Sudakshina Das Backported from master: 2020-11-02 Sudakshina Das PR target/97638 * config/aarch64/aarch64-bti-insert.c (aarch64_pac_insn_p): Update return value on INSN_P check. 2020-11-09 Lili Cui PR target/97685 * config/i386/i386.h: (PTA_BROADWELL): Delete PTA_PRFCHW. (PTA_SILVERMONT): Add PTA_PRFCHW. (PTA_KNL): Add PTA_PREFETCHWT1. (PTA_TREMONT): Add PTA_MOVDIRI, PTA_MOVDIR64B, PTA_CLDEMOTE and PTA_WAITPKG. * doc/invoke.texi: Delete PREFETCHW for broadwell, skylake, knl, knm, skylake-avx512, cannonlake, icelake-client, icelake-server, cascadelake, cooperlake, tigerlake and sapphirerapids. Add PREFETCHW for silvermont, goldmont, goldmont-plus and tremont. Add XSAVEC and XSAVES for goldmont, goldmont-plus and tremont. Add MOVDIRI, MOVDIR64B, CLDEMOTE and WAITPKG for tremont. Add KEYLOCKER and HREST for alderlake. Add AMX-BF16, AMX-TILE, AMX-INT8 and UINTR for sapphirerapids. Add KEYLOCKER for tigerlake. 2020-11-07 Richard Biener Backported from master: 2020-10-21 Richard Biener Andrew MacLeod Martin Liska PR target/97360 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Remove call to build_distinct_type_copy(). 2020-11-04 Andrea Corallo * config/aarch64/arm_neon.h (__ST2_LANE_FUNC, __ST3_LANE_FUNC) (__ST4_LANE_FUNC): Rename the macro generating the 'q' variants into __ST2Q_LANE_FUNC, __ST2Q_LANE_FUNC, __ST2Q_LANE_FUNC so they all can be undefed at the and of the file. (vst2_lane_bf16, vst2q_lane_bf16, vst3_lane_bf16, vst3q_lane_bf16) (vst4_lane_bf16, vst4q_lane_bf16): Add new intrinsics. 2020-11-04 Andrea Corallo * config/aarch64/arm_neon.h (__LD2_LANE_FUNC, __LD3_LANE_FUNC) (__LD4_LANE_FUNC): Rename the macro geneating the 'q' variants into __LD2Q_LANE_FUNC, __LD2Q_LANE_FUNC, __LD2Q_LANE_FUNC so they all can be undefed at the and of the file. (vld2_lane_bf16, vld2q_lane_bf16, vld3_lane_bf16, vld3q_lane_bf16) (vld4_lane_bf16, vld4q_lane_bf16): Add new intrinsics. 2020-11-04 Andrea Corallo * config/aarch64/arm_neon.h (vcopy_lane_bf16, vcopyq_lane_bf16) (vcopyq_laneq_bf16, vcopy_laneq_bf16): New intrinsics. 2020-11-03 Thomas Schwinge Backported from master: 2020-11-03 Thomas Schwinge * omp-low.c (scan_omp_for) : Use proper location to 'inform' of enclosing parent compute construct. 2020-11-03 Thomas Schwinge Backported from master: 2020-11-03 Thomas Schwinge * omp-low.c (scan_omp_for) : Move earlier inconsistent nested 'reduction' clauses checking. 2020-11-03 Thomas Schwinge Backported from master: 2020-11-03 Thomas Schwinge * omp-low.c (scan_omp_for) : More precise diagnostics for 'gang', 'worker', 'vector' clauses with arguments only allowed in 'kernels' regions. 2020-11-02 Jakub Jelinek * wide-int.cc (wi::set_bit_large): Call canonize unless setting msb bit and clearing bits above it. 2020-10-29 Martin Liska Backported from master: 2020-10-29 Martin Liska PR lto/97508 * langhooks.c (lhd_begin_section): Call get_section with not_existing = true. * output.h (get_section): Add new argument. * varasm.c (get_section): Fail when NOT_EXISTING is true and a section already exists. * ipa-cp.c (ipcp_write_summary): Remove. (ipcp_read_summary): Likewise. * ipa-fnsummary.c (ipa_fn_summary_read): Always read jump functions summary. (ipa_fn_summary_write): Always stream it. 2020-10-28 Richard Biener Backported from master: 2020-09-18 Richard Biener PR tree-optimization/97081 * tree-vect-patterns.c (vect_recog_rotate_pattern): Use the precision of the shifted operand to determine the mask. 2020-10-26 Martin Jambor Backported from master: 2020-10-19 Martin Jambor PR tree-optimization/97456 * tree-complex.c (set_component_ssa_name): Do not replace ignored decl default definitions with new component vars. Reorder if conditions. 2020-10-22 Andreas Krebbel Backported from master: 2020-10-22 Andreas Krebbel PR rtl-optimization/97439 * dfp.c (decimal_real_maxval): Set the sign flag in the generated number. 2020-10-22 Kito Cheng Backported from master: 2020-10-14 Kito Cheng PR target/96759 * expr.c (expand_assignment): Handle misaligned stores with PARALLEL value. 2020-10-21 liuhongt PR target/97506 * config/i386/i386-expand.c (ix86_expand_sse_movcc): Move op_true to dest directly when op_true equals op_false. 2020-10-19 Srinath Parvathaneni Backported from master: 2020-10-16 Srinath Parvathaneni PR target/97327 * config/arm/arm.c (fp_bitlist): Add isa_bit_mve_float to FP bits array. 2020-10-16 Christophe Lyon Backported from master: 2020-10-08 Christophe Lyon PR target/96914 * config/arm/arm_mve.h (__arm_vcvtnq_u32_f32): New. 2020-10-16 Christophe Lyon Backported from master: 2020-10-08 Christophe Lyon PR target/96914 * config/arm/arm_mve.h (vqrdmlashq_n_u8, vqrdmlashq_n_u16) (vqrdmlashq_n_u32, vqrdmlahq_n_u8, vqrdmlahq_n_u16) (vqrdmlahq_n_u32, vqdmlahq_n_u8, vqdmlahq_n_u16, vqdmlahq_n_u32) (vmlaldavaxq_p_u16, vmlaldavaxq_p_u32): Remove. * config/arm/arm_mve_builtins.def (vqrdmlashq_n_u, vqrdmlahq_n_u) (vqdmlahq_n_u, vmlaldavaxq_p_u): Remove. * config/arm/unspecs.md (VQDMLAHQ_N_U, VQRDMLAHQ_N_U) (VQRDMLASHQ_N_U) (VMLALDAVAXQ_P_U): Remove unspecs. * config/arm/iterators.md (VQDMLAHQ_N_U, VQRDMLAHQ_N_U) (VQRDMLASHQ_N_U, VMLALDAVAXQ_P_U): Remove attributes. (VQDMLAHQ_N, VQRDMLAHQ_N, VQRDMLASHQ_N, VMLALDAVAXQ_P): Remove unsigned variants from iterators. * config/arm/mve.md (mve_vqdmlahq_n_) (mve_vqrdmlahq_n_) (mve_vqrdmlashq_n_, mve_vmlaldavaxq_p_): Update comment. 2020-10-16 Christophe Lyon Backported from master: 2020-10-08 Christophe Lyon PR target/96914 * config/arm/arm_mve.h (vqdmlashq, vqdmlashq_m): Define. * config/arm/arm_mve_builtins.def (vqdmlashq_n_s) (vqdmlashq_m_n_s,): New. * config/arm/unspecs.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New unspecs. * config/arm/iterators.md (VQDMLASHQ_N_S, VQDMLASHQ_M_N_S): New attributes. (VQDMLASHQ_N): New iterator. * config/arm/mve.md (mve_vqdmlashq_n_, mve_vqdmlashq_m_n_s): New patterns. 2020-10-16 Jakub Jelinek Backported from master: 2020-10-13 Jakub Jelinek PR rtl-optimization/97386 * combine.c (simplify_shift_const_1): Don't optimize nested ROTATEs if they have different modes. 2020-10-16 Jakub Jelinek Backported from master: 2020-10-08 Jakub Jelinek PR sanitizer/97294 * tree-cfg.c (move_block_to_fn): Call notice_special_calls on call stmts being moved into dest_cfun. * omp-low.c (lower_rec_input_clauses): Set cfun->calls_alloca when adding __builtin_alloca_with_align call without gimplification. 2020-10-16 Srinath Parvathaneni Backported from master: 2020-10-16 Srinath Parvathaneni PR target/97291 * config/arm/arm-builtins.c (arm_strsbwbs_qualifiers): Modify array. (arm_strsbwbu_qualifiers): Likewise. (arm_strsbwbs_p_qualifiers): Likewise. (arm_strsbwbu_p_qualifiers): Likewise. * config/arm/arm_mve.h (__arm_vstrdq_scatter_base_wb_s64): Modify function definition. (__arm_vstrdq_scatter_base_wb_u64): Likewise. (__arm_vstrdq_scatter_base_wb_p_s64): Likewise. (__arm_vstrdq_scatter_base_wb_p_u64): Likewise. (__arm_vstrwq_scatter_base_wb_p_s32): Likewise. (__arm_vstrwq_scatter_base_wb_p_u32): Likewise. (__arm_vstrwq_scatter_base_wb_s32): Likewise. (__arm_vstrwq_scatter_base_wb_u32): Likewise. (__arm_vstrwq_scatter_base_wb_f32): Likewise. (__arm_vstrwq_scatter_base_wb_p_f32): Likewise. * config/arm/arm_mve_builtins.def (vstrwq_scatter_base_wb_add_u): Remove expansion for the builtin. (vstrwq_scatter_base_wb_add_s): Likewise. (vstrwq_scatter_base_wb_add_f): Likewise. (vstrdq_scatter_base_wb_add_u): Likewise. (vstrdq_scatter_base_wb_add_s): Likewise. (vstrwq_scatter_base_wb_p_add_u): Likewise. (vstrwq_scatter_base_wb_p_add_s): Likewise. (vstrwq_scatter_base_wb_p_add_f): Likewise. (vstrdq_scatter_base_wb_p_add_u): Likewise. (vstrdq_scatter_base_wb_p_add_s): Likewise. * config/arm/mve.md (mve_vstrwq_scatter_base_wb_v4si): Remove expand. (mve_vstrwq_scatter_base_wb_add_v4si): Likewise. (mve_vstrwq_scatter_base_wb_v4si_insn): Rename pattern to ... (mve_vstrwq_scatter_base_wb_v4si): This. (mve_vstrwq_scatter_base_wb_p_v4si): Remove expand. (mve_vstrwq_scatter_base_wb_p_add_v4si): Likewise. (mve_vstrwq_scatter_base_wb_p_v4si_insn): Rename pattern to ... (mve_vstrwq_scatter_base_wb_p_v4si): This. (mve_vstrwq_scatter_base_wb_fv4sf): Remove expand. (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_fv4sf_insn): Rename pattern to ... (mve_vstrwq_scatter_base_wb_fv4sf): This. (mve_vstrwq_scatter_base_wb_p_fv4sf): Remove expand. (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Rename pattern to ... (mve_vstrwq_scatter_base_wb_p_fv4sf): This. (mve_vstrdq_scatter_base_wb_v2di): Remove expand. (mve_vstrdq_scatter_base_wb_add_v2di): Likewise. (mve_vstrdq_scatter_base_wb_v2di_insn): Rename pattern to ... (mve_vstrdq_scatter_base_wb_v2di): This. (mve_vstrdq_scatter_base_wb_p_v2di): Remove expand. (mve_vstrdq_scatter_base_wb_p_add_v2di): Likewise. (mve_vstrdq_scatter_base_wb_p_v2di_insn): Rename pattern to ... (mve_vstrdq_scatter_base_wb_p_v2di): This. 2020-10-16 Joe Ramsay Backported from master: 2020-10-06 Joe Ramsay * config/arm/arm-cpus.in: (ALL_FPU_INTERNAL): Remove vfp_base. (VFPv2): Remove vfp_base. (MVE): Remove vfp_base. (vfp_base): Redefine as implied bit dependent on MVE or FP (cortex-m55): Add flags to disable MVE, MVE FP, FP and DSP extensions. * config/arm/arm.c (arm_configure_build_target): Add implied bits to ISA. * config/arm/parsecpu.awk: (gen_isa): Print implied bits and their dependencies to ISA header. (gen_data): Add parsing for implied feature bits. 2020-10-16 Martin Jambor Backported from master: 2020-10-07 Martin Jambor PR ipa/96394 * ipa-prop.c (update_indirect_edges_after_inlining): Do not add resolved speculation edges to vector of new direct edges even in presence of multiple speculative direct edges for a single call. 2020-10-16 Martin Liska Backported from master: 2020-10-16 Martin Liska PR ipa/97404 * ipa-prop.c (struct ipa_vr_ggc_hash_traits): Compare types of VRP as we can merge ranges of different types. 2020-10-15 Martin Liska Backported from master: 2020-10-15 Martin Liska PR ipa/97295 * profile-count.c (profile_count::to_frequency): Move part of gcc_assert to STATIC_ASSERT. * regs.h (REG_FREQ_FROM_BB): Do not use count.to_frequency for a function that does not have count_max initialized. 2020-10-13 Kyrylo Tkachov * config/aarch64/aarch64.c (neoversen2_tunings): Define. * config/aarch64/aarch64-cores.def (neoverse-n2): Use it. 2020-10-13 Alex Coplan Backported from master: 2020-09-30 Alex Coplan PR target/97251 * config/arm/arm.md (movsf): Relax TARGET_HARD_FLOAT to TARGET_VFP_BASE. (movdf): Likewise. * config/arm/vfp.md (no_literal_pool_df_immediate): Likewise. (no_literal_pool_sf_immediate): Likewise. 2020-10-13 Richard Sandiford Backported from master: 2020-09-25 Richard Sandiford * config/arm/arm-protos.h (arm_mve_mode_and_operands_type_check): Delete. * config/arm/arm.c (arm_coproc_mem_operand_wb): Use a scale factor of 2 rather than 4 for 16-bit modes. (arm_mve_mode_and_operands_type_check): Delete. * config/arm/constraints.md (Uj): Allow writeback for Neon, but continue to disallow it for MVE. * config/arm/arm.md (*arm32_mov): Add !TARGET_HAVE_MVE. * config/arm/vfp.md (*mov_load_vfp_hf16, *mov_store_vfp_hf16): Fold back into... (*mov_vfp_16): ...here but use Uj for the FPR memory constraints. Use for base MVE too. 2020-10-12 Kyrylo Tkachov Backported from master: 2020-10-12 Kyrylo Tkachov PR target/97349 * config/aarch64/arm_neon.h (vdupq_n_p8, vdupq_n_p16, vdupq_n_p64, vdupq_n_s8, vdupq_n_s16, vdupq_n_u8, vdupq_n_u16): Fix argument type. 2020-10-12 Richard Biener PR tree-optimization/97357 * tree-ssa-loop-split.c (ssa_semi_invariant_p): Abnormal SSA names are not semi invariant. 2020-10-12 Richard Biener PR tree-optimization/97255 * tree-vect-patterns.c (vect_recog_bool_pattern): Also handle VIEW_CONVERT_EXPR. 2020-10-09 Vladimir Makarov PR rtl-optimization/97313 * lra-constraints.c (match_reload): Don't keep strict_low_part in reloads for non-registers. 2020-10-08 Martin Sebor PR middle-end/95189 PR middle-end/95886 * builtins.c (inline_expand_builtin_string_cmp): Rename... (inline_expand_builtin_bytecmp): ...to this. (builtin_memcpy_read_str): Don't expect data to be nul-terminated. (expand_builtin_memory_copy_args): Handle object representations with embedded nul bytes. (expand_builtin_memcmp): Same. (expand_builtin_strcmp): Adjust call to naming change. (expand_builtin_strncmp): Same. * expr.c (string_constant): Create empty strings with nonzero size. * fold-const.c (c_getstr): Rename locals and update comments. * tree.c (build_string): Accept null pointer argument. (build_string_literal): Same. * tree.h (build_string): Provide a default. (build_string_literal): Same. 2020-10-08 Kyrylo Tkachov Backported from master: 2020-09-30 Kyrylo Tkachov PR target/97150 * config/aarch64/arm_neon.h (vqrshlb_u8): Make second argument signed. (vqrshlh_u16): Likewise. (vqrshls_u32): Likewise. (vqrshld_u64): Likewise. (vqshlb_u8): Likewise. (vqshlh_u16): Likewise. (vqshls_u32): Likewise. (vqshld_u64): Likewise. (vshld_u64): Likewise. 2020-10-08 Kyrylo Tkachov Backported from master: 2020-09-30 Kyrylo Tkachov PR target/96313 * config/aarch64/aarch64-simd-builtins.def (sqmovun): Use UNOPUS qualifiers. * config/aarch64/arm_neon.h (vqmovun_s16): Adjust builtin call. Remove unnecessary result cast. (vqmovun_s32): Likewise. (vqmovun_s64): Likewise. (vqmovunh_s16): Likewise. Fix return type. (vqmovuns_s32): Likewise. (vqmovund_s64): Likewise. 2020-10-08 Alan Modra Backported from master: 2020-10-01 Alan Modra * config/rs6000/rs6000.c (rs6000_legitimize_address): Use gen_int_mode for high part of address constant. 2020-10-06 Srinath Parvathaneni Backported from master: 2020-10-06 Srinath Parvathaneni * config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to iterators.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise. (MVE_3): Likewise. (MVE_2): Likewise. (MVE_5): Likewise. (MVE_6): Likewise. (MVE_CNVT): Move mode attribute iterator from mve.md to iterators.md. (MVE_LANES): Likewise. (MVE_constraint): Likewise. (MVE_constraint1): Likewise. (MVE_constraint2): Likewise. (MVE_constraint3): Likewise. (MVE_pred): Likewise. (MVE_pred1): Likewise. (MVE_pred2): Likewise. (MVE_pred3): Likewise. (MVE_B_ELEM): Likewise. (MVE_H_ELEM): Likewise. (V_sz_elem1): Likewise. (V_extr_elem): Likewise. (earlyclobber_32): Likewise. (supf): Move int attribute from mve.md to iterators.md. (mode1): Likewise. (VCVTQ_TO_F): Move int iterator from mve.md to iterators.md. (VMVNQ_N): Likewise. (VREV64Q): Likewise. (VCVTQ_FROM_F): Likewise. (VREV16Q): Likewise. (VCVTAQ): Likewise. (VMVNQ): Likewise. (VDUPQ_N): Likewise. (VCLZQ): Likewise. (VADDVQ): Likewise. (VREV32Q): Likewise. (VMOVLBQ): Likewise. (VMOVLTQ): Likewise. (VCVTPQ): Likewise. (VCVTNQ): Likewise. (VCVTMQ): Likewise. (VADDLVQ): Likewise. (VCTPQ): Likewise. (VCTPQ_M): Likewise. (VCVTQ_N_TO_F): Likewise. (VCREATEQ): Likewise. (VSHRQ_N): Likewise. (VCVTQ_N_FROM_F): Likewise. (VADDLVQ_P): Likewise. (VCMPNEQ): Likewise. (VSHLQ): Likewise. (VABDQ): Likewise. (VADDQ_N): Likewise. (VADDVAQ): Likewise. (VADDVQ_P): Likewise. (VANDQ): Likewise. (VBICQ): Likewise. (VBRSRQ_N): Likewise. (VCADDQ_ROT270): Likewise. (VCADDQ_ROT90): Likewise. (VCMPEQQ): Likewise. (VCMPEQQ_N): Likewise. (VCMPNEQ_N): Likewise. (VEORQ): Likewise. (VHADDQ): Likewise. (VHADDQ_N): Likewise. (VHSUBQ): Likewise. (VHSUBQ_N): Likewise. (VMAXQ): Likewise. (VMAXVQ): Likewise. (VMINQ): Likewise. (VMINVQ): Likewise. (VMLADAVQ): Likewise. (VMULHQ): Likewise. (VMULLBQ_INT): Likewise. (VMULLTQ_INT): Likewise. (VMULQ): Likewise. (VMULQ_N): Likewise. (VORNQ): Likewise. (VORRQ): Likewise. (VQADDQ): Likewise. (VQADDQ_N): Likewise. (VQRSHLQ): Likewise. (VQRSHLQ_N): Likewise. (VQSHLQ): Likewise. (VQSHLQ_N): Likewise. (VQSHLQ_R): Likewise. (VQSUBQ): Likewise. (VQSUBQ_N): Likewise. (VRHADDQ): Likewise. (VRMULHQ): Likewise. (VRSHLQ): Likewise. (VRSHLQ_N): Likewise. (VRSHRQ_N): Likewise. (VSHLQ_N): Likewise. (VSHLQ_R): Likewise. (VSUBQ): Likewise. (VSUBQ_N): Likewise. (VADDLVAQ): Likewise. (VBICQ_N): Likewise. (VMLALDAVQ): Likewise. (VMLALDAVXQ): Likewise. (VMOVNBQ): Likewise. (VMOVNTQ): Likewise. (VORRQ_N): Likewise. (VQMOVNBQ): Likewise. (VQMOVNTQ): Likewise. (VSHLLBQ_N): Likewise. (VSHLLTQ_N): Likewise. (VRMLALDAVHQ): Likewise. (VBICQ_M_N): Likewise. (VCVTAQ_M): Likewise. (VCVTQ_M_TO_F): Likewise. (VQRSHRNBQ_N): Likewise. (VABAVQ): Likewise. (VSHLCQ): Likewise. (VRMLALDAVHAQ): Likewise. (VADDVAQ_P): Likewise. (VCLZQ_M): Likewise. (VCMPEQQ_M_N): Likewise. (VCMPEQQ_M): Likewise. (VCMPNEQ_M_N): Likewise. (VCMPNEQ_M): Likewise. (VDUPQ_M_N): Likewise. (VMAXVQ_P): Likewise. (VMINVQ_P): Likewise. (VMLADAVAQ): Likewise. (VMLADAVQ_P): Likewise. (VMLAQ_N): Likewise. (VMLASQ_N): Likewise. (VMVNQ_M): Likewise. (VPSELQ): Likewise. (VQDMLAHQ_N): Likewise. (VQRDMLAHQ_N): Likewise. (VQRDMLASHQ_N): Likewise. (VQRSHLQ_M_N): Likewise. (VQSHLQ_M_R): Likewise. (VREV64Q_M): Likewise. (VRSHLQ_M_N): Likewise. (VSHLQ_M_R): Likewise. (VSLIQ_N): Likewise. (VSRIQ_N): Likewise. (VMLALDAVQ_P): Likewise. (VQMOVNBQ_M): Likewise. (VMOVLTQ_M): Likewise. (VMOVNBQ_M): Likewise. (VRSHRNTQ_N): Likewise. (VORRQ_M_N): Likewise. (VREV32Q_M): Likewise. (VREV16Q_M): Likewise. (VQRSHRNTQ_N): Likewise. (VMOVNTQ_M): Likewise. (VMOVLBQ_M): Likewise. (VMLALDAVAQ): Likewise. (VQSHRNBQ_N): Likewise. (VSHRNBQ_N): Likewise. (VRSHRNBQ_N): Likewise. (VMLALDAVXQ_P): Likewise. (VQMOVNTQ_M): Likewise. (VMVNQ_M_N): Likewise. (VQSHRNTQ_N): Likewise. (VMLALDAVAXQ): Likewise. (VSHRNTQ_N): Likewise. (VCVTMQ_M): Likewise. (VCVTNQ_M): Likewise. (VCVTPQ_M): Likewise. (VCVTQ_M_N_FROM_F): Likewise. (VCVTQ_M_FROM_F): Likewise. (VRMLALDAVHQ_P): Likewise. (VADDLVAQ_P): Likewise. (VABAVQ_P): Likewise. (VSHLQ_M): Likewise. (VSRIQ_M_N): Likewise. (VSUBQ_M): Likewise. (VCVTQ_M_N_TO_F): Likewise. (VHSUBQ_M): Likewise. (VSLIQ_M_N): Likewise. (VRSHLQ_M): Likewise. (VMINQ_M): Likewise. (VMULLBQ_INT_M): Likewise. (VMULHQ_M): Likewise. (VMULQ_M): Likewise. (VHSUBQ_M_N): Likewise. (VHADDQ_M_N): Likewise. (VORRQ_M): Likewise. (VRMULHQ_M): Likewise. (VQADDQ_M): Likewise. (VRSHRQ_M_N): Likewise. (VQSUBQ_M_N): Likewise. (VADDQ_M): Likewise. (VORNQ_M): Likewise. (VRHADDQ_M): Likewise. (VQSHLQ_M): Likewise. (VANDQ_M): Likewise. (VBICQ_M): Likewise. (VSHLQ_M_N): Likewise. (VCADDQ_ROT270_M): Likewise. (VQRSHLQ_M): Likewise. (VQADDQ_M_N): Likewise. (VADDQ_M_N): Likewise. (VMAXQ_M): Likewise. (VQSUBQ_M): Likewise. (VMLASQ_M_N): Likewise. (VMLADAVAQ_P): Likewise. (VBRSRQ_M_N): Likewise. (VMULQ_M_N): Likewise. (VCADDQ_ROT90_M): Likewise. (VMULLTQ_INT_M): Likewise. (VEORQ_M): Likewise. (VSHRQ_M_N): Likewise. (VSUBQ_M_N): Likewise. (VHADDQ_M): Likewise. (VABDQ_M): Likewise. (VMLAQ_M_N): Likewise. (VQSHLQ_M_N): Likewise. (VMLALDAVAQ_P): Likewise. (VMLALDAVAXQ_P): Likewise. (VQRSHRNBQ_M_N): Likewise. (VQRSHRNTQ_M_N): Likewise. (VQSHRNBQ_M_N): Likewise. (VQSHRNTQ_M_N): Likewise. (VRSHRNBQ_M_N): Likewise. (VRSHRNTQ_M_N): Likewise. (VSHLLBQ_M_N): Likewise. (VSHLLTQ_M_N): Likewise. (VSHRNBQ_M_N): Likewise. (VSHRNTQ_M_N): Likewise. (VSTRWSBQ): Likewise. (VSTRBSOQ): Likewise. (VSTRBQ): Likewise. (VLDRBGOQ): Likewise. (VLDRBQ): Likewise. (VLDRWGBQ): Likewise. (VLD1Q): Likewise. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (VLDRDGBQ): Likewise. (VLDRDGOQ): Likewise. (VLDRDGSOQ): Likewise. (VLDRWGOQ): Likewise. (VLDRWGSOQ): Likewise. (VST1Q): Likewise. (VSTRHSOQ): Likewise. (VSTRHSSOQ): Likewise. (VSTRHQ): Likewise. (VSTRWQ): Likewise. (VSTRDSBQ): Likewise. (VSTRDSOQ): Likewise. (VSTRDSSOQ): Likewise. (VSTRWSOQ): Likewise. (VSTRWSSOQ): Likewise. (VSTRWSBWBQ): Likewise. (VLDRWGBWBQ): Likewise. (VSTRDSBWBQ): Likewise. (VLDRDGBWBQ): Likewise. (VADCIQ): Likewise. (VADCIQ_M): Likewise. (VSBCQ): Likewise. (VSBCQ_M): Likewise. (VSBCIQ): Likewise. (VSBCIQ_M): Likewise. (VADCQ): Likewise. (VADCQ_M): Likewise. (UQRSHLLQ): Likewise. (SQRSHRLQ): Likewise. (VSHLCQ_M): Likewise. * config/arm/mve.md (MVE_types): Move mode iterator to iterators.md from mve.md. (MVE_VLD_ST): Likewise. (MVE_0): Likewise. (MVE_1): Likewise. (MVE_3): Likewise. (MVE_2): Likewise. (MVE_5): Likewise. (MVE_6): Likewise. (MVE_CNVT): Move mode attribute iterator to iterators.md from mve.md. (MVE_LANES): Likewise. (MVE_constraint): Likewise. (MVE_constraint1): Likewise. (MVE_constraint2): Likewise. (MVE_constraint3): Likewise. (MVE_pred): Likewise. (MVE_pred1): Likewise. (MVE_pred2): Likewise. (MVE_pred3): Likewise. (MVE_B_ELEM): Likewise. (MVE_H_ELEM): Likewise. (V_sz_elem1): Likewise. (V_extr_elem): Likewise. (earlyclobber_32): Likewise. (supf): Move int attribute to iterators.md from mve.md. (mode1): Likewise. (VCVTQ_TO_F): Move int iterator to iterators.md from mve.md. (VMVNQ_N): Likewise. (VREV64Q): Likewise. (VCVTQ_FROM_F): Likewise. (VREV16Q): Likewise. (VCVTAQ): Likewise. (VMVNQ): Likewise. (VDUPQ_N): Likewise. (VCLZQ): Likewise. (VADDVQ): Likewise. (VREV32Q): Likewise. (VMOVLBQ): Likewise. (VMOVLTQ): Likewise. (VCVTPQ): Likewise. (VCVTNQ): Likewise. (VCVTMQ): Likewise. (VADDLVQ): Likewise. (VCTPQ): Likewise. (VCTPQ_M): Likewise. (VCVTQ_N_TO_F): Likewise. (VCREATEQ): Likewise. (VSHRQ_N): Likewise. (VCVTQ_N_FROM_F): Likewise. (VADDLVQ_P): Likewise. (VCMPNEQ): Likewise. (VSHLQ): Likewise. (VABDQ): Likewise. (VADDQ_N): Likewise. (VADDVAQ): Likewise. (VADDVQ_P): Likewise. (VANDQ): Likewise. (VBICQ): Likewise. (VBRSRQ_N): Likewise. (VCADDQ_ROT270): Likewise. (VCADDQ_ROT90): Likewise. (VCMPEQQ): Likewise. (VCMPEQQ_N): Likewise. (VCMPNEQ_N): Likewise. (VEORQ): Likewise. (VHADDQ): Likewise. (VHADDQ_N): Likewise. (VHSUBQ): Likewise. (VHSUBQ_N): Likewise. (VMAXQ): Likewise. (VMAXVQ): Likewise. (VMINQ): Likewise. (VMINVQ): Likewise. (VMLADAVQ): Likewise. (VMULHQ): Likewise. (VMULLBQ_INT): Likewise. (VMULLTQ_INT): Likewise. (VMULQ): Likewise. (VMULQ_N): Likewise. (VORNQ): Likewise. (VORRQ): Likewise. (VQADDQ): Likewise. (VQADDQ_N): Likewise. (VQRSHLQ): Likewise. (VQRSHLQ_N): Likewise. (VQSHLQ): Likewise. (VQSHLQ_N): Likewise. (VQSHLQ_R): Likewise. (VQSUBQ): Likewise. (VQSUBQ_N): Likewise. (VRHADDQ): Likewise. (VRMULHQ): Likewise. (VRSHLQ): Likewise. (VRSHLQ_N): Likewise. (VRSHRQ_N): Likewise. (VSHLQ_N): Likewise. (VSHLQ_R): Likewise. (VSUBQ): Likewise. (VSUBQ_N): Likewise. (VADDLVAQ): Likewise. (VBICQ_N): Likewise. (VMLALDAVQ): Likewise. (VMLALDAVXQ): Likewise. (VMOVNBQ): Likewise. (VMOVNTQ): Likewise. (VORRQ_N): Likewise. (VQMOVNBQ): Likewise. (VQMOVNTQ): Likewise. (VSHLLBQ_N): Likewise. (VSHLLTQ_N): Likewise. (VRMLALDAVHQ): Likewise. (VBICQ_M_N): Likewise. (VCVTAQ_M): Likewise. (VCVTQ_M_TO_F): Likewise. (VQRSHRNBQ_N): Likewise. (VABAVQ): Likewise. (VSHLCQ): Likewise. (VRMLALDAVHAQ): Likewise. (VADDVAQ_P): Likewise. (VCLZQ_M): Likewise. (VCMPEQQ_M_N): Likewise. (VCMPEQQ_M): Likewise. (VCMPNEQ_M_N): Likewise. (VCMPNEQ_M): Likewise. (VDUPQ_M_N): Likewise. (VMAXVQ_P): Likewise. (VMINVQ_P): Likewise. (VMLADAVAQ): Likewise. (VMLADAVQ_P): Likewise. (VMLAQ_N): Likewise. (VMLASQ_N): Likewise. (VMVNQ_M): Likewise. (VPSELQ): Likewise. (VQDMLAHQ_N): Likewise. (VQRDMLAHQ_N): Likewise. (VQRDMLASHQ_N): Likewise. (VQRSHLQ_M_N): Likewise. (VQSHLQ_M_R): Likewise. (VREV64Q_M): Likewise. (VRSHLQ_M_N): Likewise. (VSHLQ_M_R): Likewise. (VSLIQ_N): Likewise. (VSRIQ_N): Likewise. (VMLALDAVQ_P): Likewise. (VQMOVNBQ_M): Likewise. (VMOVLTQ_M): Likewise. (VMOVNBQ_M): Likewise. (VRSHRNTQ_N): Likewise. (VORRQ_M_N): Likewise. (VREV32Q_M): Likewise. (VREV16Q_M): Likewise. (VQRSHRNTQ_N): Likewise. (VMOVNTQ_M): Likewise. (VMOVLBQ_M): Likewise. (VMLALDAVAQ): Likewise. (VQSHRNBQ_N): Likewise. (VSHRNBQ_N): Likewise. (VRSHRNBQ_N): Likewise. (VMLALDAVXQ_P): Likewise. (VQMOVNTQ_M): Likewise. (VMVNQ_M_N): Likewise. (VQSHRNTQ_N): Likewise. (VMLALDAVAXQ): Likewise. (VSHRNTQ_N): Likewise. (VCVTMQ_M): Likewise. (VCVTNQ_M): Likewise. (VCVTPQ_M): Likewise. (VCVTQ_M_N_FROM_F): Likewise. (VCVTQ_M_FROM_F): Likewise. (VRMLALDAVHQ_P): Likewise. (VADDLVAQ_P): Likewise. (VABAVQ_P): Likewise. (VSHLQ_M): Likewise. (VSRIQ_M_N): Likewise. (VSUBQ_M): Likewise. (VCVTQ_M_N_TO_F): Likewise. (VHSUBQ_M): Likewise. (VSLIQ_M_N): Likewise. (VRSHLQ_M): Likewise. (VMINQ_M): Likewise. (VMULLBQ_INT_M): Likewise. (VMULHQ_M): Likewise. (VMULQ_M): Likewise. (VHSUBQ_M_N): Likewise. (VHADDQ_M_N): Likewise. (VORRQ_M): Likewise. (VRMULHQ_M): Likewise. (VQADDQ_M): Likewise. (VRSHRQ_M_N): Likewise. (VQSUBQ_M_N): Likewise. (VADDQ_M): Likewise. (VORNQ_M): Likewise. (VRHADDQ_M): Likewise. (VQSHLQ_M): Likewise. (VANDQ_M): Likewise. (VBICQ_M): Likewise. (VSHLQ_M_N): Likewise. (VCADDQ_ROT270_M): Likewise. (VQRSHLQ_M): Likewise. (VQADDQ_M_N): Likewise. (VADDQ_M_N): Likewise. (VMAXQ_M): Likewise. (VQSUBQ_M): Likewise. (VMLASQ_M_N): Likewise. (VMLADAVAQ_P): Likewise. (VBRSRQ_M_N): Likewise. (VMULQ_M_N): Likewise. (VCADDQ_ROT90_M): Likewise. (VMULLTQ_INT_M): Likewise. (VEORQ_M): Likewise. (VSHRQ_M_N): Likewise. (VSUBQ_M_N): Likewise. (VHADDQ_M): Likewise. (VABDQ_M): Likewise. (VMLAQ_M_N): Likewise. (VQSHLQ_M_N): Likewise. (VMLALDAVAQ_P): Likewise. (VMLALDAVAXQ_P): Likewise. (VQRSHRNBQ_M_N): Likewise. (VQRSHRNTQ_M_N): Likewise. (VQSHRNBQ_M_N): Likewise. (VQSHRNTQ_M_N): Likewise. (VRSHRNBQ_M_N): Likewise. (VRSHRNTQ_M_N): Likewise. (VSHLLBQ_M_N): Likewise. (VSHLLTQ_M_N): Likewise. (VSHRNBQ_M_N): Likewise. (VSHRNTQ_M_N): Likewise. (VSTRWSBQ): Likewise. (VSTRBSOQ): Likewise. (VSTRBQ): Likewise. (VLDRBGOQ): Likewise. (VLDRBQ): Likewise. (VLDRWGBQ): Likewise. (VLD1Q): Likewise. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (VLDRDGBQ): Likewise. (VLDRDGOQ): Likewise. (VLDRDGSOQ): Likewise. (VLDRWGOQ): Likewise. (VLDRWGSOQ): Likewise. (VST1Q): Likewise. (VSTRHSOQ): Likewise. (VSTRHSSOQ): Likewise. (VSTRHQ): Likewise. (VSTRWQ): Likewise. (VSTRDSBQ): Likewise. (VSTRDSOQ): Likewise. (VSTRDSSOQ): Likewise. (VSTRWSOQ): Likewise. (VSTRWSSOQ): Likewise. (VSTRWSBWBQ): Likewise. (VLDRWGBWBQ): Likewise. (VSTRDSBWBQ): Likewise. (VLDRDGBWBQ): Likewise. (VADCIQ): Likewise. (VADCIQ_M): Likewise. (VSBCQ): Likewise. (VSBCQ_M): Likewise. (VSBCIQ): Likewise. (VSBCIQ_M): Likewise. (VADCQ): Likewise. (VADCQ_M): Likewise. (UQRSHLLQ): Likewise. (SQRSHRLQ): Likewise. (VSHLCQ_M): Likewise. (define_c_enum "unspec"): Move MVE enumerator to unspecs.md from mve.md. * config/arm/unspecs.md (define_c_enum "unspec"): Move MVE enumerator from mve.md to unspecs.md. 2020-10-06 Joe Ramsay Backported from master: 2020-10-02 Joe Ramsay * config/arm/arm_mve.h (__arm_vmaxnmavq): Remove coercion of scalar argument. (__arm_vmaxnmvq): Likewise. (__arm_vminnmavq): Likewise. (__arm_vminnmvq): Likewise. (__arm_vmaxnmavq_p): Likewise. (__arm_vmaxnmvq_p): Likewise (and delete duplicate definition). (__arm_vminnmavq_p): Likewise. (__arm_vminnmvq_p): Likewise. (__arm_vmaxavq): Likewise. (__arm_vmaxavq_p): Likewise. (__arm_vmaxvq): Likewise. (__arm_vmaxvq_p): Likewise. (__arm_vminavq): Likewise. (__arm_vminavq_p): Likewise. (__arm_vminvq): Likewise. (__arm_vminvq_p): Likewise. 2020-10-06 Richard Biener PR tree-optimization/97236 * tree-vect-stmts.c (get_group_load_store_type): Keep VMAT_ELEMENTWISE for single-element vectors. 2020-10-06 Andreas Krebbel Backported from master: 2020-10-06 Andreas Krebbel * doc/invoke.texi: Add z15/arch13 to the list of documented -march/-mtune options. 2020-10-06 Andreas Krebbel Backported from master: 2020-08-12 Andreas Krebbel PR target/96456 * config/s390/s390.h (TARGET_NONSIGNALING_VECTOR_COMPARE_OK): New macro. * config/s390/vector.md (vcond_comparison_operator): Use new macro for the check. 2020-10-05 Alex Coplan * config/arm/arm-cpus.in (neoverse-v1): Add missing vendor and part numbers. 2020-10-02 Alex Coplan * config/arm/arm-cpus.in (neoverse-n2): New. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * doc/invoke.texi: Document support for Neoverse N2. 2020-10-02 Kyrylo Tkachov Backported from master: 2020-10-02 Kyrylo Tkachov * config/aarch64/aarch64.c (neoversev1_tunings): Define. * config/aarch64/aarch64-cores.def (zeus): Use it. (neoverse-v1): Likewise. 2020-10-02 Martin Liska Backported from master: 2020-10-02 Martin Liska PR gcov-profile/97193 * coverage.c (coverage_init): GCDA note files should not be mangled and should end in output directory. 2020-10-01 Martin Liska Backported from master: 2020-09-25 Martin Liska PR gcov-profile/64636 * value-prof.c (stream_out_histogram_value): Allow negative values for HIST_TYPE_IOR. 2020-10-01 Martin Liska Backported from master: 2020-09-29 Martin Liska PR tree-optimization/96979 * tree-switch-conversion.c (jump_table_cluster::can_be_handled): Make a fast bail out. (bit_test_cluster::can_be_handled): Likewise here. * tree-switch-conversion.h (get_range): Use wi::to_wide instead of a folding. 2020-10-01 Martin Liska Backported from master: 2020-09-23 Martin Liska PR gcov-profile/97069 * profile.c (branch_prob): Line number must be at least 1. 2020-10-01 Michael Davidsaver * config/i386/t-rtems: Change from mtune to march when building multilibs. The mtune argument tunes or optimizes for a specific CPU model but does not ensure the generated code is appropriate for the CPU model. Prior to this patch, i386 compatible code was always generated but tuned for later models. 2020-10-01 Srinath Parvathaneni Backported from master: 2020-09-30 Srinath Parvathaneni PR target/96795 * config/arm/arm_mve.h (__ARM_mve_coerce2): Define. (__arm_vaddq): Correct the scalar argument. (__arm_vaddq_m): Likewise. (__arm_vaddq_x): Likewise. (__arm_vcmpeqq_m): Likewise. (__arm_vcmpeqq): Likewise. (__arm_vcmpgeq_m): Likewise. (__arm_vcmpgeq): Likewise. (__arm_vcmpgtq_m): Likewise. (__arm_vcmpgtq): Likewise. (__arm_vcmpleq_m): Likewise. (__arm_vcmpleq): Likewise. (__arm_vcmpltq_m): Likewise. (__arm_vcmpltq): Likewise. (__arm_vcmpneq_m): Likewise. (__arm_vcmpneq): Likewise. (__arm_vfmaq_m): Likewise. (__arm_vfmaq): Likewise. (__arm_vfmasq_m): Likewise. (__arm_vfmasq): Likewise. (__arm_vmaxnmavq): Likewise. (__arm_vmaxnmavq_p): Likewise. (__arm_vmaxnmvq): Likewise. (__arm_vmaxnmvq_p): Likewise. (__arm_vminnmavq): Likewise. (__arm_vminnmavq_p): Likewise. (__arm_vminnmvq): Likewise. (__arm_vminnmvq_p): Likewise. (__arm_vmulq_m): Likewise. (__arm_vmulq): Likewise. (__arm_vmulq_x): Likewise. (__arm_vsetq_lane): Likewise. (__arm_vsubq_m): Likewise. (__arm_vsubq): Likewise. (__arm_vsubq_x): Likewise. 2020-10-01 Jakub Jelinek Backported from master: 2020-10-01 Jakub Jelinek * config/s390/s390.c (s390_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR for the first assignments to fenv_var and old_fpc. Formatting fixes. 2020-10-01 Joel Hutton Backported from master: 2020-09-30 Joel Hutton PR target/96827 * tree-vect-slp.c (vect_analyze_slp): Do not call vect_attempt_slp_rearrange_stmts for vector constructors. 2020-09-30 Jim Wilson PR bootstrap/97183 * configure.ac (gcc_cv_header_zstd_h): Check ZSTD_VERISON_NUMBER. * configure: Regenerated. 2020-09-30 Kyrylo Tkachov Backported from master: 2020-09-25 Kyrylo Tkachov * config/aarch64/aarch64-option-extensions.def (rng): Add cpuinfo string. 2020-09-30 H.J. Lu Backported from master: 2020-09-30 H.J. Lu PR target/97184 * config/i386/i386.md (UNSPECV_MOVDIRI): Renamed to ... (UNSPEC_MOVDIRI): This. (UNSPECV_MOVDIR64B): Renamed to ... (UNSPEC_MOVDIR64B): This. (movdiri): Use SET operation. (@movdir64b_): Likewise. 2020-09-29 H.J. Lu Backported from master: 2020-09-29 H.J. Lu PR target/97247 * config/i386/enqcmdintrin.h: Replace with . Replace _ENQCMDNTRIN_H_INCLUDED with _ENQCMDINTRIN_H_INCLUDED. 2020-09-29 Hongyu Wang Backported from master: 2020-09-29 Hongyu Wang PR target/97231 * config/i386/avx512vp2intersectintrin.h: Add FSF copyright notes. * config/i386/avx512vp2intersectvlintrin.h: Ditto. * config/i386/pconfigintrin.h: Ditto. * config/i386/wbnoinvdintrin.h: Ditto. 2020-09-29 Alex Coplan * config/aarch64/aarch64-cores.def: Add Neoverse N2. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi: Document AArch64 support for Neoverse N2. 2020-09-29 Richard Sandiford Backported from master: 2020-09-18 Richard Sandiford PR middle-end/97054 * ira.c (ira_setup_eliminable_regset): Skip the special elimination handling of the hard frame pointer if the hard frame pointer is fixed. 2020-09-29 Richard Sandiford Backported from master: 2020-09-24 Richard Sandiford * config/arm/arm.md (*stack_protect_combined_set_insn): For non-PIC, load the address of the canary rather than the address of the constant pool entry that points to it. (*stack_protect_combined_test_insn): Likewise. 2020-09-29 Richard Sandiford Backported from master: 2020-09-23 Richard Sandiford * config/aarch64/aarch64-protos.h (aarch64_salt_type): New enum. (aarch64_stack_protect_canary_mem): Declare. * config/aarch64/aarch64.md (UNSPEC_SALT_ADDR): New unspec. (stack_protect_set): Forward to stack_protect_combined_set. (stack_protect_combined_set): New pattern. Use aarch64_stack_protect_canary_mem. (reg_stack_protect_address_): Add a salt operand. (stack_protect_test): Forward to stack_protect_combined_test. (stack_protect_combined_test): New pattern. Use aarch64_stack_protect_canary_mem. * config/aarch64/aarch64.c (strip_salt): New function. (strip_offset_and_salt): Likewise. (tls_symbolic_operand_type): Use strip_offset_and_salt. (aarch64_stack_protect_canary_mem): New function. (aarch64_cannot_force_const_mem): Use strip_offset_and_salt. (aarch64_classify_address): Likewise. (aarch64_symbolic_address_p): Likewise. (aarch64_print_operand): Likewise. (aarch64_output_addr_const_extra): New function. (aarch64_tls_symbol_p): Use strip_salt. (aarch64_classify_symbol): Likewise. (aarch64_legitimate_pic_operand_p): Use strip_offset_and_salt. (aarch64_legitimate_constant_p): Likewise. (aarch64_mov_operand_p): Use strip_salt. (TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA): Override. 2020-09-29 Richard Sandiford Backported from master: 2020-08-25 Richard Sandiford * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Rename __ARM_FEATURE_SVE_VECTOR_OPERATIONS to __ARM_FEATURE_SVE_VECTOR_OPERATORS. 2020-09-29 Richard Sandiford Backported from master: 2020-08-25 Richard Sandiford * config/aarch64/aarch64-sve-builtins.cc (add_sve_type_attribute): Take the ACLE name of the type as a parameter and add it as fourth argument to the "SVE type" attribute. (register_builtin_types): Update call accordingly. (register_tuple_type): Likewise. Construct the name of the type earlier in order to do this. (get_arm_sve_vector_bits_attributes): New function. (handle_arm_sve_vector_bits_attribute): Report a more sensible error message if the attribute is applied to an SVE tuple type. Don't allow the attribute to be applied to an existing fixed-length SVE type. Mangle the new type as __SVE_VLS. Add a dummy TYPE_DECL to the new type. 2020-09-29 Richard Sandiford Backported from master: 2020-08-25 Richard Sandiford * config/aarch64/aarch64-sve-builtins.cc (DEF_SVE_TYPE): Add a leading "u" to each mangled name. 2020-09-29 Alex Coplan * config/arm/arm-cpus.in (neoverse-v1): New. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * doc/invoke.texi: Document AArch32 support for Neoverse V1. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-23 Kyrylo Tkachov PR target/71233 * config/aarch64/arm_neon.h (vreinterpretq_f64_p128, vreinterpretq_p128_f64): Define. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-23 Kyrylo Tkachov PR target/71233 * config/aarch64/aarch64-simd-builtins.def (frintn): Use BUILTIN_VHSDF_HSDF for modes. Remove explicit hf instantiation. * config/aarch64/arm_neon.h (vrndns_f32): Define. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-23 Kyrylo Tkachov PR target/71233 * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64, vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-23 Kyrylo Tkachov PR target/71233 * config/aarch64/arm_neon.h (vldrq_p128): Define. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-23 Kyrylo Tkachov PR target/71233 * config/aarch64/arm_neon.h (vstrq_p128): Define. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-22 Kyrylo Tkachov PR target/71233 * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32, vclsq_u8, vclsq_u16, vclsq_u32): Define. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-22 Kyrylo Tkachov PR target/71233 * config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64): Define. 2020-09-28 Kyrylo Tkachov Backported from master: 2020-09-22 Kyrylo Tkachov PR target/71233 * config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8, vaddq_p16, vaddq_p64, vaddq_p128): Define. 2020-09-27 Jakub Jelinek Backported from master: 2020-09-27 Jakub Jelinek PR middle-end/97073 * optabs.c (expand_binop, expand_absneg_bit, expand_unop, expand_copysign_bit): Check reg_overlap_mentioned_p between target and operand(s) and if it returns true, force a pseudo as target. 2020-09-25 Vladimir N. Makarov Backported from master: 2020-06-04 Vladimir Makarov PR middle-end/95464 * lra.c (lra_emit_move): Add processing STRICT_LOW_PART. * lra-constraints.c (match_reload): Use STRICT_LOW_PART in output reload if the original insn has it too. 2020-09-25 Joe Ramsay Backported from master: 2020-08-20 Joe Ramsay PR target/96683 * config/arm/mve.md (mve_vst1q_f): Require MVE memory operand for destination. (mve_vst1q_): Likewise. 2020-09-24 H.J. Lu Backported from master: 2020-09-16 H.J. Lu PR target/97032 * cfgexpand.c (asm_clobber_reg_kind): Set sp_is_clobbered_by_asm to true if the stack pointer is clobbered by asm statement. * emit-rtl.h (rtl_data): Add sp_is_clobbered_by_asm. * config/i386/i386.c (ix86_get_drap_rtx): Set need_drap to true if the stack pointer is clobbered by asm statement. 2020-09-24 Alan Modra Backported from master: 2020-09-24 Alan Modra PR target/97166 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Conditionally define __PCREL__. 2020-09-24 Andrea Corallo Backported from master: 2020-09-21 Andrea Corallo * config/aarch64/aarch64-builtins.c (aarch64_general_expand_builtin): Use expand machinery not to alter the value of an rtx returned by force_reg. 2020-09-24 Alex Coplan * config/aarch64/aarch64-cores.def: Add Neoverse V1. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi: Document support for Neoverse V1. 2020-09-22 David Faust Backported from master: 2020-09-22 David Faust * config/bpf/bpf.md: Add defines for signed div and mod operators. 2020-09-20 John David Anglin < danglin@gcc.gnu.org> * config/pa/pa-hpux11.h (LINK_GCC_C_SEQUENCE_SPEC): Delete. * config/pa/pa64-hpux.h (LINK_GCC_C_SEQUENCE_SPEC): Likewise. (ENDFILE_SPEC): Link with libgcc_stub.a and mill.a. * config/pa/pa32-linux.h (ENDFILE_SPEC): Link with libgcc.a. 2020-09-17 Marek Polacek Backported from master: 2020-09-16 Marek Polacek PR preprocessor/96935 * input.c (get_substring_ranges_for_loc): Return if start.column is less than 1. 2020-09-17 liuhongt * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX_UNSET): Remove OPTION_MASK_ISA_XSAVE_UNSET. (OPTION_MASK_ISA_XSAVE_UNSET): Add OPTION_MASK_ISA_AVX_UNSET. 2020-09-16 Jakub Jelinek Backported from master: 2020-09-16 Jakub Jelinek PR tree-optimization/97053 * gimple-ssa-store-merging.c (check_no_overlap): Add FIRST_ORDER, START, FIRST_EARLIER and LAST_EARLIER arguments. Return false if any stores between FIRST_EARLIER inclusive and LAST_EARLIER exclusive has order in between FIRST_ORDER and LAST_ORDER and overlaps the to be merged store. (imm_store_chain_info::try_coalesce_bswap): Add FIRST_EARLIER argument. Adjust check_no_overlap caller. (imm_store_chain_info::coalesce_immediate_stores): Add first_earlier and last_earlier variables, adjust them during iterations. Adjust check_no_overlap callers, call check_no_overlap even when extending overlapping stores by extra INTEGER_CST stores. 2020-09-15 Will Schmidt Backported from master: 2020-09-03 Will Schmidt * config/rs6000/rs6000-call.c (rs6000_init_builtin): Update V2DI_type_node and unsigned_V2DI_type_node definitions. 2020-09-15 Jakub Jelinek Backported from master: 2020-09-15 Jakub Jelinek PR target/97028 * config/i386/sse.md (mul3_bcs, _div3_bcst): Use instead of <>. 2020-09-15 Richard Biener Backported from master: 2020-08-25 Richard Biener PR debug/96690 * dwarf2out.c (reference_to_unused): Make FUNCTION_DECL processing more consistent with respect to symtab->global_info_ready. (tree_add_const_value_attribute): Unconditionally call rtl_for_decl_init to do all mangling early but throw away the result if early_dwarf. 2020-09-14 Sergei Trofimovich Backported from master: 2020-09-14 Sergei Trofimovich * doc/invoke.texi: fix '-fprofile-reproducibility' option spelling in manual. 2020-09-14 Jose E. Marchesi Backported from master: 2020-09-14 Jose E. Marchesi * config/bpf/bpf.md ("nop"): Re-define as `ja 0'. 2020-09-14 Richard Biener Backported from master: 2020-08-27 Richard Biener PR tree-optimization/96522 * tree-ssa-address.c (copy_ref_info): Reset flow-sensitive info of the copied points-to. Transfer bigger alignment via the access type. * tree-ssa-sccvn.c (eliminate_dom_walker::eliminate_stmt): Reset all flow-sensitive info. 2020-09-14 Richard Biener PR tree-optimization/97043 * tree-vect-slp.c (vect_analyze_slp_instance): Do not elide a load permutation if the current vectorization factor is one. 2020-09-14 Nathan Sidwell * config/i386/sse.md (mov): Fix operand indices. 2020-09-13 Roger Sayle * config/pa/pa.c (hppa_rtx_costs) [ASHIFT, ASHIFTRT, LSHIFTRT]: Provide accurate costs for DImode shifts of integer constants. 2020-09-12 Roger Sayle John David Anglin * config/pa/pa.md (shrpsi4_1, shrpsi4_2): New define_insns split out from previous shrpsi4 providing two commutitive variants using plus_xor_ior_operator as a predicate. (shrpdi4_1, shrpdi4_2, shrpdi_3, shrpdi_4): Likewise DImode versions where _1 and _2 take register shifts, and _3 and _4 for integers. (rotlsi3_internal): Name this anonymous instruction. (rotrdi3): New DImode insn copied from rotrsi3. (rotldi3): New DImode expander copied from rotlsi3. (rotldi4_internal): New DImode insn copied from rotsi3_internal. 2020-09-11 Andrew Stubbs Backported from master: 2020-09-11 Andrew Stubbs * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align TImode registers. * config/gcn/gcn.md: Assert that TImode registers do not early clobber. 2020-09-11 Richard Biener Backported from master: 2020-08-27 Richard Biener PR tree-optimization/96579 * tree-ssa-reassoc.c (linearize_expr_tree): If we expand rhs via special ops make sure to swap operands. 2020-09-11 Richard Biener Backported from master: 2020-07-30 Richard Biener PR tree-optimization/96370 * tree-ssa-reassoc.c (rewrite_expr_tree): Add operation code parameter and use it instead of picking it up from the stmt that is being rewritten. (reassociate_bb): Pass down the operation code. 2020-09-11 Richard Biener Backported from master: 2020-08-07 Richard Biener PR tree-optimization/96514 * tree-if-conv.c (if_convertible_bb_p): If the last stmt is a call that is control-altering, fail. 2020-09-11 Richard Biener Backported from master: 2020-07-31 Richard Biener PR middle-end/96369 * fold-const.c (fold_range_test): Special-case constant LHS for short-circuiting operations. 2020-09-11 Richard Biener Backported from master: 2020-07-29 Richard Biener PR tree-optimization/96349 * tree-ssa-loop-split.c (stmt_semi_invariant_p_1): When the condition runs into a loop PHI with an abnormal entry value give up. 2020-09-11 Matthias Klose Backported from master: 2020-07-27 Matthias Klose PR bootstrap/96203 * common.opt: Add -fcf-protection=check. * flag-types.h (cf_protection_level): Add CF_CHECK. * lto-wrapper.c (merge_and_complain): Issue an error for mismatching -fcf-protection values with -fcf-protection=check. Otherwise, merge -fcf-protection values. * doc/invoke.texi: Document -fcf-protection=check. 2020-09-11 Matthias Klose Backported from master: 2020-07-14 Matthias Klose PR lto/95604 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, error on different values for -fcf-protection. (append_compiler_options): Pass -fcf-protection option. (find_and_merge_options): Add decoded options as parameter, pass decoded_options to merge_and_complain. (run_gcc): Pass decoded options to find_and_merge_options. * lto-opts.c (lto_write_options): Pass -fcf-protection option. 2020-09-11 Jakub Jelinek Backported from master: 2020-09-10 Jakub Jelinek * lto-streamer-out.c (collect_block_tree_leafs): Recurse on root rather than BLOCK_SUBBLOCKS (root). 2020-09-11 Jakub Jelinek * lto-streamer.h (LTO_minor_version): Bump. 2020-09-11 Jakub Jelinek Backported from master: 2020-09-10 Jakub Jelinek PR debug/93865 * lto-streamer.h (struct output_block): Add emit_pwd member. * lto-streamer-out.c: Include toplev.h. (clear_line_info): Set emit_pwd. (lto_output_location_1): Encode the ob->current_file != xloc.file bit directly into the location number. If changing file, emit additionally a bit whether pwd is emitted and emit it before the first relative pathname since clear_line_info. (output_function, output_constructor): Don't call clear_line_info here. * lto-streamer-in.c (struct string_pair_map): New type. (struct string_pair_map_hasher): New type. (string_pair_map_hasher::hash): New method. (string_pair_map_hasher::equal): New method. (path_name_pair_hash_table, string_pair_map_allocator): New variables. (relative_path_prefix, canon_relative_path_prefix, canon_relative_file_name): New functions. (canon_file_name): Add relative_prefix argument, if non-NULL and string is a relative path, return canon_relative_file_name. (lto_location_cache::input_location_and_block): Decode file change bit from the location number. If changing file, unpack bit whether pwd is streamed and stream in pwd. Adjust canon_file_name caller. (lto_free_file_name_hash): Delete path_name_pair_hash_table and string_pair_map_allocator. 2020-09-11 Jakub Jelinek Backported from master: 2020-09-07 Jakub Jelinek PR debug/94235 * lto-streamer-out.c (output_cfg): Also stream goto_locus for edges. Use bp_pack_var_len_unsigned instead of streamer_write_uhwi to stream e->dest->index and e->flags. (output_function): Call output_cfg before output_ssa_name, rather than after streaming all bbs. * lto-streamer-in.c (input_cfg): Stream in goto_locus for edges. Use bp_unpack_var_len_unsigned instead of streamer_read_uhwi to stream in dest_index and edge_flags. 2020-09-11 Jakub Jelinek Backported from master: 2020-09-04 Jakub Jelinek * lto-streamer.h (stream_input_location_now): Remove declaration. * lto-streamer-in.c (stream_input_location_now): Remove. (input_eh_region, input_struct_function_base): Use stream_input_location instead of stream_input_location_now. 2020-09-11 Jakub Jelinek Backported from master: 2020-09-04 Jakub Jelinek * lto-streamer.h (struct output_block): Add reset_locus member. * lto-streamer-out.c (clear_line_info): Set reset_locus to true. (lto_output_location_1): If reset_locus, clear it and ensure current_{file,line,col} is different from xloc members. 2020-09-11 Jakub Jelinek Backported from master: 2020-09-03 Jakub Jelinek PR c++/96901 * tree.h (struct decl_tree_traits): New type. (decl_tree_map): New typedef. 2020-09-11 Jakub Jelinek Backported from master: 2020-09-03 Jakub Jelinek PR lto/94311 * gimple.h (gimple_location_ptr, gimple_phi_arg_location_ptr): New functions. * streamer-hooks.h (struct streamer_hooks): Add output_location_and_block callback. Fix up formatting for output_location. (stream_output_location_and_block): Define. * lto-streamer.h (class lto_location_cache): Fix comment typo. Add current_block member. (lto_location_cache::input_location_and_block): New method. (lto_location_cache::lto_location_cache): Initialize current_block. (lto_location_cache::cached_location): Add block member. (struct output_block): Add current_block member. (lto_output_location): Formatting fix. (lto_output_location_and_block): Declare. * lto-streamer.c (lto_streamer_hooks_init): Initialize streamer_hooks.output_location_and_block. * lto-streamer-in.c (lto_location_cache::cmp_loc): Also compare block members. (lto_location_cache::apply_location_cache): Handle blocks. (lto_location_cache::accept_location_cache, lto_location_cache::revert_location_cache): Fix up function comments. (lto_location_cache::input_location_and_block): New method. (lto_location_cache::input_location): Implement using input_location_and_block. (input_function): Invoke apply_location_cache after streaming in all bbs. * lto-streamer-out.c (clear_line_info): Set current_block. (lto_output_location_1): New function, moved from lto_output_location, added block handling. (lto_output_location): Implement using lto_output_location_1. (lto_output_location_and_block): New function. * gimple-streamer-in.c (input_phi): Use input_location_and_block to input and cache both location and block. (input_gimple_stmt): Likewise. * gimple-streamer-out.c (output_phi): Use stream_output_location_and_block. (output_gimple_stmt): Likewise. 2020-09-11 Jakub Jelinek Backported from master: 2020-08-26 Jakub Jelinek PR debug/96729 * dwarf2out.c (dwarf2out_next_real_insn): Adjust function comment. (dwarf2out_var_location): Look for next_note only if next_real is non-NULL, in that case look for the first non-deleted NOTE_INSN_VAR_LOCATION between loc_note and next_real, if any. 2020-09-09 Przemyslaw Wirkus PR target/96357 * config/aarch64/aarch64-sve.md (cond_sub_relaxed_const): Updated and renamed from cond_sub_any_const pattern. (cond_sub_strict_const): New pattern. 2020-09-04 Carl Love PR target/85830 * config/rs6000/altivec.h (vec_popcntb, vec_popcnth, vec_popcntw, vec_popcntd): Remove defines. 2020-09-04 Martin Jambor Backported from master: 2020-09-03 Martin Jambor PR tree-optimization/96820 * tree-sra.c (create_access): Disqualify candidates with accesses beyond the end of the original aggregate. (maybe_add_sra_candidate): Check that candidate type size fits signed uhwi for the sake of consistency. 2020-09-04 David Faust Backported from master: 2020-09-04 David Faust * config/bpf/bpf.h (ASM_SPEC): Pass -mxbpf to gas, if specified. * config/bpf/bpf.c (bpf_output_call): Support indirect calls in xBPF. 2020-09-03 Peter Bergner Backported from master: 2020-09-01 Peter Bergner PR target/96808 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Do not reuse accumulator memory reference for source and destination accesses. 2020-09-02 Jose E. Marchesi Backported from master: 2020-09-02 Jose E. Marchesi * config/bpf/bpf.c (bpf_asm_named_section): Delete. (TARGET_ASM_NAMED_SECTION): Likewise. 2020-09-02 Jose E. Marchesi Backported from master: 2020-09-02 Jose E. Marchesi * config.gcc: Use elfos.h in bpf-*-* targets. * config/bpf/bpf.h (MAX_OFILE_ALIGNMENT): Remove definition. (COMMON_ASM_OP): Likewise. (INIT_SECTION_ASM_OP): Likewise. (FINI_SECTION_ASM_OP): Likewise. (ASM_OUTPUT_SKIP): Likewise. (ASM_OUTPUT_ALIGNED_COMMON): Likewise. (ASM_OUTPUT_ALIGNED_LOCAL): Likewise. 2020-09-01 Martin Liska Backported from master: 2020-08-24 Martin Liska PR tree-optimization/96597 * tree-ssa-sccvn.c (vn_reference_lookup_call): Add missing initialization of ::punned. (vn_reference_insert): Use consistently false instead of 0. (vn_reference_insert_pieces): Likewise. 2020-09-01 Richard Biener Backported from master: 2020-08-04 Richard Biener PR tree-optimization/88240 * tree-ssa-sccvn.h (vn_reference_s::punned): New flag. * tree-ssa-sccvn.c (vn_reference_insert): Initialize punned. (vn_reference_insert_pieces): Likewise. (visit_reference_op_call): Likewise. (visit_reference_op_load): Track whether a ref was punned. * tree-ssa-pre.c (do_hoist_insertion): Refuse to perform hoist insertion on punned floating point loads. 2020-08-31 Richard Biener PR tree-optimization/96854 * tree-vect-loop.c (vectorizable_live_operation): Disallow SLP_TREE_TWO_OPERATORS nodes. 2020-08-31 liuhongt PR target/96551 * config/i386/sse.md (vec_unpacku_float_hi_v16si): For vector compare to integer mask, don't use gen_rtx_LT, use ix86_expand_mask_vec_cmp instead. (vec_unpacku_float_hi_v16si): Ditto. 2020-08-28 Uros Bizjak PR target/96744 * config/i386/i386-expand.c (split_double_mode): Also handle E_P2HImode and E_P2QImode. * config/i386/sse.md (MASK_DWI): New define_mode_iterator. (mov): New expander for P2HI,P2QI. (*mov_internal): New define_insn_and_split to split movement of P2QI/P2HI to 2 movqi/movhi patterns after reload. 2020-08-28 liuhongt * common/config/i386/i386-common.c (ix86_handle_option): Set AVX512DQ when AVX512VP2INTERSECT exists. 2020-08-27 Carl Love * config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin macro expansion. (XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1. * config/rs6000/rs6000-call.c: (VSX_BUILTIN_XVCVSPBF16, VSX_BUILTIN_XVCVBF16SPN): Replace with P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SPN respectively. 2020-08-27 Christophe Lyon Backported from master: 2020-08-24 Christophe Lyon PR target/94538 PR target/94538 * config/arm/thumb1.md: Disable set-constant splitter when TARGET_HAVE_MOVT. (thumb1_movsi_insn): Fix -mpure-code alternative. 2020-08-26 Roger Sayle PR middle-end/87256 * config/pa/pa.c (hppa_rtx_costs_shadd_p): New helper function to check for coefficients supported by shNadd and shladd,l. (hppa_rtx_costs): Rewrite to avoid using estimates based upon FACTOR and enable recursing deeper into RTL expressions. * config/pa/pa.md (shd_internal): Fix define_expand to provide gen_shd_internal. 2020-08-26 Roger Sayle * config/pa/pa.md (ashldi3): Additionally, on !TARGET_64BIT generate a two instruction shd/zdep sequence when shifting registers by suitable constants. (shd_internal): New define_expand to provide gen_shd_internal. 2020-08-25 Jakub Jelinek Backported from master: 2020-08-25 Jakub Jelinek PR tree-optimization/96722 * gimple.c (infer_nonnull_range): Formatting fix. (infer_nonnull_range_by_dereference): Return false for clobber stmts. 2020-08-25 Jakub Jelinek Backported from master: 2020-08-25 Jakub Jelinek PR tree-optimization/96758 * tree-ssa-strlen.c (handle_builtin_string_cmp): If both cstlen1 and cstlen2 are set, set cmpsiz to their minimum, otherwise use the one that is set. If bound is used and smaller than cmpsiz, set cmpsiz to bound. If both cstlen1 and cstlen2 are set, perform the optimization. 2020-08-25 Jakub Jelinek Backported from master: 2020-08-25 Jakub Jelinek PR target/95450 * fold-const.c (native_interpret_real): For MODE_COMPOSITE_P modes punt if the to be returned REAL_CST does not encode to the bitwise same representation. 2020-08-25 Jakub Jelinek Backported from master: 2020-08-12 Jakub Jelinek PR tree-optimization/96535 * toplev.c (process_options): Move flag_unroll_loops and flag_cunroll_grow_size handling from here to ... * opts.c (finish_options): ... here. For flag_cunroll_grow_size, don't check for AUTODETECT_VALUE, but instead check opts_set->x_flag_cunroll_grow_size. * common.opt (funroll-completely-grow-size): Default to 0. * config/rs6000/rs6000.c (TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Redefine. (rs6000_override_options_after_change): New function. (rs6000_option_override_internal): Call it. Move there the flag_cunroll_grow_size, unroll_only_small_loops and flag_rename_registers handling. 2020-08-25 Jakub Jelinek Backported from master: 2020-08-11 Jakub Jelinek PR c/96549 * tree.c (get_narrower): Use TREE_TYPE (ret) instead of TREE_TYPE (win) for COMPOUND_EXPRs. 2020-08-25 Jakub Jelinek Backported from master: 2020-08-08 Jakub Jelinek PR fortran/93553 * tree-nested.c (convert_nonlocal_omp_clauses): For OMP_CLAUSE_REDUCTION, OMP_CLAUSE_LASTPRIVATE and OMP_CLAUSE_LINEAR save info->new_local_var_chain around walks of the clause gimple sequences and declare_vars if needed into the sequence. 2020-08-25 Jakub Jelinek Backported from master: 2020-08-05 Jakub Jelinek PR middle-end/96459 * omp-low.c (lower_omp_taskreg): Call lower_reduction_clauses even in for host teams. 2020-08-25 Martin Jambor Backported from master: 2020-08-25 Martin Jambor PR tree-optimization/96730 * tree-sra.c (create_access): Disqualify any aggregate with negative offset access. (build_ref_for_model): Add assert that offset is non-negative. 2020-08-21 Richard Sandiford Backported from master: 2020-08-21 Richard Sandiford * doc/extend.texi: Update links to Arm docs. * doc/invoke.texi: Likewise. 2020-08-21 Tobias Burnus Backported from master: 2020-05-26 Tobias Burnus PR ipa/95320 * ipa-utils.h (odr_type_p): Also permit calls with only flag_generate_offload set. 2020-08-19 Joe Ramsay Backported from master: 2020-07-29 Joe Ramsay PR target/96682 * config/arm/arm-protos.h (arm_coproc_mem_operand_no_writeback): Declare prototype. (arm_mve_mode_and_operands_type_check): Declare prototype. * config/arm/arm.c (arm_coproc_mem_operand): Refactor to use _arm_coproc_mem_operand. (arm_coproc_mem_operand_wb): New function to cover full, limited and no writeback. (arm_coproc_mem_operand_no_writeback): New constraint for memory operand with no writeback. (arm_print_operand): Extend 'E' specifier for memory operand that does not support writeback. (arm_mve_mode_and_operands_type_check): New constraint check for MVE memory operands. * config/arm/constraints.md: Add Uj constraint for VFP vldr.16 and vstr.16. * config/arm/vfp.md (*mov_load_vfp_hf16): New pattern for vldr.16. (*mov_store_vfp_hf16): New pattern for vstr.16. (*mov_vfp_16): Remove MVE moves. 2020-08-19 Peter Bergner Backported from master: 2020-08-18 Peter Bergner * config/rs6000/rs6000-builtin.def (BU_VSX_1): Rename xvcvbf16sp to xvcvbf16spn. * config/rs6000/rs6000-call.c (builtin_function_type): Likewise. * config/rs6000/vsx.md: Likewise. * doc/extend.texi: Likewise. 2020-08-19 Peter Bergner Backported from master: 2020-08-13 Peter Bergner PR target/96506 * config/rs6000/rs6000-call.c (rs6000_promote_function_mode): Disallow MMA types as return values. (rs6000_function_arg): Disallow MMA types as function arguments. 2020-08-18 Uroš Bizjak PR target/96536 * config/i386/i386.md (restore_stack_nonlocal): Add missing compare RTX. 2020-08-18 liuhongt PR target/96562 PR target/93897 * config/i386/i386-expand.c (ix86_expand_pinsr): Don't use pinsr for TImode. (ix86_expand_pextr): Don't use pextr for TImode. 2020-08-14 Jan Hubicka Backported from master: 2020-05-29 Jan Hubicka PR lto/95362 * lto-streamer-out.c (lto_output_tree): Disable redundant streaming. 2020-08-13 Jan Hubicka * lto-streamer.h (LTO_minor_version): Bump version. 2020-08-13 Jan Hubicka Backported from master: 2020-06-06 Jan Hubicka PR lto/95548 * ipa-devirt.c (struct odr_enum_val): Turn values to wide_int. (ipa_odr_summary_write): Update streaming. (ipa_odr_read_section): Update streaming. 2020-08-13 Jan Hubicka Backported from master: 2020-06-03 Jan Hubicka * ipa-devirt.c: Include data-streamer.h, lto-streamer.h and streamer-hooks.h. (odr_enums): New static var. (struct odr_enum_val): New struct. (class odr_enum): New struct. (odr_enum_map): New hashtable. (odr_types_equivalent_p): Drop code testing TYPE_VALUES. (add_type_duplicate): Likewise. (free_odr_warning_data): Do not free TYPE_VALUES. (register_odr_enum): New function. (ipa_odr_summary_write): New function. (ipa_odr_read_section): New function. (ipa_odr_summary_read): New function. (class pass_ipa_odr): New pass. (make_pass_ipa_odr): New function. * ipa-utils.h (register_odr_enum): Declare. * lto-section-in.c: (lto_section_name): Add odr_types section. * lto-streamer.h (enum lto_section_type): Add odr_types section. * passes.def: Add odr_types pass. * lto-streamer-out.c (DFS::DFS_write_tree_body): Do not stream TYPE_VALUES. (hash_tree): Likewise. * tree-streamer-in.c (lto_input_ts_type_non_common_tree_pointers): Likewise. * tree-streamer-out.c (write_ts_type_non_common_tree_pointers): Likewise. * timevar.def (TV_IPA_ODR): New timervar. * tree-pass.h (make_pass_ipa_odr): Declare. * tree.c (free_lang_data_in_type): Regiser ODR types. 2020-08-13 Jan Hubicka Backported from master: 2020-08-13 Jan Hubicka * lto-streamer-out.c (lto_output_tree): Add streamer_debugging check. * lto-streamer.h (streamer_debugging): New constant * tree-streamer-in.c (streamer_read_tree_bitfields): Add streamer_debugging check. (streamer_get_pickled_tree): Likewise. * tree-streamer-out.c (pack_ts_base_value_fields): Likewise. 2020-08-13 Jan Hubicka Backported from master: 2020-08-13 Jan Hubicka * lto-streamer-out.c (lto_output_tree): Do not stream final ref if it is not needed. 2020-08-13 Jan Hubicka Backported from master: 2020-08-13 Jan Hubicka * tree-streamer.c (record_common_node): Fix hash value of pre-streamed nodes. 2020-08-13 Jan Hubicka Backported from master: 2020-08-13 Jan Hubicka * lto-streamer-in.c (lto_read_tree): Do not stream end markers. (lto_input_scc): Optimize streaming of entry lengths. * lto-streamer-out.c (lto_write_tree): Do not stream end markers (DFS::DFS): Optimize stremaing of entry lengths 2020-08-13 Jan Hubicka Backported from master: 2020-08-13 Jan Hubicka * lto-streamer-in.c (lto_input_scc): Add SHARED_SCC parameter. (lto_input_tree_1): Strenghten sanity check. (lto_input_tree): Update call of lto_input_scc. * lto-streamer-out.c: Include ipa-utils.h (create_output_block): Initialize local_trees if merigng is going to happen. (destroy_output_block): Destroy local_trees. (DFS): Add max_local_entry. (local_tree_p): New function. (DFS::DFS): Initialize and maintain it. (DFS::DFS_write_tree): Decide on streaming format. (lto_output_tree): Stream inline singleton SCCs * lto-streamer.h (enum LTO_tags): Add LTO_trees. (struct output_block): Add local_trees. (lto_input_scc): Update prototype. 2020-08-13 Martin Liska Backported from master: 2020-08-13 Martin Liska PR ipa/96482 * ipa-cp.c (ipcp_bits_lattice::meet_with_1): Mask m_value with m_mask. 2020-08-12 Alan Modra Backported from master: 2020-08-07 Alan Modra PR target/96493 * config/rs6000/predicates.md (current_file_function_operand): Don't accept functions that differ in r2 usage. 2020-08-12 Martin Liska Backported from master: 2020-08-12 Martin Liska PR ipa/96482 * ipa-cp.c (ipcp_bits_lattice::meet_with_1): Drop value bits for bits that are unknown. (ipcp_bits_lattice::set_to_constant): Likewise. * tree-ssa-ccp.c (get_default_value): Add sanity check that IPA CP bit info has all bits set to zero in bits that are unknown. 2020-08-12 Sergei Trofimovich Backported from master: 2020-07-28 Sergei Trofimovich PR ipa/96291 * ipa-cp.c (has_undead_caller_from_outside_scc_p): Consider unoptimized callers as undead. 2020-08-12 Jose E. Marchesi * config/bpf/bpf.md: Remove trailing whitespaces. * config/bpf/constraints.md: Likewise. * config/bpf/predicates.md: Likewise. 2020-08-12 Jose E. Marchesi * config/bpf/bpf-helpers.h (KERNEL_HELPER): Define. (KERNEL_VERSION): Remove. * config/bpf/bpf-helpers.def: Delete. * config/bpf/bpf.c (bpf_handle_fndecl_attribute): New function. (bpf_attribute_table): Define. (bpf_helper_names): Delete. (bpf_helper_code): Likewise. (enum bpf_builtins): Adjust to new helpers mechanism. (bpf_output_call): Likewise. (bpf_init_builtins): Likewise. (bpf_init_builtins): Likewise. * doc/extend.texi (BPF Function Attributes): New section. (BPF Kernel Helpers): Delete section. 2020-08-12 Jose E. Marchesi * config/bpf/bpf.c (bpf_compute_frame_layout): Include space for callee saved registers only in xBPF. (bpf_expand_prologue): Save callee saved registers only in xBPF. (bpf_expand_epilogue): Likewise for restoring. * doc/invoke.texi (eBPF Options): Document this is activated by -mxbpf. 2020-08-12 Jose E. Marchesi * config/bpf/bpf.opt (mxbpf): New option. * doc/invoke.texi (Option Summary): Add -mxbpf. (eBPF Options): Document -mxbbpf. 2020-08-10 Hongtao Liu PR target/96243 * config/i386/i386-expand.c (ix86_expand_sse_cmp): Refine for maskcmp. (ix86_expand_mask_vec_cmp): Change prototype. * config/i386/i386-protos.h (ix86_expand_mask_vec_cmp): Change prototype. * config/i386/i386.c (ix86_print_operand): Remove operand modifier 'I'. * config/i386/sse.md (*_cmp3): Deleted. (*_cmp3): Ditto. (*_ucmp3): Ditto. (*_ucmp3, avx512f_maskcmp3): Ditto. 2020-08-10 Martin Liska Backported from master: 2020-05-20 Martin Liska * lto-compress.c (lto_compression_zstd): Fill up num_compressed_il_bytes. (lto_uncompression_zstd): Likewise for num_uncompressed_il_bytes here. 2020-08-10 Peter Bergner Backported from master: 2020-08-08 Peter Bergner PR target/96530 * config/rs6000/rs6000.c (rs6000_invalid_conversion): Use canonical types for type comparisons. Refactor code to simplify it. 2020-08-08 Peter Bergner Backported from master: 2020-08-06 Peter Bergner PR target/96446 * config/rs6000/mma.md (*movpxi): Add xxsetaccz generation. Disable split for zero constant source operand. (mma_xxsetaccz): Change to define_expand. Call gen_movpxi. 2020-08-07 Tamar Christina Backported from master: 2020-08-03 Tamar Christina * config/aarch64/driver-aarch64.c (readline): Check return value fgets. 2020-08-07 Tamar Christina Backported from master: 2020-07-17 Tamar Christina * doc/sourcebuild.texi (dg-set-compiler-env-var, dg-set-target-env-var): Document. 2020-08-07 Tamar Christina Backported from master: 2020-07-17 Tamar Christina * config/arm/driver-arm.c (host_detect_local_cpu): Add GCC_CPUINFO. 2020-08-07 Tamar Christina Backported from master: 2020-07-17 Tamar Christina * config/aarch64/driver-aarch64.c (host_detect_local_cpu): Add GCC_CPUINFO. 2020-08-07 Tamar Christina Backported from master: 2020-07-17 Tamar Christina * config/aarch64/driver-aarch64.c (INCLUDE_SET): New. (parse_field): Use std::string. (split_words, readline, find_field): New. (host_detect_local_cpu): Fix truncation issues. 2020-08-07 Richard Sandiford Backported from master: 2020-08-06 Richard Sandiford PR target/96191 * config/arm/arm.md (arm_stack_protect_test_insn): Zero out operand 2 after use. * config/arm/thumb1.md (thumb1_stack_protect_test_insn): Likewise. 2020-08-07 Richard Sandiford Backported from master: 2020-08-05 Richard Sandiford PR target/96191 * config/aarch64/aarch64.md (stack_protect_test_): Set the CC register directly, instead of a GPR. Replace the original GPR destination with an extra scratch register. Zero out operand 3 after use. (stack_protect_test): Update accordingly. 2020-08-06 Richard Biener Backported from master: 2020-08-06 Richard Biener PR tree-optimization/96483 * tree-ssa-pre.c (create_component_ref_by_pieces_1): Handle POLY_INT_CST. 2020-08-04 Jakub Jelinek Backported from master: 2020-08-04 Jakub Jelinek * doc/extend.texi (symver): Add @cindex for symver function attribute. 2020-08-04 Matthew Malcomson * config/aarch64/aarch64-protos.h (aarch64_indirect_call_asm): New declaration. * config/aarch64/aarch64.c (aarch64_regno_regclass): Handle new stub registers class. (aarch64_class_max_nregs): Likewise. (aarch64_register_move_cost): Likewise. (aarch64_sls_shared_thunks): Global array to store stub labels. (aarch64_sls_emit_function_stub): New. (aarch64_create_blr_label): New. (aarch64_sls_emit_blr_function_thunks): New. (aarch64_sls_emit_shared_blr_thunks): New. (aarch64_asm_file_end): New. (aarch64_indirect_call_asm): New. (TARGET_ASM_FILE_END): Use aarch64_asm_file_end. (TARGET_ASM_FUNCTION_EPILOGUE): Use aarch64_sls_emit_blr_function_thunks. * config/aarch64/aarch64.h (STB_REGNUM_P): New. (enum reg_class): Add STUB_REGS class. (machine_function): Introduce `call_via` array for function-local stub labels. * config/aarch64/aarch64.md (*call_insn, *call_value_insn): Use aarch64_indirect_call_asm to emit code when hardening BLR instructions. * config/aarch64/constraints.md (Ucr): New constraint representing registers for indirect calls. Is GENERAL_REGS usually, and STUB_REGS when hardening BLR instruction against SLS. * config/aarch64/predicates.md (aarch64_general_reg): STUB_REGS class is also a general register. 2020-08-04 Matthew Malcomson * config/aarch64/aarch64-protos.h (aarch64_sls_barrier): New. * config/aarch64/aarch64.c (aarch64_output_casesi): Emit speculation barrier after BR instruction if needs be. (aarch64_trampoline_init): Handle ptr_mode value & adjust size of code copied. (aarch64_sls_barrier): New. (aarch64_asm_trampoline_template): Add needed barriers. * config/aarch64/aarch64.h (AARCH64_ISA_SB): New. (TARGET_SB): New. (TRAMPOLINE_SIZE): Account for barrier. * config/aarch64/aarch64.md (indirect_jump, *casesi_dispatch, simple_return, *do_return, *sibcall_insn, *sibcall_value_insn): Emit barrier if needs be, also account for possible barrier using "sls_length" attribute. (sls_length): New attribute. (length): Determine default using any non-default sls_length value. 2020-08-04 Matthew Malcomson * config/aarch64/aarch64-protos.h (aarch64_harden_sls_retbr_p): New. (aarch64_harden_sls_blr_p): New. * config/aarch64/aarch64.c (enum aarch64_sls_hardening_type): New. (aarch64_harden_sls_retbr_p): New. (aarch64_harden_sls_blr_p): New. (aarch64_validate_sls_mitigation): New. (aarch64_override_options): Parse options for SLS mitigation. * config/aarch64/aarch64.opt (-mharden-sls): New option. * doc/invoke.texi: Document new option. 2020-08-04 Andrea Corallo Backported from master: 2020-08-04 Andrea Corallo * config/aarch64/aarch64.md (aarch64_fjcvtzs): Add missing clobber. * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new target supports option. 2020-08-04 Jakub Jelinek Backported from master: 2020-08-04 Jakub Jelinek PR middle-end/96426 * tree-vect-generic.c (expand_vector_conversion): Replace .VEC_CONVERT call with GIMPLE_NOP if there is no lhs. 2020-08-04 Jakub Jelinek Backported from master: 2020-08-04 Jakub Jelinek PR debug/96354 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Add IS_DEBUG argument. Return false instead of gcc_unreachable if it is true and get_addr_base_and_unit_offset returns NULL. (fold_stmt_1) : Adjust caller. 2020-08-03 Jonathan Wakely Backported from master: 2020-08-03 Jonathan Wakely * doc/cpp.texi (Variadic Macros): Use the exact ... token in code examples. 2020-08-03 Richard Sandiford Backported from master: 2020-08-03 Richard Sandiford * doc/invoke.texi: Add missing comma after octeontx2f95mm entry. 2020-08-03 Qian Jianhua Backported from master: 2020-08-03 Qian jianhua * config/aarch64/aarch64-cores.def (a64fx): New core. * config/aarch64/aarch64-tune.md: Regenerated. * config/aarch64/aarch64.c (a64fx_prefetch_tune, a64fx_tunings): New. * doc/invoke.texi: Add a64fx to the list. 2020-07-31 Martin Liska Backported from master: 2020-07-31 Martin Liska * cgraph.h: Remove leading empty lines. * cgraphunit.c (enum cgraph_order_sort_kind): Remove ORDER_UNDEFINED. (struct cgraph_order_sort): Add constructors. (cgraph_order_sort::process): New. (cgraph_order_cmp): New. (output_in_order): Simplify and push nodes to vector. 2020-07-30 Martin Liska Backported from master: 2020-07-30 Martin Liska PR target/95435 * config/i386/x86-tune-costs.h: Use libcall for large sizes for -m32. Start using libcall from 128+ bytes. 2020-07-30 Martin Liska Backported from master: 2020-07-30 Martin Liska * config/i386/x86-tune-costs.h: Change code formatting. 2020-07-28 Martin Liska Backported from master: 2020-07-27 Martin Liska PR tree-optimization/96058 * expr.c (string_constant): Build string_constant only for a type that has same precision as char_type_node and is an integral type. 2020-07-28 Jakub Jelinek Backported from master: 2020-07-28 Jakub Jelinek PR middle-end/96335 * calls.c (maybe_warn_rdwr_sizes): Add FNDECL and FNTYPE arguments, instead of trying to rediscover them in the body. (initialize_argument_information): Adjust caller. 2020-07-27 Aaron Sawdey Backported from master: 2020-06-23 Aaron Sawdey * config.gcc: Identify power10 as a 64-bit processor and as valid for --with-cpu and --with-tune. 2020-07-27 Martin Liska Backported from master: 2020-07-27 Martin Liska PR lto/45375 * symbol-summary.h: Call vec_safe_reserve before grow is called in order to grow to a reasonable size. * vec.h (vec_safe_reserve): Add missing function for vl_ptr type. 2020-07-23 Sergei Trofimovich Backported from master: 2020-07-20 Sergei Trofimovich PR target/96190 * config/sparc/linux.h (ENDFILE_SPEC): Use GNU_USER_TARGET_ENDFILE_SPEC to get crtendS.o for !no-pie mode. * config/sparc/linux64.h (ENDFILE_SPEC): Ditto. 2020-07-23 Peter Bergner Backported from master: 2020-07-22 Peter Bergner PR target/96236 * config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Handle little-endian memory ordering. 2020-07-23 Kito Cheng Backported from master: 2020-07-23 Kito Cheng PR target/96260 * asan.c (asan_shadow_offset_set_p): New. * asan.h (asan_shadow_offset_set_p): Ditto. * toplev.c (process_options): Allow -fsanitize=kernel-address even TARGET_ASAN_SHADOW_OFFSET not implemented, only check when asan stack protection is enabled. 2020-07-23 Release Manager * GCC 10.2.0 released. 2020-07-21 Uroš Bizjak * config/i386/i386.h (TARGET_AVOID_MFENCE): Rename from TARGET_USE_XCHG_FOR_ATOMIC_STORE. * config/i386/sync.md (atomic_store): Update for rename. * config/i386/x86-tune.def (X86_TUNE_AVOID_MFENCE): Rename from X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE. 2020-07-17 Romain Naour Backported from master: 2020-06-03 Romain Naour * Makefile.in (SELFTEST_DEPS): Move before including language makefile fragments. 2020-07-16 Stefan Schulze Frielinghaus Backported from master: 2020-06-16 Stefan Schulze Frielinghaus * config.in: Regenerate. * config/s390/s390.c (print_operand): Emit vector alignment hints for target z13, if AS accepts them. For other targets the logic stays the same. * config/s390/s390.h (TARGET_VECTOR_LOADSTORE_ALIGNMENT_HINTS): Define macro. * configure: Regenerate. * configure.ac: Check HAVE_AS_VECTOR_LOADSTORE_ALIGNMENT_HINTS_ON_Z13. 2020-07-15 Richard Sandiford PR target/95726 * config/aarch64/aarch64.c (aarch64_attribute_table): Add "Advanced SIMD type". * config/aarch64/aarch64-builtins.c: Include stringpool.h and attribs.h. (aarch64_init_simd_builtin_types): Add an "Advanced SIMD type" attribute to each Advanced SIMD type. * config/arm/arm.c (arm_attribute_table): Add "Advanced SIMD type". * config/arm/arm-builtins.c: Include stringpool.h and attribs.h. (arm_init_simd_builtin_types): Add an "Advanced SIMD type" attribute to each Advanced SIMD type. 2020-07-15 Jakub Jelinek Backported from master: 2020-07-15 Jakub Jelinek PR target/96174 * config/i386/avx512fintrin.h (_mm512_cmpeq_pd_mask, _mm512_mask_cmpeq_pd_mask, _mm512_cmplt_pd_mask, _mm512_mask_cmplt_pd_mask, _mm512_cmple_pd_mask, _mm512_mask_cmple_pd_mask, _mm512_cmpunord_pd_mask, _mm512_mask_cmpunord_pd_mask, _mm512_cmpneq_pd_mask, _mm512_mask_cmpneq_pd_mask, _mm512_cmpnlt_pd_mask, _mm512_mask_cmpnlt_pd_mask, _mm512_cmpnle_pd_mask, _mm512_mask_cmpnle_pd_mask, _mm512_cmpord_pd_mask, _mm512_mask_cmpord_pd_mask, _mm512_cmpeq_ps_mask, _mm512_mask_cmpeq_ps_mask, _mm512_cmplt_ps_mask, _mm512_mask_cmplt_ps_mask, _mm512_cmple_ps_mask, _mm512_mask_cmple_ps_mask, _mm512_cmpunord_ps_mask, _mm512_mask_cmpunord_ps_mask, _mm512_cmpneq_ps_mask, _mm512_mask_cmpneq_ps_mask, _mm512_cmpnlt_ps_mask, _mm512_mask_cmpnlt_ps_mask, _mm512_cmpnle_ps_mask, _mm512_mask_cmpnle_ps_mask, _mm512_cmpord_ps_mask, _mm512_mask_cmpord_ps_mask): Move outside of __OPTIMIZE__ guarded section. 2020-07-15 Richard Biener Revert: 2020-07-14 Matthias Klose PR lto/95604 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, error on different values for -fcf-protection. (append_compiler_options): Pass -fcf-protection option. (find_and_merge_options): Add decoded options as parameter, pass decoded_options to merge_and_complain. (run_gcc): Pass decoded options to find_and_merge_options. * lto-opts.c (lto_write_options): Pass -fcf-protection option. 2020-07-14 Richard Sandiford PR middle-end/95114 * tree.h (virtual_method_call_p): Add a default-false parameter that indicates whether the function is being called from dump routines. (obj_type_ref_class): Likewise. * tree.c (virtual_method_call_p): Likewise. * ipa-devirt.c (obj_type_ref_class): Likewise. Lazily add ODR type information for the type when the parameter is false. * tree-pretty-print.c (dump_generic_node): Update calls to virtual_method_call_p and obj_type_ref_class accordingly. 2020-07-14 Richard Sandiford PR tree-optimization/96146 * value-range.cc (value_range::set): Only decompose POLY_INT_CST bounds to integers for VR_RANGE. Decay to VR_VARYING for anti-ranges involving POLY_INT_CSTs. 2020-07-14 Jakub Jelinek Backported from master: 2020-07-14 Jakub Jelinek PR middle-end/96194 * expr.c (expand_constructor): Don't create temporary for store to volatile MEM if exp has an addressable type. 2020-07-14 Matthias Klose Backported from master: 2020-07-14 Matthias Klose PR lto/95604 * lto-wrapper.c (merge_and_complain): Add decoded options as parameter, error on different values for -fcf-protection. (append_compiler_options): Pass -fcf-protection option. (find_and_merge_options): Add decoded options as parameter, pass decoded_options to merge_and_complain. (run_gcc): Pass decoded options to find_and_merge_options. * lto-opts.c (lto_write_options): Pass -fcf-protection option. 2020-07-13 Szabolcs Nagy Backported from master: 2020-07-13 Szabolcs Nagy * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_PAC_DEFAULT support. 2020-07-13 Szabolcs Nagy Backported from master: 2020-07-13 Szabolcs Nagy PR target/94891 * doc/extend.texi: Update the text for __builtin_return_address. 2020-07-13 Szabolcs Nagy Backported from master: 2020-07-13 Szabolcs Nagy PR target/94891 * config/aarch64/aarch64.c (aarch64_return_address_signing_enabled): Disable return address signing if __builtin_eh_return is used. 2020-07-13 Szabolcs Nagy Backported from master: 2020-07-13 Szabolcs Nagy PR target/94891 PR target/94791 * config/aarch64/aarch64-protos.h (aarch64_return_addr_rtx): Declare. * config/aarch64/aarch64.c (aarch64_return_addr_rtx): New. (aarch64_return_addr): Use aarch64_return_addr_rtx. * config/aarch64/aarch64.h (PROFILE_HOOK): Likewise. 2020-07-13 Szabolcs Nagy Backported from master: 2020-07-09 Szabolcs Nagy * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_BTI_DEFAULT support. 2020-07-13 Julian Brown Backported from master: 2020-07-13 Julian Brown Thomas Schwinge * gimplify.c (gimplify_scan_omp_clauses): Do not strip GOMP_MAP_TO_PSET/GOMP_MAP_POINTER for OpenACC enter/exit data directives (see also PR92929). 2020-07-13 Jakub Jelinek Backported from master: 2020-07-13 Jakub Jelinek PR ipa/96130 * ipa-fnsummary.c (analyze_function_body): Treat NULL bb->aux as false predicate. 2020-07-13 Hans-Peter Nilsson Backported from master: 2020-07-13 Richard Biener PR middle-end/94600 * expr.c (expand_constructor): Make a temporary also if we're storing to volatile memory. 2020-07-12 Jakub Jelinek Backported from master: 2020-07-02 Jakub Jelinek PR tree-optimization/95857 * tree-cfg.c (group_case_labels_stmt): When removing an unreachable base_bb, remember all forced and non-local labels on it and later treat those as if they have NULL label_to_block. Formatting fix. Fix a comment typo. 2020-07-10 Bill Seurer Backported from master: 2020-07-10 Bill Seurer PR target/95581 * config/rs6000/rs6000-call.c: Add new type v16qi_ftype_pcvoid. (altivec_init_builtins) Change __builtin_altivec_mask_for_load to use v16qi_ftype_pcvoid with correct number of parameters. 2020-07-10 Anton Youdkevitch * config/aarch64/aarch64.c (thunderx2t99_regmove_cost, thunderx2t99_vector_cost): Likewise. 2020-07-10 Peter Bergner Backported from master: 2020-07-09 Peter Bergner PR target/96125 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Define the MMA specific types __vector_quad and __vector_pair, and initialize the MMA built-ins if TARGET_EXTRA_BUILTINS is set. (mma_init_builtins): Don't test for mask set in rs6000_builtin_mask. Remove now unneeded mask variable. * config/rs6000/rs6000.c (rs6000_option_override_internal): Add the OPTION_MASK_MMA flag for power10 if not already set. 2020-07-10 Will Schmidt Backported from master: 2020-07-08 Will Schmidt * config/rs6000/altivec.h (vec_vmsumudm): New define. * config/rs6000/altivec.md (UNSPEC_VMSUMUDM): New unspec. (altivec_vmsumudm): New define_insn. * config/rs6000/rs6000-builtin.def (altivec_vmsumudm): New BU_ALTIVEC_3 entry. (vmsumudm): New BU_ALTIVEC_OVERLOAD_3 entry. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add entries for ALTIVEC_BUILTIN_VMSUMUDM variants of vec_msum. * doc/extend.texi: Add document for vmsumudm behind vmsum. 2020-07-10 Richard Biener Backported from master: 2020-07-10 Richard Biener PR tree-optimization/96133 * gimple-fold.c (fold_array_ctor_reference): Do not recurse to folding a CTOR that does not fully cover the asked for object. 2020-07-10 Bin Cheng Backported from master: 2020-07-09 Bin Cheng PR tree-optimization/95804 * tree-loop-distribution.c (break_alias_scc_partitions): Force negative post order to reduction partition. 2020-07-10 Bin Cheng Backported from master: 2020-06-20 Bin Cheng PR tree-optimization/95638 * tree-loop-distribution.c (pg_edge_callback_data): New field. (loop_distribution::break_alias_scc_partitions): Record and restore postorder information. Fix memory leak. 2020-07-09 Kito Cheng Backported from master: 2020-07-09 Kito Cheng * config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls): Abort if any arguments on stack. 2020-07-09 Kito Cheng Backported from master: 2020-06-22 Kito Cheng * config/riscv/riscv-builtins.c (RISCV_FTYPE_NAME0): New. (RISCV_FTYPE_ATYPES0): New. (riscv_builtins): Using RISCV_USI_FTYPE for frflags. * config/riscv/riscv-ftypes.def: Remove VOID argument. 2020-07-09 Kito Cheng Backported from master: 2020-06-16 Kito Cheng PR target/95683 * config/riscv/riscv.c (riscv_gpr_save_operation_p): Remove assertion and turn it into a early exit check. 2020-07-09 Kito Cheng Backported from master: 2020-06-15 Kito Cheng * config/riscv/riscv.c (riscv_gen_gpr_save_insn): Change type to unsigned for i. (riscv_gpr_save_operation_p): Change type to unsigned for i and len. 2020-07-09 Kito Cheng Backported from master: 2020-06-11 Kito Cheng * config/riscv/riscv-protos.h (riscv_output_gpr_save): Remove. * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Update value. * config/riscv/riscv.c (riscv_output_gpr_save): Remove. * config/riscv/riscv.md (gpr_save): Update output asm pattern. 2020-07-09 Kito Cheng Backported from master: 2020-06-11 Kito Cheng * config/riscv/predicates.md (gpr_save_operation): New. * config/riscv/riscv-protos.h (riscv_gen_gpr_save_insn): New. (riscv_gpr_save_operation_p): Ditto. * config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls): Ignore USEs for gpr_save patter. * config/riscv/riscv.c (gpr_save_reg_order): New. (riscv_expand_prologue): Use riscv_gen_gpr_save_insn to gen gpr_save. (riscv_gen_gpr_save_insn): New. (riscv_gpr_save_operation_p): Ditto. * config/riscv/riscv.md (S3_REGNUM): New. (S4_REGNUM): Ditto. (S5_REGNUM): Ditto. (S6_REGNUM): Ditto. (S7_REGNUM): Ditto. (S8_REGNUM): Ditto. (S9_REGNUM): Ditto. (S10_REGNUM): Ditto. (S11_REGNUM): Ditto. (gpr_save): Model USEs correctly. 2020-07-09 Keith Packard Backported from master: 2020-05-12 Keith Packard * config/riscv/riscv.c (riscv_unique_section): New. (TARGET_ASM_UNIQUE_SECTION): New. 2020-07-08 Richard Sandiford PR target/95105 * config/aarch64/aarch64-sve-builtins.cc (handle_arm_sve_vector_bits_attribute): Create a copy of the original type's TYPE_MAIN_VARIANT, then reapply all the differences between the original type and its main variant. 2020-07-07 Richard Biener Backported from master: 2020-07-06 Richard Biener PR tree-optimization/96075 * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Use TYPE_SIZE_UNIT of the vector component type instead of DR_STEP for the misalignment calculation for negative step. 2020-07-07 Richard Biener Backported from master: 2020-07-07 Richard Biener * lto-streamer-out.c (cmp_symbol_files): Use the computed order map to sort symbols from the same sub-file together. (lto_output): Compute a map of sub-file to an order number it appears in the symbol output array. 2020-07-06 Will Schmidt * config/rs6000/altivec.h (vec_pack_to_short_fp32): Update. * config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec. (convert_4f32_8f16): New define_expand * config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define and overload. * config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New overloaded builtin entry. * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec. (vsx_xvcvsphp): New define_insn. 2020-07-04 Martin Jambor Backported from master: 2020-07-03 Martin Jambor PR ipa/96040 * ipa-sra.c (all_callee_accesses_present_p): Do not accept type mismatched accesses. 2020-07-03 Martin Jambor Backported from master: 2020-07-02 Martin Jambor PR debug/95343 * ipa-param-manipulation.c (ipa_param_adjustments::modify_call): Adjust argument index if necessary. 2020-07-02 Segher Boessenkool * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define _ARCH_PWR10 when appropriate. 2020-07-02 Peter Bergner Backported from master: 2020-06-26 Peter Bergner * config/rs6000/rs6000-call.c (cpu_is_info) : New. * doc/extend.texi (PowerPC Built-in Functions): Document power10, arch_3_1 and mma. 2020-07-02 Michael Meissner Backported from master: 2020-06-09 Michael Meissner * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Allocate 'power10' PowerPC platform. (PPC_FEATURE2_ARCH_3_1): New HWCAP2 bit for ARCH 3.1. (PPC_FEATURE2_MMA): New HWCAP2 bit for MMA. * config/rs6000/rs6000-call.c (cpu_supports_info): Add ARCH 3.1 and MMA HWCAP2 bits. 2020-07-01 Srinath Parvathaneni Backported from master: 2020-06-22 Srinath Parvathaneni * doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item. (arm_mve_hw): Likewise. 2020-06-30 Segher Boessenkool * config/rs6000/rs6000.md (isa): Rename "fut" to "p10". 2020-06-30 Segher Boessenkool * config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10 on AIX, and -mpower10 elsewhere. * config/rs6000/future.md: Delete. * config/rs6000/linux64.h: Update comments. Use TARGET_POWER10, not TARGET_FUTURE. * config/rs6000/power10.md: New file. * config/rs6000/rs6000-builtin.def: Update comments. * config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*. Update compiler messages. * config/rs6000/rs6000-cpus.def: Update comments. Use ISA_3_1_*, not ISA_FUTURE_*. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. * config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. * config/rs6000/rs6000-string.c: Ditto. * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10" instead of "future", reorder it to right after "power9". * config/rs6000/rs6000.c: Update comments. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use TARGET_POWER10, not TARGET_FUTURE. Use RS6000_BTM_P10, not RS6000_BTM_FUTURE. Update compiler messages. Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. Use ISA_3_1_MASKS_SERVER, not ISA_FUTURE_MASKS_SERVER. (rs6000_opt_masks): Use "power10" instead of "future". (rs6000_builtin_mask_names): Ditto. (rs6000_disable_incompatible_switches): Ditto. * config/rs6000/rs6000.h: Use -mpower10, not -mfuture. Use -mcpu=power10, not -mcpu=future. Use MASK_POWER10, not MASK_FUTURE. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use RS6000_BTM_P10, not RS6000_BTM_FUTURE. * config/rs6000/rs6000.md: Use "power10", not "future". Use TARGET_POWER10, not TARGET_FUTURE. Include "power10.md", not "future.md". * config/rs6000/rs6000.opt (mfuture): Delete. (mpower10): New. * config/rs6000/t-rs6000: Use "power10.md", not "future.md". * config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE. 2020-06-30 Alex Coplan Backported from master: 2020-05-18 Alex Coplan * config/arm/arm.c (output_move_double): Fix codegen when loading into a register pair with an odd base register. 2020-06-29 Jakub Jelinek Backported from master: 2020-06-24 Jakub Jelinek PR middle-end/95810 * fold-const.c (fold_cond_expr_with_comparison): Optimize A <= 0 ? A : -A into (type)-absu(A) rather than -abs(A). 2020-06-25 H.J. Lu Backported from master: 2020-06-25 H.J. Lu PR target/95874 * config/i386/i386.h (PTA_ICELAKE_CLIENT): Remove PTA_CLWB. (PTA_ICELAKE_SERVER): Add PTA_CLWB. (PTA_TIGERLAKE): Add PTA_CLWB. 2020-06-24 Peter Bergner Backported from master: 2020-06-21 Peter Bergner * config/rs6000/predicates.md (mma_assemble_input_operand): New. * config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3, BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA built-in functions. (ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR, PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP, PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN, PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN, PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP, PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4, PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP, XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2, XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER, XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN, XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S, XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP, XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins. * config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P. Allow zero constants. (print_operand) : New output modifier. (rs6000_split_multireg_move): Add support for inserting accumulator priming and depriming instructions. Add support for splitting an assemble accumulator pattern. * config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin, rs6000_gimple_fold_mma_builtin): New functions. (RS6000_BUILTIN_M): New macro. (def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes. (bdesc_mma): Add new MMA built-in support. (htm_expand_builtin): Use RS6000_BTC_OPND_MASK. (rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and RS6000_BTM_MMA. (rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute. (rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p and rs6000_gimple_fold_mma_builtin. (rs6000_expand_builtin): Call mma_expand_builtin. Use RS6000_BTC_OPND_MASK. (rs6000_init_builtins): Adjust comment. Call mma_init_builtins. (htm_init_builtins): Use RS6000_BTC_OPND_MASK. (builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and VSX_BUILTIN_XVCVBF16SP. * config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY, RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR, RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines. (RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST, RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values. * config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant. (UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2, UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP, UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP, UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN, UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN, UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER, UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP, UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP, UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN, UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN, UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2, UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S, UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8, UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4, UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP, UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN, UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN, UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN, UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP, UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP, UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER, UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN, UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP, UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8, UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP, UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New. (MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8, MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4, MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4, MMA_AVVI4I4I4): New define_int_iterator. (acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2, avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4, avvi4i4i4): New define_int_attr. (*movpxi): Add zero constant alternative. (mma_assemble_pair, mma_assemble_acc): New define_expand. (*mma_assemble_acc): New define_insn_and_split. (mma_, mma_xxsetaccz, mma_, mma_, mma_, mma_, mma_, mma_, mma_, mma_, mma_, mma_, mma_, mma_, mma_, mma_): New define_insn. * config/rs6000/rs6000.md (define_attr "type"): New type mma. * config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New. (UNSPEC_VSX_XVCVSPBF16): Likewise. (XVCVBF16): New define_int_iterator. (xvcvbf16): New define_int_attr. (vsx_): New define_insn. * doc/extend.texi: Document the mma built-ins. 2020-06-24 Kelvin Nilsen * config/rs6000/predicates.md (u8bit_cint_operand): New predicate. 2020-06-24 Peter Bergner Backported from master: 2020-06-21 Peter Bergner Michael Meissner * config/rs6000/mma.md: New file. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define __MMA__ for mma. * config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support for __vector_pair and __vector_quad types. * config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add OPTION_MASK_MMA. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000-modes.def (OI, XI): New integer modes. (POI, PXI): New partial integer modes. * config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define. (rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P. (rs6000_hard_regno_mode_ok_uncached): Likewise. Add support for POImode being allowed in VSX registers and PXImode being allowed in FP registers. (rs6000_modes_tieable_p): Adjust comment. Add support for POImode and PXImode. (rs6000_debug_reg_global) : Add OImode, POImode XImode, PXImode, V2SImode, V2SFmode and CCFPmode.. (rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P. Set up appropriate addr_masks for vector pair and vector quad addresses. (rs6000_init_hard_regno_mode_ok): Add support for vector pair and vector quad registers. Setup reload handlers for POImode and PXImode. (rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA. (rs6000_option_override_internal): Error if -mmma is specified without -mcpu=future. (rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P. (quad_address_p): Change size test to less than 16 bytes. (reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair and vector quad instructions. (avoiding_indexed_address_p): Likewise. (rs6000_emit_move): Disallow POImode and PXImode moves involving constants. (rs6000_preferred_reload_class): Prefer VSX registers for POImode and FP registers for PXImode. (rs6000_split_multireg_move): Support splitting POImode and PXImode move instructions. (rs6000_mangle_type): Adjust comment. Add support for mangling __vector_pair and __vector_quad types. (rs6000_opt_masks): Add entry for mma. (rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. (rs6000_function_value): Use VECTOR_ALIGNMENT_P. (address_to_insn_form): Likewise. (reg_to_non_prefixed): Likewise. (rs6000_invalid_conversion): New function. * config/rs6000/rs6000.h (MASK_MMA): Define. (BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled. (VECTOR_ALIGNMENT_P): New helper macro. (ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P. (RS6000_BTM_MMA): Define. (RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. (rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and RS6000_BTI_vector_quad. (vector_pair_type_node): New. (vector_quad_type_node): New. * config/rs6000/rs6000.md: Include mma.md. (define_mode_iterator RELOAD): Add POI and PXI. * config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md. * config/rs6000/rs6000.opt (-mmma): New. * doc/invoke.texi: Document -mmma. 2020-06-24 Richard Biener Backported from master: 2020-06-17 Richard Biener PR tree-optimization/95717 * tree-vect-loop-manip.c (slpeel_tree_duplicate_loop_to_edge_cfg): Move BB SSA updating before exit/latch PHI current def copying. 2020-06-23 Richard Biener PR middle-end/95493 PR middle-end/95690 * cfgexpand.c (expand_debug_expr): Avoid calling set_mem_attributes_minus_bitpos when we were expanding an SSA name. * emit-rtl.c (set_mem_attributes_minus_bitpos): Remove ARRAY_REF special-casing, add CONSTRUCTOR to the set of special-cases we do not want MEM_EXPRs for. Assert we end up with reasonable MEM_EXPRs. * varasm.c (build_constant_desc): Remove set_mem_attributes call. 2020-06-23 Richard Biener PR tree-optimization/95487 * tree-vect-stmts.c (vectorizable_store): Use a truth type for the scatter mask. 2020-06-23 Richard Biener PR tree-optimization/95308 * tree-ssa-forwprop.c (pass_forwprop::execute): Generalize test for TARGET_MEM_REFs. 2020-06-23 Richard Biener PR tree-optimization/95133 * gimple-ssa-split-paths.c (find_block_to_duplicate_for_splitting_paths): Check for normal edges. 2020-06-23 Richard Biener PR middle-end/95118 * real.c (real_to_decimal_for_mode): Make sure we handle a zero with nonzero exponent. 2020-06-23 Richard Biener PR tree-optimization/95049 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition between different constants. 2020-06-23 Richard Biener PR middle-end/94964 * cfgloopmanip.c (create_preheader): Require non-complex preheader edge for CP_SIMPLE_PREHEADERS. 2020-06-20 Bin Cheng PR tree-optimization/94969 * tree-data-ref.c (constant_access_functions): Rename to... (invariant_access_functions): ...this. Add parameter. Check for invariant access function, rather than constant. (build_classic_dist_vector): Call above function. * tree-loop-distribution.c (pg_add_dependence_edges): Add comment. 2020-06-19 Jiufu Guo PR target/95018 * common.opt (flag_cunroll_grow_size): New flag. * toplev.c (process_options): Set flag_cunroll_grow_size. * tree-ssa-loop-ivcanon.c (pass_complete_unroll::execute): Use flag_cunroll_grow_size. * config/rs6000/rs6000.c (rs6000_option_override_internal): Override flag_cunroll_grow_size. 2020-06-18 Aaron Sawdey PR target/95347 * config/rs6000/rs6000.c (is_stfs_insn): Rename to is_lfs_stfs_insn and make it recognize lfs as well. (prefixed_store_p): Use is_lfs_stfs_insn(). (prefixed_load_p): Use is_lfs_stfs_insn() to recognize lfs. 2020-06-18 Aaron Sawdey PR target/95347 * config/rs6000/rs6000.c (prefixed_store_p): Add special case for stfs. (is_stfs_insn): New helper function. 2020-06-18 Jakub Jelinek Backported from master: 2020-06-18 Jakub Jelinek PR target/95713 * tree-ssa-forwprop.c (simplify_vector_constructor): Don't allow scalar mode halfvectype other than vector boolean for VEC_PACK_TRUNC_EXPR. 2020-06-18 Srinath Parvathaneni Backported from master: 2020-06-16 Srinath Parvathaneni * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Correct the intrinsic arguments. (__arm_vaddq_m_n_s32): Likewise. (__arm_vaddq_m_n_s16): Likewise. (__arm_vaddq_m_n_u8): Likewise. (__arm_vaddq_m_n_u32): Likewise. (__arm_vaddq_m_n_u16): Likewise. (__arm_vaddq_m): Modify polymorphic variant. 2020-06-18 Srinath Parvathaneni Backported from master: 2020-06-16 Srinath Parvathaneni * config/arm/mve.md (mve_uqrshll_sat_di): Correct the predicate and constraint of all the operands. (mve_sqrshrl_sat_di): Likewise. (mve_uqrshl_si): Likewise. (mve_sqrshr_si): Likewise. (mve_uqshll_di): Likewise. (mve_urshrl_di): Likewise. (mve_uqshl_si): Likewise. (mve_urshr_si): Likewise. (mve_sqshl_si): Likewise. (mve_srshr_si): Likewise. (mve_srshrl_di): Likewise. (mve_sqshll_di): Likewise. * config/arm/predicates.md (arm_low_register_operand): Define. 2020-06-17 Thomas Schwinge Backported from master: 2020-06-17 Thomas Schwinge * hsa-gen.c (gen_hsa_insns_for_call): Move 'function_decl == NULL_TREE' check earlier. 2020-06-16 Srinath Parvathaneni * config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic arguments. (__arm_vbicq_n_s16): Likewise. (__arm_vbicq_n_u32): Likewise. (__arm_vbicq_n_s32): Likewise. (__arm_vbicq): Modify polymorphic variant. 2020-06-16 Srinath Parvathaneni PR target/94735 * config/arm/predicates.md (mve_scatter_memory): Define to match (mem (reg)) for scatter store memory. * config/arm/mve.md (mve_vstrbq_scatter_offset_): Modify define_insn to define_expand. (mve_vstrbq_scatter_offset_p_): Likewise. (mve_vstrhq_scatter_offset_): Likewise. (mve_vstrhq_scatter_shifted_offset_p_): Likewise. (mve_vstrhq_scatter_shifted_offset_): Likewise. (mve_vstrdq_scatter_offset_p_v2di): Likewise. (mve_vstrdq_scatter_offset_v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_p_v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_v2di): Likewise. (mve_vstrhq_scatter_offset_fv8hf): Likewise. (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. (mve_vstrwq_scatter_offset_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_v4si): Likewise. (mve_vstrwq_scatter_offset_v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_v4si): Likewise. (mve_vstrbq_scatter_offset__insn): Define insn for scatter stores. (mve_vstrbq_scatter_offset_p__insn): Likewise. (mve_vstrhq_scatter_offset__insn): Likewise. (mve_vstrhq_scatter_shifted_offset_p__insn): Likewise. (mve_vstrhq_scatter_shifted_offset__insn): Likewise. (mve_vstrdq_scatter_offset_p_v2di_insn): Likewise. (mve_vstrdq_scatter_offset_v2di_insn): Likewise. (mve_vstrdq_scatter_shifted_offset_p_v2di_insn): Likewise. (mve_vstrdq_scatter_shifted_offset_v2di_insn): Likewise. (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise. (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise. (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise. (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise. (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise. (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise. (mve_vstrwq_scatter_offset_p_v4si_insn): Likewise. (mve_vstrwq_scatter_offset_v4si_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_p_v4si_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_v4si_insn): Likewise. 2020-06-16 Srinath Parvathaneni * config/arm/arm.c (mve_vector_mem_operand): Fix unwanted fall-throughs. 2020-06-16 Srinath Parvathaneni Andre Vieira PR target/94959 * config/arm/arm-protos.h (arm_mode_base_reg_class): Function declaration. (mve_vector_mem_operand): Likewise. * config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check the load from memory to a core register is legitimate for give mode. (mve_vector_mem_operand): Define function. (arm_print_operand): Modify comment. (arm_mode_base_reg_class): Define. * config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE. * config/arm/constraints.md (Ux): Likewise. (Ul): Likewise. * config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also add support for missing Vector Store Register and Vector Load Register. Add a new alternative to support load from memory to PC (or label) in vector store/load. (mve_vstrbq_): Modify constraint Us to Ux. (mve_vldrbq_): Modify constriant Us to Ux, predicate to mve_memory_operand and also modify the MVE instructions to emit. (mve_vldrbq_z_): Modify constraint Us to Ux. (mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to mve_memory_operand and also modify the MVE instructions to emit. (mve_vldrhq_): Modify constriant Us to Ux, predicate to mve_memory_operand and also modify the MVE instructions to emit. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrhq_z_): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vldrwq_z_v4si): Likewise. (mve_vld1q_f): Modify constriant Us to Ux. (mve_vld1q_): Likewise. (mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to mve_memory_operand. (mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to mve_memory_operand and also modify the MVE instructions to emit. (mve_vstrhq_p_): Likewise. (mve_vstrhq_): Modify constriant Us to Ux, predicate to mve_memory_operand. (mve_vstrwq_fv4sf): Modify constriant Us to Ux. (mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE instructions to emit. (mve_vstrwq_p_v4si): Likewise. (mve_vstrwq_v4si): Likewise.Modify constriant Us to Ux. * config/arm/predicates.md (mve_memory_operand): Define. 2020-06-15 Andrew Stubbs * config/gcn/gcn-valu.md (v3): Fix unsignedp. 2020-06-15 Tobias Burnus * omp-offload.c (add_decls_addresses_to_decl_constructor, omp_finish_file): With in_lto_p, stream out all offload-table items even if the symtab_node does not exist. 2020-06-15 Tobias Burnus PR lto/94848 PR middle-end/95551 * omp-offload.c (add_decls_addresses_to_decl_constructor, omp_finish_file): Skip removed items. * lto-cgraph.c (output_offload_tables): Likewise; set force_output to this node for variables and functions. 2020-06-14 Jakub Jelinek PR target/95528 * tree-ssa-forwprop.c (simplify_vector_constructor): Don't use VEC_UNPACK*_EXPR or VEC_PACK_TRUNC_EXPR with scalar modes unless the type is vector boolean. 2020-06-14 Jakub Jelinek PR c++/95197 * gimplify.c (find_combined_omp_for): Move to omp-general.c. * omp-general.h (find_combined_omp_for): Declare. * omp-general.c: Include tree-iterator.h. (find_combined_omp_for): New function, moved from gimplify.c. 2020-06-14 Jakub Jelinek PR middle-end/95108 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member. (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in entry block if info->after_stmt is NULL, otherwise add after that stmt and update it after adding each stmt. (ipa_simd_modify_function_body): Initialize info.after_stmt. 2020-06-14 Jakub Jelinek PR debug/95080 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even if the last insn is a note. 2020-06-12 Martin Liska Jakub Jelinek PR sanitizer/95634 * asan.c (asan_emit_stack_protection): Fix emission for ilp32 by using Pmode instead of ptr_mode. 2020-06-12 Martin Liska PR sanitizer/94910 * asan.c (asan_emit_stack_protection): Emit also **SavedFlagPtr(FakeStack, class_id) = 0 in order to release a stack frame. 2020-06-08 Martin Jambor PR ipa/95113 * tree-ssa-dce.c (mark_stmt_if_obviously_necessary): Move non-call exceptions check to... * tree-eh.c (stmt_unremovable_because_of_non_call_eh_p): ...this new function. * tree-eh.h (stmt_unremovable_because_of_non_call_eh_p): Declare it. * ipa-sra.c (isra_track_scalar_value_uses): Use it. New parameter fun. 2020-06-05 Thomas Schwinge Julian Brown * gimplify.c (gimplify_adjust_omp_clauses): Remove 'GOMP_MAP_STRUCT' mapping from OpenACC 'exit data' directives. 2020-06-05 H.J. Lu * config/i386/driver-i386.c (host_detect_local_cpu): Support Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake processor families. 2020-06-05 Lili Cui PR target/95525 * config/i386/i386.h (PTA_WAITPKG): Change bitmask value. 2020-06-02 Kyrylo Tkachov * config/aarch64/aarch64-cores.def (zeus): Define. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (AArch64 Options): Document zeus -mcpu option. 2020-06-02 Iain Buclaw PR target/95420 * config.gcc (arm-wrs-vxworks7*): Set default cpu to generic-armv7-a. 2020-05-29 Alex Coplan PR target/94591 * config/aarch64/aarch64.c (aarch64_evpc_rev_local): Don't match identity permutation. 2020-05-29 Andrew Stubbs * config/gcn/gcn-valu.md (add3_zext_dup): Change to a define_expand, and rename the original to ... (add3_vcc_zext_dup): ... this, and add a custom VCC operand. (add3_zext_dup_exec): Likewise, with ... (add3_vcc_zext_dup_exec): ... this. (add3_zext_dup2): Likewise, with ... (add3_zext_dup_exec): ... this. (add3_zext_dup2_exec): Likewise, with ... (add3_zext_dup2): ... this. * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch addv64di3_zext* calls to use addv64di3_vcc_zext*. 2020-05-29 Dong JianQiang PR gcov-profile/95332 * gcov-io.c (gcov_var::endian): Move field. (from_file): Add IN_GCOV_TOOL check. * gcov-io.h (gcov_magic): Ditto. 2020-05-28 Richard Sandiford PR testsuite/95361 * config/aarch64/aarch64.c (aarch64_expand_epilogue): Only redefine the CFA if we have CFI operations. 2020-05-28 Uroš Bizjak * config/i386/mmx.md (mmx_haddsubv2sf3): Correct RTL template to model horizontal subtraction and addition. 2020-05-28 Uroš Bizjak PR target/95355 * config/i386/sse.md (avx512f_v16qiv16si2): Remove %q operand modifier from insn template. (avx512f_v8hiv8di2): Ditto. 2020-05-28 Martin Liska PR web/95380 * doc/invoke.texi: Add missing params, remove max-once-peeled-insns and rename ipcp-unit-growth to ipa-cp-unit-growth. 2020-05-24 Uroš Bizjak PR target/95255 * config/i386/i386.md (2): Do not try to expand non-sse4 ROUND_ROUNDEVEN rounding via SSE support routines. 2020-05-24 Iain Sandoe Backported from master. 2020-05-22 Iain Sandoe * config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): Make ubsan_{data,type},ASAN linker-visible. 2020-05-24 H.J. Lu PR target/95258 * config/i386/driver-i386.c (host_detect_local_cpu): Detect AVX512VPOPCNTDQ. 2020-05-22 Richard Biener PR lto/95190 * doc/invoke.texi (flto): Document behavior of diagnostic options. 2020-05-21 Uroš Bizjak PR target/95169 * config/i386/i386-expand.c (ix86_expand_int_movcc): Avoid reversing a non-trapping comparison to a trapping one. 2020-05-21 Martin Liska * common/config/aarch64/aarch64-common.c (aarch64_handle_option): Handle OPT_moutline_atomics. * config/aarch64/aarch64.c: Add outline-atomics to aarch64_attributes. * doc/extend.texi: Document the newly added target attribute. 2020-05-21 H.J. Lu Backport from master 2020-05-21 H.J. Lu PR target/95212 * config/i386/i386-builtins.c (processor_features): Move F_AVX512VP2INTERSECT after F_AVX512BF16. (isa_names_table): Likewise. 2020-05-19 Gerald Pfeifer Backport from mainline 2020-05-10 Gerald Pfeifer * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and __ILP32__ for 32-bit targets. 2020-05-19 Tobias Burnus Backport from mainline 2020-05-15 Tobias Burnus PR middle-end/94635 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with OMP_TARGET_EXIT_DATA, use 'release:' unless the associated item is 'delete:'. 2020-05-18 Martin Sebor PR middle-end/94940 * tree-vrp.c (vrp_prop::check_mem_ref): Remove unreachable code. * tree.c (component_ref_size): Correct the handling or array members of unions. Drop a pointless test. Rename a local variable. 2020-05-12 Richard Biener Backport from mainline 2020-05-07 Richard Biener PR ipa/94947 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible. (refered_from_nonlocal_var): Likewise. (ipa_pta_execute): Likewise. 2020-05-05 Richard Biener PR ipa/94947 * tree-ssa-structalias.c (ipa_pta_execute): Use varpool_node::externally_visible_p (). (refered_from_nonlocal_var): Likewise. 2020-05-12 David Edelsohn Backport from mainline 2020-05-04 Clement Chigot David Edelsohn * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit for fmodl, frexpl, ldexpl and modfl builtins. 2020-05-11 Sebastian Huber Backport from mainline 2020-05-05 Sebastian Huber * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined. (RTEMS_ENDFILE_SPEC): Likewise. (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC. (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC. (LIB_SPECS): Support -nodefaultlibs option. * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define. (RTEMS_ENDFILE_SPEC): Likewise. * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise. (RTEMS_ENDFILE_SPEC): Likewise. * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise. (RTEMS_ENDFILE_SPEC): Likewise. 2020-05-11 Martin Liska Backport from mainline 2020-05-11 Martin Liska PR c/95040 * common.opt: Fix typo in option description. 2020-05-08 Jakub Jelinek PR middle-end/94724 * tree.c (get_narrower): Reuse the op temporary instead of shadowing it. 2020-05-07 Uroš Bizjak * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR for the first assignments to fenv_var and new_fenv_var. 2020-05-07 Martin Liska Backport from mainline 2020-05-07 Martin Liska * doc/invoke.texi: Fix 2 optindex entries. 2020-05-07 Jakub Jelinek Backported from mainline 2020-05-06 Jakub Jelinek PR target/94950 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags. PR rtl-optimization/94873 * combine.c (combine_instructions): Don't optimize using REG_EQUAL note if SET_SRC (set) has side-effects. 2020-05-05 Jakub Jelinek PR target/94942 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv. 2020-05-04 Jakub Jelinek * opts.c (get_option_html_page): Instead of hardcoding a list of options common between C/C++ and Fortran only use gfortran/ documentation for warnings that have CL_Fortran set but not CL_C or CL_CXX. 2020-05-07 Jakub Jelinek * BASE-VER: Set to 10.1.1. 2020-05-07 Release Manager * GCC 10.1.0 released. 2020-05-06 Rainer Orth * doc/install.texi: Replace Sun with Solaris as appropriate. (Tools/packages necessary for building GCC, Perl version between 5.6.1 and 5.6.24): Remove Solaris 8 reference. (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove TGCware reference. (Specific, i?86-*-solaris2*): Update version references for Solaris 11.3 and later. Remove gas 2.26 caveat. (Specific, *-*-solaris2*): Update version references for Solaris 11.3 and later. Remove boehm-gc reference. Document GMP, MPFR caveats on Solaris 11.3. (Specific, sparc-sun-solaris2*): Update Solaris 9 references. (Specific, sparc64-*-solaris2*): Likewise. Document --build requirement. 2020-05-05 Rainer Orth * configure.ac : Add --32 to tls_as_opt on Solaris. * configure: Regenerate. 2020-05-04 Richard Sandiford PR middle-end/94941 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the chosen lhs is different from the gcall lhs. (expand_mask_load_optab_fn): Likewise. (expand_gather_load_optab_fn): Likewise. 2020-05-04 Marek Polacek Revert: 2020-04-30 Marek Polacek PR c++/94775 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match. (check_aligned_type): Check if TYPE_USER_ALIGN match. 2020-05-02 Jakub Jelinek * config/tilegx/tilegx.md (insn_stnt_add): Use rather than just . 2020-04-30 Alexandre Oliva * doc/sourcebuild.texi (Effective-Target Keywords): Document the newly-introduced fileio effective target. 2020-04-30 Richard Sandiford PR rtl-optimization/94740 * cse.c (cse_process_notes_1): Replace with... (cse_process_note_1): ...this new function, acting as a simplify_replace_fn_rtx callback to process_note. Handle only REGs and MEMs directly. Validate the MEM if cse_process_note changes its address. (cse_process_notes): Replace with... (cse_process_note): ...this new function. (cse_extended_basic_block): Update accordingly, iterating over the register notes and passing individual notes to cse_process_note. 2020-04-30 Martin Jambor PR ipa/94856 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies saved by the inliner and thunks which had their call inlined. * ipa-inline-transform.c (save_inline_function_body): Fill in former_clone_of of new body holders. 2020-04-30 Jakub Jelinek * DEV-PHASE: Set to prerelease. 2020-04-30 Jonathan Wakely * pretty-print.c (pp_take_prefix): Fix spelling in comment. 2020-04-30 Marek Polacek PR c++/94775 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match. (check_aligned_type): Check if TYPE_USER_ALIGN match. 2020-04-30 Kyrylo Tkachov * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define. * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable. * doc/invoke.texi (moutline-atomics): Document as on by default. 2020-04-30 Szabolcs Nagy PR target/94748 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove the check for NOTE_INSN_DELETED_LABEL. 2020-04-30 Jakub Jelinek * configure.ac (--with-documentation-root-url, --with-changes-root-url): Diagnose URL not ending with /, use AC_DEFINE_UNQUOTED instead of AC_SUBST. * opts.h (get_changes_url): Remove. * opts.c (get_changes_url): Remove. * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL or -DCHANGES_ROOT_URL. * doc/install.texi (--with-documentation-root-url, --with-changes-root-url): Document. * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call get_changes_url and free, change url variable type to const char * and set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base". * config/s390/s390.c (s390_function_arg_vector, s390_function_arg_float): Likewise. * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate): Likewise. * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate): Likewise. * config.in: Regenerate. * configure: Regenerate. 2020-04-30 Christophe Lyon PR target/57002 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries. 2020-04-30 Andreas Krebbel * config/s390/constraints.md ("j>f", "jb4"): New constraints. * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix macro definitions. * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a separate expander. ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst. Change constraint for vlrl/vstrl to jb4. 2020-04-30 Stefan Schulze Frielinghaus * var-tracking.c (vt_initialize): Move variables pre and post into inner block and initialize both in order to fix warning about uninitialized use. Remove unnecessary checks for frame_pointer_needed. 2020-04-30 Stefan Schulze Frielinghaus * toplev.c (output_stack_usage_1): Ensure that first argument to fprintf is not null. 2020-04-29 Jakub Jelinek * configure.ac (-with-changes-root-url): New configure option, defaulting to https://gcc.gnu.org/. * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for opts.c. * pretty-print.c (get_end_url_string): New function. (pp_format): Handle %{ and %} for URLs. (pp_begin_url): Use pp_string instead of pp_printf. (pp_end_url): Use get_end_url_string. * opts.h (get_changes_url): Declare. * opts.c (get_changes_url): New function. * config/rs6000/rs6000-call.c: Include opts.h. (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead of just in GCC 10.1 in diagnostics and add URL. * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise. * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate): Likewise. * config/s390/s390.c (s390_function_arg_vector, s390_function_arg_float): Likewise. * configure: Regenerated. PR target/94704 * config/s390/s390.c (s390_function_arg_vector, s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type passed to the function rather than the type of the single element. Rename cxx17_empty_base_seen variable to empty_base_seen, change type to int, and adjust diagnostics depending on if the field has [[no_unique_attribute]] or not. PR target/94832 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8, _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands used in casts into parens. * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph, _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph, _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph, _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask, _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask, _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask, _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise. * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8, _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8, _mm256_mask_cmp_epu8_mask): Likewise. * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph, _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise. * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise. * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise. PR target/94832 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd, _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd, _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps, _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps, _mm256_mask_i64gather_ps, _mm_i32gather_epi64, _mm_mask_i32gather_epi64, _mm256_i32gather_epi64, _mm256_mask_i32gather_epi64, _mm_i64gather_epi64, _mm_mask_i64gather_epi64, _mm256_i64gather_epi64, _mm256_mask_i64gather_epi64, _mm_i32gather_epi32, _mm_mask_i32gather_epi32, _mm256_i32gather_epi32, _mm256_mask_i32gather_epi32, _mm_i64gather_epi32, _mm_mask_i64gather_epi32, _mm256_i64gather_epi32, _mm256_mask_i64gather_epi32): Surround macro parameter uses with parens. (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd, _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps, _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use as mask vector containing -1.0 or -1.0f elts, but instead vector with all bits set using _mm*_cmpeq_p? with zero operands. * config/i386/avx512fintrin.h (_mm512_i32gather_ps, _mm512_mask_i32gather_ps, _mm512_i32gather_pd, _mm512_mask_i32gather_pd, _mm512_i64gather_ps, _mm512_mask_i64gather_ps, _mm512_i64gather_pd, _mm512_mask_i64gather_pd, _mm512_i32gather_epi32, _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64, _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32, _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64, _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps, _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd, _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps, _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd, _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32, _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64, _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32, _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64, _mm512_mask_i64scatter_epi64): Surround macro parameter uses with parens. * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd, _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd, _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd, _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd, _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd, _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd, _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd, _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd, _mm512_mask_prefetch_i64scatter_ps): Likewise. * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps, _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd, _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps, _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd, _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32, _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64, _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32, _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64, _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps, _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps, _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd, _mm_mask_i32scatter_pd, _mm256_i64scatter_ps, _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps, _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd, _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32, _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32, _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64, _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64, _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32, _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32, _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64, _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64, _mm_mask_i64scatter_epi64): Likewise. 2020-04-29 Jeff Law * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific division instructions are 4 bytes long. 2020-04-29 Jakub Jelinek PR target/94826 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR for first assignment to fenv_var, fenv_clear and old_fenv variables. For fenv_addr take address of TARGET_EXPR of fenv_var with void_node initializer. Formatting fixes. 2020-04-29 Stefan Schulze Frielinghaus PR tree-optimization/94774 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize variable retval. 2020-04-29 Richard Sandiford * calls.h (cxx17_empty_base_field_p): Turn into a function declaration. * calls.c (cxx17_empty_base_field_p): New function. Check DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the previous checks. 2020-04-29 H.J. Lu PR target/93654 * config/i386/i386-options.c (ix86_set_indirect_branch_type): Allow -fcf-protection with -mindirect-branch=thunk-extern and -mfunction-return=thunk-extern. * doc/invoke.texi: Update notes for -fcf-protection=branch with -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern. 2020-04-29 Richard Sandiford * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor. 2020-04-29 Richard Sandiford * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR for the first assignments to fenv_var and new_fenv_var. 2020-04-29 Richard Sandiford * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new effective-target keyword. (arm_arch_v8a_hard_multilib): Likewise. (arm_arch_v8a_hard): Document new dg-add-options keyword. * config/arm/arm.c (arm_return_in_memory): Note that the APCS code is deprecated and has not been updated to handle DECL_FIELD_ABI_IGNORED. (WARN_PSABI_EMPTY_CXX17_BASE): New constant. (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise. (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields whose DECL_FIELD_ABI_IGNORED bit is set when determining whether something actually is a HFA or HVA. Record whether we see a [[no_unique_address]] field that previous GCCs would not have ignored in this way. (aapcs_vfp_is_call_or_return_candidate): Update the calls to aapcs_vfp_sub_candidate and report a -Wpsabi warning for the [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the diagnostic messages. (arm_needs_doubleword_align): Add a comment explaining why we consider even zero-sized fields. 2020-04-29 Richard Biener Li Zekun PR lto/94822 * tree.c (component_ref_size): Guard against error_mark_node DECL_INITIAL as it happens with LTO. 2020-04-29 Richard Sandiford * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a comment explaining why we consider even zero-sized fields. (WARN_PSABI_EMPTY_CXX17_BASE): New constant. (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise. (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields whose DECL_FIELD_ABI_IGNORED bit is set when determining whether something actually is a HFA or HVA. Record whether we see a [[no_unique_address]] field that previous GCCs would not have ignored in this way. (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say whether diagnostics should be suppressed. Update the calls to aapcs_vfp_sub_candidate and report a -Wpsabi warning for the [[no_unique_address]] case. (aarch64_return_in_msb): Update call accordingly, never silencing diagnostics. (aarch64_function_value): Likewise. (aarch64_return_in_memory_1): Likewise. (aarch64_init_cumulative_args): Likewise. (aarch64_gimplify_va_arg_expr): Likewise. (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and use it to decide whether arch64_vfp_is_call_or_return_candidate should be silent. (aarch64_pass_by_reference): Update calls accordingly. (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument to decide whether arch64_vfp_is_call_or_return_candidate should be silent. 2020-04-29 Haijian Zhang PR target/94820 * config/aarch64/aarch64-builtins.c (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and new_fenv_var. 2020-04-29 Thomas Schwinge * configure.ac <$enable_offload_targets>: Do parsing as done elsewhere. * configure: Regenerate. * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'. * configure: Regenerate. PR target/94279 * rtlanal.c (set_noop_p): Handle non-constant selectors. PR target/94282 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New function. (TARGET_EXCEPT_UNWIND_INFO): Define. 2020-04-29 Jakub Jelinek PR target/94248 * config/gcn/gcn.md (*mov_insn): Use 'reg_overlap_mentioned_p' to check for overlap. PR target/94706 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED instead of cxx17_empty_base_field_p. PR target/94707 * tree-core.h (tree_decl_common): Note decl_flag_0 used for DECL_FIELD_ABI_IGNORED. * tree.h (DECL_FIELD_ABI_IGNORED): Define. * calls.h (cxx17_empty_base_field_p): Change into a temporary macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address" attribute. * calls.c (cxx17_empty_base_field_p): Remove. * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle DECL_FIELD_ABI_IGNORED. * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise. * lto-streamer-out.c (hash_tree): Likewise. * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename cxx17_empty_base_seen to empty_base_seen, change type to int *, adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of cxx17_empty_base_field_p, if "no_unique_address" attribute is present, propagate that to the caller too. (rs6000_discover_homogeneous_aggregate): Adjust rs6000_aggregate_candidate caller, emit different diagnostics when c++17 empty base fields are present and when empty [[no_unique_address]] fields are present. * config/rs6000/rs6000.c (rs6000_special_round_type_align, darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED fields. 2020-04-29 Richard Biener * tree-ssa-loop-im.c (ref_always_accessed::operator ()): Just check whether the stmt stores. 2020-04-28 Alexandre Oliva PR target/94812 * gcc/config/rs6000/rs6000.md (rs6000_mffsl): Copy result to output operand in emulation. Don't overwrite pseudos. 2020-04-28 Jeff Law * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific multiply patterns are 4 bytes long. 2020-04-28 Kyrylo Tkachov * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option. * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option. 2020-04-28 Matthew Malcomson Jakub Jelinek PR target/94711 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty base class artificial fields. (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI decision is different after this fix. 2020-04-28 David Malcolm PR analyzer/94447 PR analyzer/94639 PR analyzer/94732 PR analyzer/94754 * doc/invoke.texi (Static Analyzer Options): Remove -Wanalyzer-use-of-uninitialized-value. (-Wno-analyzer-use-of-uninitialized-value): Remove item. 2020-04-28 Jakub Jelinek PR tree-optimization/94809 * tree.c (build_call_expr_internal_loc_array): Call process_call_operands. 2020-04-27 Anton Youdkevitch * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define. (thunderx3t110_regmove_cost): Likewise. (thunderx3t110_vector_cost): Likewise. (thunderx3t110_prefetch_tune): Likewise. (thunderx3t110_tunings): Likewise. * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs): Define. * config/aarch64/thunderx3t110.md: New file. * config/aarch64/aarch64.md: Include thunderx3t110.md. * doc/invoke.texi (AArch64 options): Add thunderx3t110. 2020-04-28 Jakub Jelinek PR target/94704 * config/s390/s390.c (s390_function_arg_vector, s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed. 2020-04-28 Richard Sandiford PR tree-optimization/94727 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison operands are invariant booleans, use the mask type associated with the STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP. (vectorizable_condition): Pass vectype unconditionally to vect_is_simple_cond. 2020-04-27 Jakub Jelinek PR target/94780 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use TARGET_EXPR instead of MODIFY_EXPR for first assignment to sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var. 2020-04-27 David Malcolm PR 92830 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from default value, so that it can by supplied by get_option_html_page. * configure: Regenerate. * opts.c: Include "selftest.h". (get_option_html_page): New function. (get_option_url): Use it. Reformat to place comments next to the expressions they refer to. (selftest::test_get_option_html_page): New. (selftest::opts_c_tests): New. * selftest-run-tests.c (selftest::run_tests): Call selftest::opts_c_tests. * selftest.h (selftest::opts_c_tests): New decl. 2020-04-27 Richard Sandiford * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply UINTVAL to CONST_INTs. 2020-04-27 Srinath Parvathaneni * config/arm/constraints.md (e): Remove constraint. (Te): Define constraint. * config/arm/mve.md (vaddvq_): Modify constraint in operand 0 from "e" to "Te". (vaddvaq_): Likewise. (vaddvq_p_): Likewise. (vmladavq_): Likewise. (vmladavxq_s): Likewise. (vmlsdavq_s): Likewise. (vmlsdavxq_s): Likewise. (vaddvaq_p_): Likewise. (vmladavaq_): Likewise. (vmladavq_p_): Likewise. (vmladavxq_p_s): Likewise. (vmlsdavq_p_s): Likewise. (vmlsdavxq_p_s): Likewise. (vmlsdavaxq_s): Likewise. (vmlsdavaq_s): Likewise. (vmladavaxq_s): Likewise. (vmladavaq_p_): Likewise. (vmladavaxq_p_s): Likewise. (vmlsdavaq_p_s): Likewise. (vmlsdavaxq_p_s): Likewise. 2020-04-27 Andre Vieira * config/arm/arm.c (output_move_neon): Only get the first operand if addr is PLUS. 2020-04-27 Felix Yang PR tree-optimization/94784 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the assert around so that it checks that the two vectors have equal TYPE_VECTOR_SUBPARTS and that converting the corresponding element types is a useless_type_conversion_p. 2020-04-27 Szabolcs Nagy PR target/94515 * dwarf2cfi.c (struct GTY): Add ra_mangled. (cfi_row_equal_p): Check ra_mangled. (dwarf2out_frame_debug_cfa_window_save): Remove the argument, this only handles the sparc logic now. (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for the aarch64 specific logic. (dwarf2out_frame_debug): Update to use the new subroutines. (change_cfi_row): Check ra_mangled. 2020-04-27 Jakub Jelinek PR target/94704 * config/s390/s390.c (s390_function_arg_vector, s390_function_arg_float): Ignore cxx17_empty_base_field_p fields. 2020-04-27 Jiufu Guo * common/config/rs6000/rs6000-common.c (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off -fweb. * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to set flag_web. 2020-04-27 Martin Liska PR lto/94659 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p): Do not remove ifunc_resolvers in remove unreachable nodes in LTO. 2020-04-27 Xiong Hu Luo PR target/91518 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed): New variable. (rs6000_emit_prologue_components): Check with frame_pointer_needed_indeed. (rs6000_emit_epilogue_components): Likewise. (rs6000_emit_prologue): Likewise. (rs6000_emit_epilogue): Set frame_pointer_needed_indeed. 2020-04-25 David Edelsohn * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a stack frame when debugging and flag_compare_debug is enabled. 2020-04-25 Michael Meissner * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to enable PC-relative addressing for -mcpu=future. * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS. * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined, suppress PC-relative addressing. (rs6000_option_override_internal): Split up error messages checking for -mprefixed and -mpcrel. Enable -mpcrel if the target system supports it. 2020-04-25 Jakub Jelinek Richard Biener PR tree-optimization/94734 PR tree-optimization/89430 * tree-ssa-phiopt.c: Include tree-eh.h. (cond_store_replacement): Return false if an automatic variable access could trap. If -fstore-data-races, don't return false just because an automatic variable is addressable. 2020-04-24 Andrew Stubbs * config/gcn/gcn-valu.md (add_zext_dup2_exec): Fix merge of high-part. (add_sext_dup2_exec): Likewise. 2020-04-24 Segher Boessenkool PR target/94710 * config/rs6000/vector.md (vec_shr_ for VEC_L): Correct little endian byteshift_val calculation. 2020-04-24 Andrew Stubbs * config/gcn/gcn.md (*mov_insn): Only split post-reload. 2020-04-24 Richard Sandiford * config/aarch64/arm_sve.h: Add a comment. 2020-04-24 Haijian Zhang PR rtl-optimization/94708 * combine.c (simplify_if_then_else): Add check for !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode). 2020-04-23 Martin Sebor PR driver/90983 * common.opt (-Wno-frame-larger-than): New option. (-Wno-larger-than, -Wno-stack-usage): Same. 2020-04-23 Andrew Stubbs * config/gcn/gcn-valu.md (mov_exec): Swap the numbers on operands 2 and 3. (mov_exec): Likewise. (trunc2_exec): Swap parameters to gen_mov_exec. (2_exec): Likewise. 2019-04-23 Eric Botcazou PR tree-optimization/94717 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one of the stores doesn't have the same landing pad number as the first. (coalesce_immediate_stores): Do not try to coalesce the store using bswap if it doesn't have the same landing pad number as the first. 2020-04-23 Bill Schmidt * gcc/doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Replace outdated link to ELFv2 ABI. 2020-04-23 Jakub Jelinek PR target/94710 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx just return v2. PR middle-end/94724 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs temporarily with non-final second operand and updating it later, push COMPOUND_EXPRs into a vector and process it in reverse, creating COMPOUND_EXPRs with the final operands. 2020-04-23 Szabolcs Nagy PR target/94697 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap bti c and bti j handling. 2020-04-23 Andrew Stubbs Thomas Schwinge PR middle-end/93488 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on t_async and the wait arguments. 2020-04-23 Richard Sandiford PR tree-optimization/94727 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when comparing invariant scalar booleans. 2020-04-23 Matthew Malcomson Jakub Jelinek PR target/94383 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17 empty base class artificial fields. (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is different after this fix. 2020-04-23 Jakub Jelinek PR target/94707 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate): Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check if the same type has been diagnosed most recently already. 2020-04-23 Srinath Parvathaneni * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's datatype. (__arm_vbicq_n_s16): Likewise. (__arm_vbicq_n_u32): Likewise. (__arm_vbicq_n_s32): Likewise. (__arm_vbicq): Likewise. (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype. (__arm_vbicq_n_s32): Likewise. (__arm_vbicq_n_u16): Likewise. (__arm_vbicq_n_u32): Likewise. (__arm_vdupq_m_n_s8): Likewise. (__arm_vdupq_m_n_s16): Likewise. (__arm_vdupq_m_n_s32): Likewise. (__arm_vdupq_m_n_u8): Likewise. (__arm_vdupq_m_n_u16): Likewise. (__arm_vdupq_m_n_u32): Likewise. (__arm_vdupq_m_n_f16): Likewise. (__arm_vdupq_m_n_f32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_f16): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_f16): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_f16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise. (__arm_vldrwq_gather_offset_s32): Likewise. (__arm_vldrwq_gather_offset_u32): Likewise. (__arm_vldrwq_gather_offset_f32): Likewise. (__arm_vldrwq_gather_offset_z_s32): Likewise. (__arm_vldrwq_gather_offset_z_u32): Likewise. (__arm_vldrwq_gather_offset_z_f32): Likewise. (__arm_vldrwq_gather_shifted_offset_s32): Likewise. (__arm_vldrwq_gather_shifted_offset_u32): Likewise. (__arm_vldrwq_gather_shifted_offset_f32): Likewise. (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise. (__arm_vdwdupq_x_n_u8): Likewise. (__arm_vdwdupq_x_n_u16): Likewise. (__arm_vdwdupq_x_n_u32): Likewise. (__arm_viwdupq_x_n_u8): Likewise. (__arm_viwdupq_x_n_u16): Likewise. (__arm_viwdupq_x_n_u32): Likewise. (__arm_vidupq_x_n_u8): Likewise. (__arm_vddupq_x_n_u8): Likewise. (__arm_vidupq_x_n_u16): Likewise. (__arm_vddupq_x_n_u16): Likewise. (__arm_vidupq_x_n_u32): Likewise. (__arm_vddupq_x_n_u32): Likewise. (__arm_vldrdq_gather_offset_s64): Likewise. (__arm_vldrdq_gather_offset_u64): Likewise. (__arm_vldrdq_gather_offset_z_s64): Likewise. (__arm_vldrdq_gather_offset_z_u64): Likewise. (__arm_vldrdq_gather_shifted_offset_s64): Likewise. (__arm_vldrdq_gather_shifted_offset_u64): Likewise. (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise. (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise. (__arm_vidupq_m_n_u8): Likewise. (__arm_vidupq_m_n_u16): Likewise. (__arm_vidupq_m_n_u32): Likewise. (__arm_vddupq_m_n_u8): Likewise. (__arm_vddupq_m_n_u16): Likewise. (__arm_vddupq_m_n_u32): Likewise. (__arm_vidupq_n_u16): Likewise. (__arm_vidupq_n_u32): Likewise. (__arm_vidupq_n_u8): Likewise. (__arm_vddupq_n_u16): Likewise. (__arm_vddupq_n_u32): Likewise. (__arm_vddupq_n_u8): Likewise. 2020-04-23 Iain Buclaw * doc/install.texi (D-Specific Options): Document --enable-libphobos-checking and --with-libphobos-druntime-only. 2020-04-23 Jakub Jelinek PR target/94707 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add cxx17_empty_base_seen argument. Pass it to recursive calls. Ignore cxx17_empty_base_field_p fields after setting *cxx17_empty_base_seen to true. (rs6000_discover_homogeneous_aggregate): Adjust rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous aggregates with C++17 empty base fields. PR c/94705 * attribs.c (decl_attribute): Don't diagnose attribute exclusions if last_decl is error_mark_node or has such a TREE_TYPE. PR c/94705 * attribs.c (decl_attribute): Don't diagnose attribute exclusions if last_decl is error_mark_node or has such a TREE_TYPE. 2020-04-22 Felix Yang PR target/94678 * config/aarch64/aarch64.h (TARGET_SVE): Add && !TARGET_GENERAL_REGS_ONLY. (TARGET_SVE2): Add && TARGET_SVE. (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3, TARGET_SVE2_SM4): Add && TARGET_SVE2. * config/aarch64/aarch64-sve-builtins.h (sve_switcher::m_old_general_regs_only): New member. * config/aarch64/aarch64-sve-builtins.cc (check_required_registers): New function. (reported_missing_registers_p): New variable. (check_required_extensions): Call check_required_registers before return if all required extenstions are present. (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in global_options.x_target_flags. (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in global_options.x_target_flags if m_old_general_regs_only is true. 2020-04-22 Zackery Spytz * doc/extend.exi: Add "free" to list of other builtin functions supported by GCC. 2020-04-20 Aaron Sawdey PR target/94622 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed" if TARGET_PREFIXED. (store_quadpti): Ditto. (atomic_load): Do not swap doublewords if TARGET_PREFIXED as plq will be used and doesn't need it. (atomic_store): Ditto, for pstq. 2020-04-22 Erick Ochoa * doc/invoke.texi: Update flags turned on by -O3. 2020-04-22 Jakub Jelinek PR target/94706 * config/ia64/ia64.c (hfa_element_mode): Ignore cxx17_empty_base_field_p fields. PR target/94383 * calls.h (cxx17_empty_base_field_p): Declare. * calls.c (cxx17_empty_base_field_p): Define. 2020-04-22 Christophe Lyon * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document. 2020-04-22 Kyrylo Tkachov Andre Vieira Mihail Ionescu * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu. * config/arm/arm-cpus.in (quirk_no_asmcpu): Define. (ALL_QUIRKS): Add quirk_no_asmcpu. (cortex-m55): Define new cpu. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55. 2020-04-22 Richard Sandiford PR tree-optimization/94700 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures of similarly-structured but distinct vector types. 2020-04-21 Martin Sebor PR middle-end/94647 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct the computation of the lower bound of the source access size. (builtin_access::generic_overlap): Remove a hack for setting ranges of overlap offsets. 2020-04-21 John David Anglin * config/pa/som.h (ASM_WEAKEN_LABEL): Delete. (ASM_WEAKEN_DECL): New define. (HAVE_GAS_WEAKREF): Undefine. 2020-04-21 Richard Sandiford PR tree-optimization/94683 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a VIEW_CONVERT_EXPR to handle mixtures of similarly-structured but distinct vector types. 2020-04-21 Jakub Jelinek PR c/94641 * stor-layout.c (place_field, finalize_record_size): Don't emit -Wpadded warning on TYPE_ARTIFICIAL rli->t. * ubsan.c (ubsan_get_type_descriptor_type, ubsan_get_source_location_type, ubsan_create_data): Set TYPE_ARTIFICIAL. * asan.c (asan_global_struct): Likewise. 2020-04-21 Duan bo PR target/94577 * config/aarch64/aarch64.c: Add an error message for option conflict. * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is incompatible with -fpic, -fPIC and -mabi=ilp32. 2020-04-21 Frederik Harwath PR other/94629 * omp-low.c (new_omp_context): Remove assignments to ctx->outer_reduction_clauses and ctx->local_reduction_clauses. 2020-04-20 Andreas Krebbel * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx") ("popcountv2di2_vx"): Use simplify_gen_subreg. 2020-04-20 Andreas Krebbel PR target/94613 * config/s390/s390-builtin-types.def: Add 3 new function modes. * config/s390/s390-builtins.def: Add mode dependent low-level builtin and map the overloaded builtins to these. * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ... ("vsel * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo has a variable VF, prefer new_loop_vinfo if it is cheaper for the estimated VF and is no worse at double the estimated VF. 2020-04-20 Richard Sandiford PR target/94668 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix order of arguments to rtx_vector_builder. (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise. When extending the trailing constants to a full vector, replace any variables with zeros. 2020-04-20 Jan Hubicka PR ipa/94582 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local flag. 2020-04-20 Martin Liska * symtab.c (symtab_node::dump_references): Add space after one entry. (symtab_node::dump_referring): Likewise. 2020-04-18 Jeff Law PR debug/94439 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking the chain. 2020-04-18 Iain Buclaw * doc/sourcebuild.texi (Effective-Target Keywords, Environment attributes): Document d_runtime_has_std_library. 2020-04-17 Jeff Law PR rtl-optimization/90275 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels when the destination has a REG_UNUSED note. 2020-04-17 Tobias Burnus PR middle-end/94635 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to MAP_DELETE. 2020-04-17 Richard Sandiford * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function. (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the cost of load and store insns if one loop iteration has enough scalar elements to use an Advanced SIMD LDP or STP. (aarch64_add_stmt_cost): Update call accordingly. 2020-04-17 Jakub Jelinek Jeff Law PR target/94567 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than CCNOmode in ix86_match_ccmode if len is equal to mode precision, or pos + len >= 32, or pos + len is equal to operands[2] precision and operands[2] is not a register operand. During splitting perform SImode AND if operands[0] doesn't have CCZmode and pos + len is equal to mode precision. 2020-04-17 Richard Biener PR other/94629 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate initialization. * dwarf2out.c (dw_val_equal_p): Fix pasto in dw_val_class_vms_delta comparison. * optabs.c (expand_binop_directly): Fix pasto in commutation check. * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in initialization. 2020-04-17 Jakub Jelinek PR rtl-optimization/94618 * cfgrtl.c (delete_insn_and_edges): Set purge not just when insn is the BB_END of its block, but also when it is only followed by DEBUG_INSNs in its block. PR tree-optimization/94621 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN. Move id->adjust_array_error_bounds check first in the condition. 2020-04-17 Martin Liska Jonathan Yong <10walls@gmail.com> PR gcov-profile/94570 * coverage.c (coverage_init): Use separator properly. 2020-04-16 Peter Bergner PR rtl-optimization/93974 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define. (rs6000_cannot_substitute_mem_equiv_p): New function. 2020-04-16 Martin Jambor PR ipa/93621 * ipa-inline.h (ipa_saved_clone_sources): Declare. * ipa-inline-transform.c (ipa_saved_clone_sources): New variable. (save_inline_function_body): Link the new body holder with the previous one. * cgraph.c: Include ipa-inline.h. (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from the statement in ipa_saved_clone_sources. * cgraphunit.c: Include ipa-inline.h. (expand_all_functions): Free ipa_saved_clone_sources. 2020-04-16 Richard Sandiford PR target/94606 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take the VNx16BI lowpart of the recursively-generated constant. 2020-04-16 Martin Liska Jakub Jelinek PR c++/94314 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop DECL_IS_REPLACEABLE_OPERATOR during cloning. * tree-ssa-dce.c (valid_new_delete_pair_p): New function. (propagate_necessity): Check operator names. 2020-04-16 Richard Sandiford PR rtl-optimization/94605 * early-remat.c (early_remat::process_block): Handle insns that set multiple candidate registers. 2020-04-16 Jan Hubicka PR gcov-profile/93401 * common.opt (profile-prefix-path): New option. * coverae.c: Include diagnostics.h. (coverage_init): Strip profile prefix path. * doc/invoke.texi (-fprofile-prefix-path): Document. 2020-04-16 Richard Biener PR middle-end/94614 * expr.c (emit_move_multi_word): Do not generate code when the destination part is undefined_operand_subword_p. * lower-subreg.c (resolve_clobber): Look through a paradoxica subreg. 2020-04-16 Martin Jambor PR tree-optimization/94598 * tree-sra.c (verify_sra_access_forest): Fix verification of total scalarization accesses under access to one-element arrays. 2020-04-16 Jakub Jelinek PR bootstrap/89494 * function.c (assign_parm_find_data_types): Add workaround for BROKEN_VALUE_INITIALIZATION compilers. 2020-04-16 Richard Biener * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME nodes. 2020-04-15 Uroš Bizjak PR target/94603 * config/i386/i386-builtin.def (__builtin_ia32_movq128): Require OPTION_MASK_ISA_SSE2. 2020-04-15 Gustavo Romero PR bootstrap/89494 * dumpfile.c (selftest::temp_dump_context::temp_dump_context): Don't construct a dump_context temporary to call static method. 2020-04-15 Andrea Corallo * config/aarch64/falkor-tag-collision-avoidance.c (valid_src_p): Check for aarch64_address_info type before accessing base field. 2020-04-15 Andre Vieira * config/arm/mve.md (mve_vec_duplicate): New pattern. (V_sz_elem2): Remove unused mode attribute. 2020-04-15 Matthew Malcomson * config/arm/arm.md (arm_movdi): Disallow for MVE. 2020-04-15 Richard Biener PR middle-end/94539 * tree-ssa-alias.c (same_type_for_tbaa): Defer to alias_sets_conflict_p for pointers. 2020-04-14 Max Filippov PR target/94584 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2) (extendhisi2_internal): Add %v1 before the load instructions. 2020-04-14 Aaron Sawdey PR target/94542 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to use PC-relative addressing for TLS references. 2020-04-14 Martin Jambor PR ipa/94434 * ipa-sra.c: Include internal-fn.h. (enum isra_scan_context): Update comment. (scan_function): Treat calls to internal_functions like loads or stores. 2020-04-14 Yang Yang PR tree-optimization/94574 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing whether a vector-insert is rewritable using a BIT_INSERT_EXPR. 2020-04-14 H.J. Lu PR target/94561 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check. 2020-04-13 Martin Sebor * doc/extend.texi (-Wall): Mention -Wformat-overflow and -Wformat-truncation. Move -Wzero-length-bounds last. (-Wrestrict): Document positive form of option enabled by -Wall. 2020-04-13 Zachary Spytz * doc/extend.texi: Add realloc to list of built-in functions are recognized by the compiler. 2020-04-13 H.J. Lu PR target/94556 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame pointer in word_mode for eh_return epilogues. 2020-04-13 Jozef Lawrynowicz * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to memory references in %B, %C and %D operand selectors when the inner operand is a post increment address. 2020-04-13 Jozef Lawrynowicz * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory reference by 4 bytes, and %D memory reference by 6 bytes. 2020-04-11 Uroš Bizjak PR target/94494 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2 condition for V4SI, V8HI and V16QI modes. 2020-04-11 Jakub Jelinek PR debug/94495 PR target/94551 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on val->val_rtx. 2020-04-10 Thomas Schwinge PR middle-end/89433 PR middle-end/93465 * omp-general.c (oacc_verify_routine_clauses): Diagnose if "#pragma omp declare target" has also been applied. 2020-04-09 Jozef Lawrynowicz * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn when to emit the epilogue_helper insn. * config/msp430/msp430.md (epilogue_helper): Add a return insn to the RTL pattern. 2020-04-09 Jakub Jelinek PR debug/94495 * cselib.h (cselib_record_sp_cfa_base_equiv, cselib_sp_derived_value_p): Declare. * cselib.c (cselib_record_sp_cfa_base_equiv, cselib_sp_derived_value_p): New functions. * var-tracking.c (add_stores): Don't record MO_VAL_SET for cselib_sp_derived_value_p values. (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the start of extended basic blocks other than the first one for !frame_pointer_needed functions. 2020-04-09 Richard Sandiford * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw) (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw) (aarch64_sve2048_hw): Document. * config/aarch64/aarch64-protos.h (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled. * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New function. (find_type_suffix_for_scalar_type): Use it instead of comparing TYPE_MAIN_VARIANTs. (function_resolver::infer_vector_or_tuple_type): Likewise. (function_resolver::require_vector_type): Likewise. (handle_arm_sve_vector_bits_attribute): New function. * config/aarch64/aarch64.c (pure_scalable_type_info): New class. (aarch64_attribute_table): Add arm_sve_vector_bits. (aarch64_return_in_memory_1): (pure_scalable_type_info::piece::get_rtx): New function. (pure_scalable_type_info::num_zr): Likewise. (pure_scalable_type_info::num_pr): Likewise. (pure_scalable_type_info::get_rtx): Likewise. (pure_scalable_type_info::analyze): Likewise. (pure_scalable_type_info::analyze_registers): Likewise. (pure_scalable_type_info::analyze_array): Likewise. (pure_scalable_type_info::analyze_record): Likewise. (pure_scalable_type_info::add_piece): Likewise. (aarch64_some_values_include_pst_objects_p): Likewise. (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info to analyze whether the type is returned in SVE registers. (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type is passed in SVE registers. (aarch64_pass_by_reference_1): New function, extracted from... (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info to analyze whether the type is a pure scalable type and, if so, whether it should be passed by reference. (aarch64_return_in_msb): Return false for pure scalable types. (aarch64_function_value_1): Fold back into... (aarch64_function_value): ...this function. Use pure_scalable_type_info to analyze whether the type is a pure scalable type and, if so, which registers it should use. Handle types that include pure scalable types but are not themselves pure scalable types. (aarch64_return_in_memory_1): New function, split out from... (aarch64_return_in_memory): ...here. Use pure_scalable_type_info to analyze whether the type is a pure scalable type and, if so, whether it should be returned by reference. (aarch64_layout_arg): Remove orig_mode argument. Use pure_scalable_type_info to analyze whether the type is a pure scalable type and, if so, which registers it should use. Handle types that include pure scalable types but are not themselves pure scalable types. (aarch64_function_arg): Update call accordingly. (aarch64_function_arg_advance): Likewise. (aarch64_pad_reg_upward): On big-endian targets, return false for pure scalable types that are smaller than 16 bytes. (aarch64_member_type_forces_blk): New function. (aapcs_vfp_sub_candidate): Exit early for built-in SVE types. (aarch64_short_vector_p): Return false for VECTOR_TYPEs that correspond to built-in SVE types. Do not rely on a vector mode if the type includes an pure scalable type. When returning true, assert that the mode is not an SVE mode. (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE built-in types here. When returning true, assert that the type does not have an SVE mode. (aarch64_can_change_mode_class): Don't allow anything to change between a predicate mode and a non-predicate mode. Also don't allow changes between SVE vector modes and other modes that might be bigger than 128 bits. (aarch64_invalid_binary_op): Reject binary operations that mix SVE and GNU vector types. (TARGET_MEMBER_TYPE_FORCES_BLK): Define. 2020-04-09 Richard Sandiford * config/aarch64/aarch64.c (aarch64_attribute_table): Add "SVE sizeless type". * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless) (sizeless_type_p): New functions. (register_builtin_types): Apply make_type_sizeless to the type. (register_tuple_type): Likewise. (verify_type_context): Use sizeless_type_p instead of builin_type_p. 2020-04-09 Matthew Malcomson * config/arm/arm_cde.h: Remove `extern "C"` when compiling for C++. 2020-04-09 Martin Jambor Richard Biener PR tree-optimization/94482 * tree-sra.c (create_access_replacement): Dump new replacement with TDF_UID. (sra_modify_expr): Fix handling of cases when the original EXPR writes to only part of the replacement. * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify the first operand of combinations into REAL/IMAGPART_EXPR and BIT_FIELD_REF. 2020-04-09 Richard Sandiford * doc/sourcebuild.texi (check-function-bodies): Treat the third parameter as a list of option regexps and require each regexp to match. 2020-04-09 Andrea Corallo PR target/94530 * config/aarch64/falkor-tag-collision-avoidance.c (valid_src_p): Fix missing rtx type check. 2020-04-09 Bin Cheng Richard Biener PR tree-optimization/93674 * tree-ssa-loop-ivopts.c (langhooks.h): New include. (add_iv_candidate_for_use): For iv_use of non integer or pointer type, or non-mode precision type, add candidate in unsigned type with the same precision. 2020-04-08 Clement Chigot * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128. * config/rs6000/aix71.h (LIB_SPEC): Likewise. * config/rs6000/aix72.h (LIB_SPEC): Likewise. 2020-04-08 Jakub Jelinek PR middle-end/94526 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P with zero offset. * reload1.c (eliminate_regs_1): Avoid creating (plus (reg) (const_int 0)) in DEBUG_INSNs. PR tree-optimization/94524 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is negative for signed TRUNC_MOD_EXPR, multiply with absolute value of op1 rather than op1 itself at the end. Punt for signed modulo by most negative constant. * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed modulo by most negative constant. 2020-04-08 Richard Biener PR rtl-optimization/93946 * cse.c (cse_insn): Record the tabled expression in src_related. Verify a redundant store removal is valid. 2020-04-08 H.J. Lu PR target/94417 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert ENDBR at function entry if function will be called indirectly. 2020-04-08 Jakub Jelinek PR target/94438 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size 1, 2, 4 and 8. 2020-04-08 Martin Liska PR c++/94314 * gimple.c (gimple_call_operator_delete_p): Rename to... (gimple_call_replaceable_operator_delete_p): ... this. Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P. * gimple.h (gimple_call_operator_delete_p): Rename to ... (gimple_call_replaceable_operator_delete_p): ... this. * tree-core.h (tree_function_decl): Add replaceable_operator flag. * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1): Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P. (propagate_necessity): Use gimple_call_replaceable_operator_delete_p. (eliminate_unnecessary_stmts): Likewise. * tree-streamer-in.c (unpack_ts_function_decl_value_fields): Pack DECL_IS_REPLACEABLE_OPERATOR. * tree-streamer-out.c (pack_ts_function_decl_value_fields): Unpack the field here. * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New. (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New. (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New. * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable. * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare replaceable operator flags. 2020-04-08 Dennis Zhang Matthew Malcomson * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro. (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise. (CX_TERNARY_QUALIFIERS): Likewise. (ARM_BUILTIN_CDE_PATTERN_START): Likewise. (ARM_BUILTIN_CDE_PATTERN_END): Likewise. (arm_init_acle_builtins): Initialize CDE builtins. (arm_expand_acle_builtin): Check CDE constant operands. * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range of CDE constant operand. * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for TARGET_VFP_BASE. (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise. * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface. (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise. (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise. (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise. (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise. * config/arm/arm_cde_builtins.def: New file. * config/arm/iterators.md (V_reg): New attribute of SI. * config/arm/predicates.md (const_int_coproc_operand): New. (const_int_vcde1_operand, const_int_vcde2_operand): New. (const_int_vcde3_operand): New. * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New. * config/arm/vfp.md (arm_vcx1): New entry. (arm_vcx1a, arm_vcx2, arm_vcx2a): Likewise. (arm_vcx3, arm_vcx3a): Likewise. 2020-04-08 Dennis Zhang * config.gcc: Add arm_cde.h. * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC. * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options. * config/arm/arm.c (arm_option_reconfigure_globals): Configure arm_arch_cde and arm_arch_cde_coproc to store the feature bits. * config/arm/arm.h (TARGET_CDE): New macro. * config/arm/arm_cde.h: New file. * doc/invoke.texi: Document CDE options +cdecp[0-7]. * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target supports option. (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise. 2020-04-08 Jakub Jelinek PR rtl-optimization/94516 * postreload.c: Include rtl-iter.h. (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR looking for all MEMs with RTX_AUTOINC operand. (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling. 2020-04-08 Tobias Burnus * omp-grid.c (grid_eliminate_combined_simd_part): Use OMP_CLAUSE_CODE to access the omp clause code. 2020-04-07 Jeff Law PR rtl-optimization/92264 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when the destination is the stack pointer. 2020-04-07 Jakub Jelinek PR rtl-optimization/94291 PR rtl-optimization/84169 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST must be a REG or SUBREG of REG; if it is not one of these, don't update LOG_LINKs. 2020-04-07 Richard Biener PR middle-end/94479 * gimplify.c (gimplify_addr_expr): Also consider generated MEM_REFs. 2020-04-07 Andre Vieira * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs. 2020-04-07 Andre Vieira * config/arm/arm_mve.h: Cast some pointers to expected types. 2020-04-07 Andre Vieira * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the same with '__arm_' prefix. 2020-04-07 Andre Vieira * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set. 2020-04-07 Andre Vieira * config/arm/arm.c (arm_mve_immediate_check): Removed. * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types. (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*, mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*, mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*, mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*, mve_vqshruntq_m_n_s*): Fixed immediate constraints. 2020-04-07 Andre Vieira * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts. 2020-04-07 Andre Vieira * config/arm/arm_mve.h: Fix v[id]wdup intrinsics. * config/arm/mve/md: Fix v[id]wdup patterns. 2020-04-07 Andre Vieira * config/arm/arm.c (output_move_neon): Deal with label + offset cases. * config/arm/mve.md (*mve_mov): Handle const vectors. 2020-04-07 Andre Vieira * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters and remove const_ptr enums. 2020-04-07 Andre Vieira * config/arm/arm_mve.h (vsubq_n): Merge with... (vsubq): ... this. (vmulq_n): Merge with... (vmulq): ... this. (__ARM_mve_typeid): Simplify scalar and constant detection. 2020-04-07 Jakub Jelinek PR target/94509 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check for inter-lane permutation for 64-byte modes. PR target/94488 * config/aarch64/aarch64-simd.md (ashl3, lshr3, ashr3): Force operands[2] into reg whenever it is not CONST_INT. Assume it is a REG after that instead of testing it and doing FAIL otherwise. Formatting fix. 2020-04-07 Sebastian Huber * config/rs6000/t-rtems: Delete mcpu=8540 multilib. 2020-04-07 Jakub Jelinek PR target/94500 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes. 2020-04-06 Jakub Jelinek * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P + const0_rtx return the SP_DERIVED_VALUE_P. 2020-04-06 Richard Sandiford PR rtl-optimization/92989 * lra-lives.c (process_bb_lives): Do not treat eh_return data registers as being live at the beginning of the EH receiver. 2020-04-05 Zachary Spytz * extend.texi: Add free to list of ISO C90 functions that are recognized by the compiler. 2020-04-05 Nagaraju Mekala * config/microblaze/microblaze.c (microblaze_must_save_register): Check for fast_interrupt. * config/microblaze/microblaze.md (trap): Update output pattern. 2020-04-04 Hannes Domani Jakub Jelinek PR debug/94459 * dwarf2out.c (gen_subprogram_die): Look through references, pointers, arrays, pointer-to-members, function types and qualifiers when checking if in-class DIE had an 'auto' or 'decltype(auto)' return type to emit type again on definition. 2020-04-04 Jan Hubicka PR ipa/93940 * ipa-fnsummary.c (vrp_will_run_p): New function. (fre_will_run_p): New function. (evaluate_properties_for_edge): Use it. * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline !optimize_debug to optimize_debug. 2020-04-04 Jakub Jelinek PR rtl-optimization/94468 * cselib.c (references_value_p): Formatting fix. (cselib_useless_value_p): New function. (discard_useless_locs, discard_useless_values, cselib_invalidate_regno_val, cselib_invalidate_mem, cselib_record_set): Use it instead of v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx). PR debug/94441 * tree-iterator.h (expr_single): Declare. * tree-iterator.c (expr_single): New function. * tree.h (protected_set_expr_location_if_unset): Declare. * tree.c (protected_set_expr_location): Use expr_single. (protected_set_expr_location_if_unset): New function. 2020-04-03 Jeff Law PR rtl-optimization/92264 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle reloading of auto-increment addressing modes. 2020-04-03 H.J. Lu PR target/94467 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand as earlyclobber. 2020-04-03 Jeff Law PR rtl-optimization/92264 * config/m32r/m32r.c (m32r_output_block_move): Properly account for post-increment addressing of source operands as well as residuals when computing any adjustments to the input pointer. 2020-04-03 Jakub Jelinek PR target/94460 * config/i386/sse.md (avx2_phwv16hi3, avx2_phdv8si3): Fix up RTL pattern to do second half of first lane from first lane of second operand and first half of second lane from second lane of first operand. 2020-04-03 Andre Vieira * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE. 2020-04-03 Tamar Christina PR target/94396 * common/config/aarch64/aarch64-common.c (aarch64_get_extension_string_for_isa_flags): Handle default flags. 2020-04-03 Richard Biener PR middle-end/94465 * tree.c (array_ref_low_bound): Deal with released SSA names in index position. 2020-04-03 Kwok Cheung Yeung * config/gcn/gcn.c (print_operand): Handle unordered comparison operators. * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered comparison operators. 2020-04-03 Kewen Lin PR tree-optimization/94443 * tree-vect-loop.c (vectorizable_live_operation): Use gsi_insert_seq_before to replace gsi_insert_before. 2020-04-03 Martin Liska PR ipa/94445 * ipa-icf-gimple.c (func_checker::compare_gimple_call): Compare type attributes for gimple_call_fntypes. 2020-04-02 Sandra Loosemore * alias.c (get_alias_set): Fix comment typos. 2020-04-02 Fritz Reese PR fortran/85982 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into attribute checking used by TYPE. 2020-04-02 Martin Jambor PR ipa/92676 * ipa-sra.c (struct caller_issues): New fields candidate and call_from_outside_comdat. (check_for_caller_issues): Check for calls from outsied of candidate's same_comdat_group. (check_all_callers_for_issues): Set up issues.candidate, check result of the new check. (mark_callers_calls_comdat_local): New function. (process_isra_node_results): Set calls_comdat_local of callers if appropriate. 2020-04-02 Richard Biener PR c/94392 * common.opt (ffinite-loops): Initialize to zero. * opts.c (default_options_table): Remove OPT_ffinite_loops entry. * cfgloop.h (loop::finite_p): New member. * cfgloopmanip.c (copy_loop_info): Copy finite_p. * ipa-icf-gimple.c (func_checker::compare_loops): Compare finite_p. * lto-streamer-in.c (input_cfg): Stream finite_p. * lto-streamer-out.c (output_cfg): Likewise. * tree-cfg.c (replace_loop_annotate): Initialize finite_p from flag_finite_loops at CFG build time. * tree-ssa-loop-niter.c (finite_loop_p): Check the loops finite_p flag instead of flag_finite_loops. * doc/invoke.texi (ffinite-loops): Adjust documentation of default setting. 2020-04-02 Richard Biener PR debug/94450 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting DW_TAG_imported_unit. 2020-04-02 Maciej W. Rozycki * doc/install.texi (Specific) : Update binutils requirement to 2.30. 2020-04-02 Kewen Lin PR tree-optimization/94401 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE access type when loading halves of vector to avoid peeling for gaps. 2020-04-02 Jakub Jelinek * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in between a string literal and MIPS_SYSVERSION_SPEC macro. 2020-04-02 Martin Jambor * doc/invoke.texi (Optimize Options): Document sra-max-propagations. 2020-04-02 Jakub Jelinek PR rtl-optimization/92264 * params.opt (-param=max-find-base-term-values=): Decrease default from 2000 to 200. PR rtl-optimization/92264 * rtl.h (struct rtx_def): Mention that call bit is used as SP_DERIVED_VALUE_P in cselib.c. * cselib.c (SP_DERIVED_VALUE_P): Define. (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier. (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P val_rtx and sp based expression where offsets cancel each other. (preserve_constants_and_equivs): Formatting fix. (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P locs list for cfa_base_preserved_val if needed. Formatting fix. (autoinc_split): If the to be returned value is a REG, MEM or VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off. (rtx_equal_for_cselib_1): Call autoinc_split even if both expressions are PLUS in Pmode with CONST_INT second operands. Handle SP_DERIVED_VALUE_P cases. (cselib_hash_plus_const_int): New function. (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT second operand, as well as for PRE_DEC etc. that ought to be hashed the same way. (cselib_subst_to_values): Substitute PLUS with Pmode and CONST_INT operand if the first operand is a VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the SP_DERIVED_VALUE_P + adjusted offset. (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx, set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location. * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv on the sp value before calling cselib_add_permanent_equiv on the cfa_base value. * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC in the insn without REG_INC note. (replace_read): Punt on RTX_AUTOINC in the *loc being replaced. Punt on invalid insns added by copy_to_mode_reg. Formatting fixes. PR target/94435 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode. 2020-04-02 Srinath Parvathaneni PR target/94317 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define. (LDRGBWBXU_Z_QUALIFIERS): Likewise. * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify intrinsic defintion by adding a new builtin call to writeback into base address. (__arm_vldrdq_gather_base_wb_u64): Likewise. (__arm_vldrdq_gather_base_wb_z_s64): Likewise. (__arm_vldrdq_gather_base_wb_z_u64): Likewise. (__arm_vldrwq_gather_base_wb_s32): Likewise. (__arm_vldrwq_gather_base_wb_u32): Likewise. (__arm_vldrwq_gather_base_wb_z_s32): Likewise. (__arm_vldrwq_gather_base_wb_z_u32): Likewise. (__arm_vldrwq_gather_base_wb_f32): Likewise. (__arm_vldrwq_gather_base_wb_z_f32): Likewise. * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify builtin's qualifier. (vldrdq_gather_base_wb_z_u): Likewise. (vldrwq_gather_base_wb_u): Likewise. (vldrdq_gather_base_wb_u): Likewise. (vldrwq_gather_base_wb_z_s): Likewise. (vldrwq_gather_base_wb_z_f): Likewise. (vldrdq_gather_base_wb_z_s): Likewise. (vldrwq_gather_base_wb_s): Likewise. (vldrwq_gather_base_wb_f): Likewise. (vldrdq_gather_base_wb_s): Likewise. (vldrwq_gather_base_nowb_z_u): Define builtin. (vldrdq_gather_base_nowb_z_u): Likewise. (vldrwq_gather_base_nowb_u): Likewise. (vldrdq_gather_base_nowb_u): Likewise. (vldrwq_gather_base_nowb_z_s): Likewise. (vldrwq_gather_base_nowb_z_f): Likewise. (vldrdq_gather_base_nowb_z_s): Likewise. (vldrwq_gather_base_nowb_s): Likewise. (vldrwq_gather_base_nowb_f): Likewise. (vldrdq_gather_base_nowb_s): Likewise. * config/arm/mve.md (mve_vldrwq_gather_base_nowb_v4si): Define RTL pattern. (mve_vldrwq_gather_base_wb_v4si): Modify RTL pattern. (mve_vldrwq_gather_base_nowb_z_v4si): Define RTL pattern. (mve_vldrwq_gather_base_wb_z_v4si): Modify RTL pattern. (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern. (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern. (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern. (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern. (mve_vldrdq_gather_base_nowb_v4di): Define RTL pattern. (mve_vldrdq_gather_base_wb_v4di): Modify RTL pattern. (mve_vldrdq_gather_base_nowb_z_v4di): Define RTL pattern. (mve_vldrdq_gather_base_wb_z_v4di): Modify RTL pattern. 2020-04-02 Andreas Krebbel * config/s390/vector.md ("add3", "mul3") ("and3", "notand3", "ior3", "ior_not3") ("xor3", "notxor3", "smin3", "smax3") ("umin3", "umax3", "vec_widen_smult_even_") ("vec_widen_umult_even_", "vec_widen_smult_odd_") ("vec_widen_umult_odd_", "add3", "sub3") ("mul3", "fma4", "fms4", "neg_fma4") ("neg_fms4", "*smax3_vxe", "*smaxv2df3_vx") ("*smin3_vxe", "*sminv2df3_vx"): Remove % constraint modifier. ("vec_widen_umult_lo_", "vec_widen_umult_hi_") ("vec_widen_smult_lo_", "vec_widen_smult_hi_"): Remove constraints from expander. * config/s390/vx-builtins.md ("vacc_", "vacq") ("vacccq", "vec_avg", "vec_avgu", "vec_vmal") ("vec_vmah", "vec_vmalh", "vec_vmae") ("vec_vmale", "vec_vmao", "vec_vmalo") ("vec_smulh", "vec_umulh", "vec_nor3") ("vfmin", "vfmax"): Remove % constraint modifier. 2020-04-01 Peter Bergner PR rtl-optimization/94123 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for flag_split_wide_types_early. 2020-04-01 Joerg Sonnenberger * doc/extend.texi (Common Function Attributes): Fix typo. 2020-04-01 Segher Boessenkool PR target/94420 * config/rs6000/rs6000.md (*tocref for P): Add insn condition on operands[1]. 2020-04-01 Zackery Spytz * doc/extend.texi: Fix a typo in the documentation of the copy function attribute. 2020-04-01 Jakub Jelinek PR middle-end/94423 * tree-object-size.c (pass_object_sizes::execute): Don't call replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead call replace_call_with_value. 2020-04-01 Kewen Lin PR tree-optimization/94043 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed phi for vec_lhs and use it for lane extraction. 2020-03-31 Felix Yang PR tree-optimization/94398 * tree-vect-stmts.c (vectorizable_store): Instead of calling vect_supportable_dr_alignment, set alignment_support_scheme to dr_unaligned_supported for gather-scatter accesses. (vectorizable_load): Likewise. 2020-03-31 Andrew Stubbs * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF): New mode iterators. (vnsi, VnSI, vndi, VnDI): New mode attributes. (mov): Use in place of V64DI. (mov_exec): Likewise. (mov_sgprbase): Likewise. (reload_out): Likewise. (*vec_set_1): Use GET_MODE_NUNITS instead of constant 64. (gather_loadv64si): Rename to ... (gather_load): ... this, and use in place of V64SI, and in place of V64DI. (gather_insn_1offset): Use in place of V64DI. (gather_insn_1offset_ds): Use in place of V64SI. (gather_insn_2offsets): Use and . (scatter_storev64si): Rename to ... (scatter_store): ... this, and use and . (scatter_expr): Use and . (scatter_insn_1offset): Likewise. (scatter_insn_1offset_ds): Likewise. (scatter_insn_2offsets): Likewise. (ds_bpermute): Use . (addv64si3_vcc): Rename to ... (add3_vcc): ... this, and use V_SI. (addv64si3_vcc_dup): Rename to ... (add3_vcc_dup): ... this, and use V_SI. (addcv64si3): Rename to ... (addc3): ... this, and use V_SI. (subv64si3_vcc): Rename to ... (sub3_vcc): ... this, and use V_SI. (subcv64si3): Rename to ... (subc3): ... this, and use V_SI. (addv64di3): Rename to ... (add3): ... this, and use V_DI. (addv64di3_exec): Rename to ... (add3_exec): ... this, and use V_DI. (subv64di3): Rename to ... (sub3): ... this, and use V_DI. (subv64di3_exec): Rename to ... (sub3_exec): ... this, and use V_DI. (addv64di3_zext): Rename to ... (add3_zext): ... this, and use V_DI and . (addv64di3_zext_exec): Rename to ... (add3_zext_exec): ... this, and use V_DI and . (addv64di3_zext_dup): Rename to ... (add3_zext_dup): ... this, and use V_DI and . (addv64di3_zext_dup_exec): Rename to ... (add3_zext_dup_exec): ... this, and use V_DI and . (addv64di3_zext_dup2): Rename to ... (add3_zext_dup2): ... this, and use V_DI and . (addv64di3_zext_dup2_exec): Rename to ... (add3_zext_dup2_exec): ... this, and use V_DI and . (addv64di3_sext_dup2): Rename to ... (add3_sext_dup2): ... this, and use V_DI and . (addv64di3_sext_dup2_exec): Rename to ... (add3_sext_dup2_exec): ... this, and use V_DI and . (mulv64si3_highpart): Rename to ... (mul3_highpart): ... this and use V_SI and . (mulv64di3): Rename to ... (mul3): ... this, and use V_DI and . (mulv64di3_exec): Rename to ... (mul3_exec): ... this, and use V_DI and . (mulv64di3_zext): Rename to ... (mul3_zext): ... this, and use V_DI and . (mulv64di3_zext_exec): Rename to ... (mul3_zext_exec): ... this, and use V_DI and . (mulv64di3_zext_dup2): Rename to ... (mul3_zext_dup2): ... this, and use V_DI and . (mulv64di3_zext_dup2_exec): Rename to ... (mul3_zext_dup2_exec): ... this, and use V_DI and . (v64di3): Rename to ... (3): ... this, and use V_DI and . (v64di3_exec): Rename to ... (3_exec): ... this, and use V_DI and . (v64si3): Rename to ... (3): ... this, and use V_SI and . (vv64si3): Rename to ... (v3): ... this, and use V_SI and . (v64si3): Rename to ... (3): ... this, and use V_SI. (subv64df3): Rename to ... (sub3): ... this, and use V_DF. (truncv64di2): Rename to ... (trunc2): ... this, and use . (truncv64di2_exec): Rename to ... (trunc2_exec): ... this, and use . (v64di2): Rename to ... (2): ... this, and use . (v64di2_exec): Rename to ... (2_exec): ... this, and use . (vec_cmpv64qidi): Rename to ... (vec_cmpdi): ... this, and use . (vec_cmpv64qidi_exec): Rename to ... (vec_cmpdi_exec): ... this, and use . (vcond_mask_di): Use . (maskloaddi): Likewise. (maskstoredi): Likewise. (mask_gather_loadv64si): Rename to ... (mask_gather_load): ... this, and use and . (mask_scatter_storev64si): Rename to ... (mask_scatter_store): ... this, and use and . (*_dpp_shr_v64di): Rename to ... (*_dpp_shr_): ... this, and use V_DI and . (*plus_carry_in_dpp_shr_v64si): Rename to ... (*plus_carry_in_dpp_shr_): ... this, and use V_SI. (*plus_carry_dpp_shr_v64di): Rename to ... (*plus_carry_dpp_shr_): ... this, and use V_DI and . (vec_seriesv64si): Rename to ... (vec_series): ... this, and use V_SI. (vec_seriesv64di): Rename to ... (vec_series): ... this, and use V_DI. 2020-03-31 Claudiu Zissulescu * config/arc/arc.c (arc_print_operand): Use HOST_WIDE_INT_PRINT_DEC macro. 2020-03-31 Claudiu Zissulescu * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it. 2020-03-31 Srinath Parvathaneni * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic variant. (__arm_vbicq): Likewise. 2020-03-31 Vineet Gupta * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700. 2020-03-31 Srinath Parvathaneni * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the common section of both MVE Integer and MVE Floating Point. (vaddvq): Likewise. (vaddlvq_p): Likewise. (vaddvaq): Likewise. (vaddvq_p): Likewise. (vcmpcsq): Likewise. (vmlsdavxq): Likewise. (vmlsdavq): Likewise. (vmladavxq): Likewise. (vmladavq): Likewise. (vminvq): Likewise. (vminavq): Likewise. (vmaxvq): Likewise. (vmaxavq): Likewise. (vmlaldavq): Likewise. (vcmphiq): Likewise. (vaddlvaq): Likewise. (vrmlaldavhq): Likewise. (vrmlaldavhxq): Likewise. (vrmlsldavhq): Likewise. (vrmlsldavhxq): Likewise. (vmlsldavxq): Likewise. (vmlsldavq): Likewise. (vabavq): Likewise. (vrmlaldavhaq): Likewise. (vcmpgeq_m_n): Likewise. (vmlsdavxq_p): Likewise. (vmlsdavq_p): Likewise. (vmlsdavaxq): Likewise. (vmlsdavaq): Likewise. (vaddvaq_p): Likewise. (vcmpcsq_m_n): Likewise. (vcmpcsq_m): Likewise. (vmladavxq_p): Likewise. (vmladavq_p): Likewise. (vmladavaxq): Likewise. (vmladavaq): Likewise. (vminvq_p): Likewise. (vminavq_p): Likewise. (vmaxvq_p): Likewise. (vmaxavq_p): Likewise. (vcmphiq_m): Likewise. (vaddlvaq_p): Likewise. (vmlaldavaq): Likewise. (vmlaldavaxq): Likewise. (vmlaldavq_p): Likewise. (vmlaldavxq_p): Likewise. (vmlsldavaq): Likewise. (vmlsldavaxq): Likewise. (vmlsldavq_p): Likewise. (vmlsldavxq_p): Likewise. (vrmlaldavhaxq): Likewise. (vrmlaldavhq_p): Likewise. (vrmlaldavhxq_p): Likewise. (vrmlsldavhaq): Likewise. (vrmlsldavhaxq): Likewise. (vrmlsldavhq_p): Likewise. (vrmlsldavhxq_p): Likewise. (vabavq_p): Likewise. (vmladavaq_p): Likewise. (vstrbq_scatter_offset): Likewise. (vstrbq_p): Likewise. (vstrbq_scatter_offset_p): Likewise. (vstrdq_scatter_base_p): Likewise. (vstrdq_scatter_base): Likewise. (vstrdq_scatter_offset_p): Likewise. (vstrdq_scatter_offset): Likewise. (vstrdq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_shifted_offset): Likewise. (vmaxq_x): Likewise. (vminq_x): Likewise. (vmovlbq_x): Likewise. (vmovltq_x): Likewise. (vmulhq_x): Likewise. (vmullbq_int_x): Likewise. (vmullbq_poly_x): Likewise. (vmulltq_int_x): Likewise. (vmulltq_poly_x): Likewise. (vstrbq): Likewise. 2020-03-31 Jakub Jelinek PR target/94368 * config/aarch64/constraints.md (Uph): New constraint. * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr. (@aarch64_compare_and_swap): Use it instead of n in operand 2's constraint. 2020-03-31 Marc Glisse Jakub Jelinek PR middle-end/94412 * fold-const.c (fold_binary_loc) : Use ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P. 2020-03-31 Jakub Jelinek PR tree-optimization/94403 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also ENUMERAL_TYPE lhs_type. PR rtl-optimization/94344 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision conversions, either on both operands of |^+ or just one. Handle also extra same precision conversion on RSHIFT_EXPR first operand provided RSHIFT_EXPR is performed in unsigned type. 2020-03-30 David Malcolm * lra.c (finish_insn_code_data_once): Set the array elements to NULL after freeing them. 2020-03-30 Andreas Schwab * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]: Define. 2020-03-30 Will Schmidt * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code to skip defining builtins based on builtin_mask. 2020-03-30 Jakub Jelinek PR target/94343 * config/i386/sse.md (one_cmpl2): If !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input operand is a register. Don't enable masked variants for V*[QH]Imode. PR target/93069 * config/i386/sse.md (vec_extract_lo_): Use instead of m in output operand constraint. (vec_extract_hi_): Use instead of %{%3%}. 2020-03-30 Alan Modra * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern. (rs6000_indirect_call_template_1): Adjust to suit. * config/rs6000/rs6000.md (call_local): Merge call_local32, call_local64, and call_local_aix. (call_value_local): Simlarly. (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit, and disable pattern when CALL_LONG. (call_indirect_aix, call_value_indirect_aix): Adjust rtl. (call_indirect_elfv2, call_indirect_pcrel): Likewise. (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise. 2020-03-29 H.J. Lu PR driver/94381 * doc/invoke.texi: Update -falign-functions, -falign-loops and -falign-jumps documentation. 2020-03-29 Martin Liska PR ipa/94363 * cgraphunit.c (process_function_and_variable_attributes): Remove double 'attribute' words. 2020-03-29 John David Anglin * gcc/config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate .align output. 2020-03-28 Jakub Jelinek PR c/93573 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const to true after setting size to integer_one_node. PR tree-optimization/94329 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt on the last stmt in a bb, make sure gsi_prev isn't done immediately after gsi_last_bb. 2020-03-27 Alan Modra PR target/94145 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile for PLT16_LO and PLT_PCREL. * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove. (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define. (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile. 2020-03-27 Martin Sebor PR c++/94098 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes. 2020-03-27 Andrew Stubbs * config/gcn/gcn-valu.md: (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout. (VEC_1REG_MODE): Delete. (VEC_1REG_ALT): Delete. (VEC_ALL1REG_MODE): Rename to V_1REG throughout. (VEC_1REG_INT_MODE): Delete. (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout. (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout. (VEC_2REG_MODE): Rename to V_2REG throughout. (VEC_REG_MODE): Rename to V_noHI throughout. (VEC_ALLREG_MODE): Rename to V_ALL throughout. (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout. (VEC_ALLREG_INT_MODE): Rename to V_INT throughout. (VEC_INT_MODE): Delete. (VEC_FP_MODE): Rename to V_FP throughout and move to top. (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top. (FP_MODE): Delete and replace with FP throughout. (FP_1REG_MODE): Delete and replace with FP_1REG throughout. (VCMP_MODE): Rename to V_noQI throughout and move to top. (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top. * config/gcn/gcn.md (FP): New mode iterator. (FP_1REG): New mode iterator. 2020-03-27 David Malcolm * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this now emits two .dot files. * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD. (graphviz_out::end_tr): Only close a TR, not a TD. (graphviz_out::begin_td): New. (graphviz_out::end_td): New. (graphviz_out::begin_trtd): New, replacing the old implementation of graphviz_out::begin_tr. (graphviz_out::end_tdtr): New, replacing the old implementation of graphviz_out::end_tr. * graphviz.h (graphviz_out::begin_td): New decl. (graphviz_out::end_td): New decl. (graphviz_out::begin_trtd): New decl. (graphviz_out::end_tdtr): New decl. 2020-03-27 Richard Biener PR debug/94273 * dwarf2out.c (should_emit_struct_debug): Return false for DINFO_LEVEL_TERSE. 2020-03-27 Richard Biener PR tree-optimization/94352 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the worklist ... (ssa_propagation_engine::ssa_propagate): ... here after initializing curr_order. 2020-03-27 Kewen Lin PR tree-optimization/90332 * tree-vect-stmts.c (vector_vector_composition_type): New function. (get_group_load_store_type): Adjust to call vector_vector_composition_type, extend it to construct with scalar types. (vectorizable_load): Likewise. 2020-03-27 Roman Zhuykov * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions. (create_ddg_dep_no_link): Likewise. (add_cross_iteration_register_deps): Move debug instruction check. Other minor refactoring. (add_intra_loop_mem_dep): Do not check for debug instructions. (add_inter_loop_mem_dep): Likewise. (build_intra_loop_deps): Likewise. (create_ddg): Do not include debug insns into the graph. * ddg.h (struct ddg): Remove num_debug field. * modulo-sched.c (doloop_register_get): Adjust condition. (res_MII): Remove DDG num_debug field usage. (sms_schedule_by_order): Use assertion against debug insns. (ps_has_conflicts): Drop debug insn check. 2020-03-26 Jakub Jelinek PR debug/94323 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST that contains exactly one non-DEBUG_BEGIN_STMT statement. PR debug/94281 * gimple.h (gimple_seq_first_nondebug_stmt): New function. (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains a single non-debug stmt followed by one or more debug stmts. * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and gimple_seq_last to check if outer_stmt gbind could be reused and if yes and it is surrounded by any debug stmts, move them into the gbind body. PR rtl-optimization/92264 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even for sp based values in !frame_pointer_needed && !ACCUMULATE_OUTGOING_ARGS functions. 2020-03-26 Felix Yang PR tree-optimization/94269 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict this operation to single basic block. 2020-03-25 Jeff Law PR rtl-optimization/90275 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the pattern. 2020-03-25 Jakub Jelinek PR target/94292 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to mode rather than VOIDmode. 2020-03-25 Martin Sebor PR middle-end/94004 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings even for alloca calls resulting from system macro expansion. Include inlining context in all warnings. 2020-03-25 Richard Sandiford PR target/94254 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow FPRs to change between SDmode and DDmode. 2020-03-25 Martin Sebor PR tree-optimization/94131 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length types and decls. * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming types have constant sizes. 2020-03-25 Martin Liska PR lto/94259 * configure.ac: Report error only when --with-zstd is used. * configure: Regenerate. 2020-03-25 Jakub Jelinek PR target/94308 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set INSN_CODE (insn) to -1 when changing the pattern. 2020-03-25 Martin Liska PR target/93274 PR ipa/94271 * config/i386/i386-features.c (make_resolver_func): Drop public flag for resolver. * config/rs6000/rs6000.c (make_resolver_func): Add comdat group for resolver and drop public flag if possible. * multiple_target.c (create_dispatcher_calls): Drop unique_name and resolution as we want to enable LTO privatization of the default symbol. 2020-03-25 Martin Liska PR lto/94259 * configure.ac: Respect --without-zstd and report error when we can't find header file with --with-zstd. * configure: Regenerate. 2020-03-25 Jakub Jelinek PR middle-end/94303 * varasm.c (output_constructor_array_range): If local->index RANGE_EXPR doesn't start at the current location in the constructor, skip needed number of bytes using assemble_zeros or assert we don't go backwards. PR c++/94223 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong counter instead of DECL_UID. PR tree-optimization/94300 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset is positive, make sure that off + size isn't larger than needed_len. 2020-03-25 Richard Biener Jakub Jelinek PR debug/94283 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards. 2020-03-24 Christophe Lyon * doc/sourcebuild.texi (ARM-specific attributes): Add arm_fp_dp_ok. (Features for dg-add-options): Add arm_fp_dp. 2020-03-24 John David Anglin PR lto/94249 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__. 2020-03-24 Tobias Burnus PR libgomp/81689 * omp-offload.c (omp_finish_file): Fix target-link handling if targetm_common.have_named_sections is false. 2020-03-24 Jakub Jelinek PR target/94286 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode instead of GEN_INT. PR debug/94285 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts. If not after and at *incr_pos is a debug stmt, set stmt location to location of next non-debug stmt after it if any. PR debug/94283 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set GF_PLF_2, but don't add them to worklist. Don't add an assigment to worklist or set GF_PLF_2 just because it is used in a debug stmt in another bb. Formatting improvements. PR debug/94277 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC regardless of whether TREE_NO_WARNING is set on it or whether warn_unused_function is true or not. 2020-03-23 Jeff Law PR rtl-optimization/90275 PR target/94238 PR target/94144 * simplify-rtx.c (comparison_code_valid_for_mode): New function. (simplify_logical_relational_operation): Use it. 2020-03-23 Jakub Jelinek PR c++/91993 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on ultimate rhs and if returned something different, reconstructing the COMPOUND_EXPRs. 2020-03-23 Lewis Hyatt * opts.c (print_filtered_help): Improve the help text for alias options. 2020-03-23 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm_mve.h (vshlcq_m_s8): Define macro. (vshlcq_m_u8): Likewise. (vshlcq_m_s16): Likewise. (vshlcq_m_u16): Likewise. (vshlcq_m_s32): Likewise. (vshlcq_m_u32): Likewise. (__arm_vshlcq_m_s8): Define intrinsic. (__arm_vshlcq_m_u8): Likewise. (__arm_vshlcq_m_s16): Likewise. (__arm_vshlcq_m_u16): Likewise. (__arm_vshlcq_m_s32): Likewise. (__arm_vshlcq_m_u32): Likewise. (vshlcq_m): Define polymorphic variant. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE): Use builtin qualifier. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. * config/arm/mve.md (mve_vshlcq_m_vec_): Define RTL pattern. (mve_vshlcq_m_carry_): Likewise. (mve_vshlcq_m_): Likewise. 2020-03-23 Srinath Parvathaneni * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier. (UQSHL_QUALIFIERS): Likewise. (ASRL_QUALIFIERS): Likewise. (SQSHL_QUALIFIERS): Likewise. * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in Big-Endian Mode. (sqrshr): Define macro. (sqrshrl): Likewise. (sqrshrl_sat48): Likewise. (sqshl): Likewise. (sqshll): Likewise. (srshr): Likewise. (srshrl): Likewise. (uqrshl): Likewise. (uqrshll): Likewise. (uqrshll_sat48): Likewise. (uqshl): Likewise. (uqshll): Likewise. (urshr): Likewise. (urshrl): Likewise. (lsll): Likewise. (asrl): Likewise. (__arm_lsll): Define intrinsic. (__arm_asrl): Likewise. (__arm_uqrshll): Likewise. (__arm_uqrshll_sat48): Likewise. (__arm_sqrshrl): Likewise. (__arm_sqrshrl_sat48): Likewise. (__arm_uqshll): Likewise. (__arm_urshrl): Likewise. (__arm_srshrl): Likewise. (__arm_sqshll): Likewise. (__arm_uqrshl): Likewise. (__arm_sqrshr): Likewise. (__arm_uqshl): Likewise. (__arm_urshr): Likewise. (__arm_sqshl): Likewise. (__arm_srshr): Likewise. * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin qualifier. (UQSHL_QUALIFIERS): Likewise. (ASRL_QUALIFIERS): Likewise. (SQSHL_QUALIFIERS): Likewise. * config/arm/mve.md (mve_uqrshll_sat_di): Define RTL pattern. (mve_sqrshrl_sat_di): Likewise. (mve_uqrshl_si): Likewise. (mve_sqrshr_si): Likewise. (mve_uqshll_di): Likewise. (mve_urshrl_di): Likewise. (mve_uqshl_si): Likewise. (mve_urshr_si): Likewise. (mve_sqshl_si): Likewise. (mve_srshr_si): Likewise. (mve_srshrl_di): Likewise. (mve_sqshll_di): Likewise. 2020-03-23 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm_mve.h (vsetq_lane_f16): Define macro. (vsetq_lane_f32): Likewise. (vsetq_lane_s16): Likewise. (vsetq_lane_s32): Likewise. (vsetq_lane_s8): Likewise. (vsetq_lane_s64): Likewise. (vsetq_lane_u8): Likewise. (vsetq_lane_u16): Likewise. (vsetq_lane_u32): Likewise. (vsetq_lane_u64): Likewise. (vgetq_lane_f16): Likewise. (vgetq_lane_f32): Likewise. (vgetq_lane_s16): Likewise. (vgetq_lane_s32): Likewise. (vgetq_lane_s8): Likewise. (vgetq_lane_s64): Likewise. (vgetq_lane_u8): Likewise. (vgetq_lane_u16): Likewise. (vgetq_lane_u32): Likewise. (vgetq_lane_u64): Likewise. (__ARM_NUM_LANES): Likewise. (__ARM_LANEQ): Likewise. (__ARM_CHECK_LANEQ): Likewise. (__arm_vsetq_lane_s16): Define intrinsic. (__arm_vsetq_lane_s32): Likewise. (__arm_vsetq_lane_s8): Likewise. (__arm_vsetq_lane_s64): Likewise. (__arm_vsetq_lane_u8): Likewise. (__arm_vsetq_lane_u16): Likewise. (__arm_vsetq_lane_u32): Likewise. (__arm_vsetq_lane_u64): Likewise. (__arm_vgetq_lane_s16): Likewise. (__arm_vgetq_lane_s32): Likewise. (__arm_vgetq_lane_s8): Likewise. (__arm_vgetq_lane_s64): Likewise. (__arm_vgetq_lane_u8): Likewise. (__arm_vgetq_lane_u16): Likewise. (__arm_vgetq_lane_u32): Likewise. (__arm_vgetq_lane_u64): Likewise. (__arm_vsetq_lane_f16): Likewise. (__arm_vsetq_lane_f32): Likewise. (__arm_vgetq_lane_f16): Likewise. (__arm_vgetq_lane_f32): Likewise. (vgetq_lane): Define polymorphic variant. (vsetq_lane): Likewise. * config/arm/mve.md (mve_vec_extract): Define RTL pattern. (mve_vec_extractv2didi): Likewise. (mve_vec_extract_sext_internal): Likewise. (mve_vec_extract_zext_internal): Likewise. (mve_vec_set_internal): Likewise. (mve_vec_setv2di_internal): Likewise. * config/arm/neon.md (vec_set): Move RTL pattern to vec-common.md file. (vec_extract): Rename to "neon_vec_extract". (vec_extractv2didi): Rename to "neon_vec_extractv2didi". * config/arm/vec-common.md (vec_extract): Define RTL pattern common for MVE and NEON. (vec_set): Move RTL pattern from neon.md and modify to accept both MVE and NEON. 2020-03-23 Andre Vieira * config/arm/mve.md (earlyclobber_32): New mode attribute. (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*, mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers. 2020-03-23 Richard Biener PR tree-optimization/94261 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove IL operand swapping code. (vect_slp_rearrange_stmts): Do not arrange isomorphic nodes that would need operation code adjustments. 2020-03-23 Tobias Burnus * doc/install.texi (amdgcn-*-amdhsa): Renamed from amdgcn-unknown-amdhsa; change amdgcn-unknown-amdhsa to amdgcn-amdhsa. 2020-03-23 Richard Biener PR ipa/94245 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP directly rather than also folding it via build_fold_addr_expr. 2020-03-23 Richard Biener PR tree-optimization/94266 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate addresses of TARGET_MEM_REFs. 2020-03-23 Martin Liska PR ipa/94250 * symtab.c (symtab_node::clone_references): Save speculative_id as ref may be overwritten by create_reference. (symtab_node::clone_referring): Likewise. (symtab_node::clone_reference): Likewise. 2020-03-22 Iain Sandoe * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove references to Darwin. * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this unconditionally and comment on why. 2020-03-21 Iain Sandoe * config/darwin.c (darwin_mergeable_constant_section): Collect section anchor checks into the caller. (machopic_select_section): Collect section anchor checks into the determination of 'effective zero-size' objects. When the size is unknown, assume it is non-zero, and thus return the 'generic' section for the DECL. 2020-03-21 Iain Sandoe PR target/93694 * gcc/config/darwin.opt: Amend options descriptions. 2020-03-21 Richard Sandiford PR rtl-optimization/94052 * lra-constraints.c (simplify_operand_subreg): Reload the inner register of a paradoxical subreg if simplify_subreg_regno fails to give a valid hard register for the outer mode. 2020-03-20 Martin Jambor PR tree-optimization/93435 * params.opt (sra-max-propagations): New parameter. * tree-sra.c (propagation_budget): New variable. (budget_for_propagation_access): New function. (propagate_subaccesses_from_rhs): Use it. (propagate_subaccesses_from_lhs): Likewise. (propagate_all_subaccesses): Set up and destroy propagation_budget. 2020-03-20 Carl Love PR/target 87583 * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal): Add check for TARGET_FPRND for Power 7 or newer. 2020-03-20 Jan Hubicka PR ipa/93347 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag. (cgraph_edge::redirect_callee): Move here; likewise. (cgraph_node::remove_callees): Update calls_comdat_local flag. (cgraph_node::verify_node): Verify that calls_comdat_local flag match reality. (cgraph_node::check_calls_comdat_local_p): New member function. * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare. (cgraph_edge::redirect_callee): Move offline. * ipa-fnsummary.c (compute_fn_summary): Do not compute calls_comdat_local flag here. * ipa-inline-transform.c (inline_call): Fix updating of calls_comdat_local flag. * ipa-split.c (split_function): Use true instead of 1 to set the flag. * symtab.c (symtab_node::add_to_same_comdat_group): Update calls_comdat_local flag. 2020-03-20 Richard Biener * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree from the possibly modified root. 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm_mve.h (vst1q_p_u8): Define macro. (vst1q_p_s8): Likewise. (vst2q_s8): Likewise. (vst2q_u8): Likewise. (vld1q_z_u8): Likewise. (vld1q_z_s8): Likewise. (vld2q_s8): Likewise. (vld2q_u8): Likewise. (vld4q_s8): Likewise. (vld4q_u8): Likewise. (vst1q_p_u16): Likewise. (vst1q_p_s16): Likewise. (vst2q_s16): Likewise. (vst2q_u16): Likewise. (vld1q_z_u16): Likewise. (vld1q_z_s16): Likewise. (vld2q_s16): Likewise. (vld2q_u16): Likewise. (vld4q_s16): Likewise. (vld4q_u16): Likewise. (vst1q_p_u32): Likewise. (vst1q_p_s32): Likewise. (vst2q_s32): Likewise. (vst2q_u32): Likewise. (vld1q_z_u32): Likewise. (vld1q_z_s32): Likewise. (vld2q_s32): Likewise. (vld2q_u32): Likewise. (vld4q_s32): Likewise. (vld4q_u32): Likewise. (vld4q_f16): Likewise. (vld2q_f16): Likewise. (vld1q_z_f16): Likewise. (vst2q_f16): Likewise. (vst1q_p_f16): Likewise. (vld4q_f32): Likewise. (vld2q_f32): Likewise. (vld1q_z_f32): Likewise. (vst2q_f32): Likewise. (vst1q_p_f32): Likewise. (__arm_vst1q_p_u8): Define intrinsic. (__arm_vst1q_p_s8): Likewise. (__arm_vst2q_s8): Likewise. (__arm_vst2q_u8): Likewise. (__arm_vld1q_z_u8): Likewise. (__arm_vld1q_z_s8): Likewise. (__arm_vld2q_s8): Likewise. (__arm_vld2q_u8): Likewise. (__arm_vld4q_s8): Likewise. (__arm_vld4q_u8): Likewise. (__arm_vst1q_p_u16): Likewise. (__arm_vst1q_p_s16): Likewise. (__arm_vst2q_s16): Likewise. (__arm_vst2q_u16): Likewise. (__arm_vld1q_z_u16): Likewise. (__arm_vld1q_z_s16): Likewise. (__arm_vld2q_s16): Likewise. (__arm_vld2q_u16): Likewise. (__arm_vld4q_s16): Likewise. (__arm_vld4q_u16): Likewise. (__arm_vst1q_p_u32): Likewise. (__arm_vst1q_p_s32): Likewise. (__arm_vst2q_s32): Likewise. (__arm_vst2q_u32): Likewise. (__arm_vld1q_z_u32): Likewise. (__arm_vld1q_z_s32): Likewise. (__arm_vld2q_s32): Likewise. (__arm_vld2q_u32): Likewise. (__arm_vld4q_s32): Likewise. (__arm_vld4q_u32): Likewise. (__arm_vld4q_f16): Likewise. (__arm_vld2q_f16): Likewise. (__arm_vld1q_z_f16): Likewise. (__arm_vst2q_f16): Likewise. (__arm_vst1q_p_f16): Likewise. (__arm_vld4q_f32): Likewise. (__arm_vld2q_f32): Likewise. (__arm_vld1q_z_f32): Likewise. (__arm_vst2q_f32): Likewise. (__arm_vst1q_p_f32): Likewise. (vld1q_z): Define polymorphic variant. (vld2q): Likewise. (vld4q): Likewise. (vst1q_p): Likewise. (vst2q): Likewise. * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier. (LOAD1): Likewise. * config/arm/mve.md (mve_vst2q): Define RTL pattern. (mve_vld2q): Likewise. (mve_vld4q): Likewise. 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define. (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise. (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array. (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC and ARM_BUILTIN_SET_FPSCR_NZCVQC. * config/arm/arm_mve.h (vadciq_s32): Define macro. (vadciq_u32): Likewise. (vadciq_m_s32): Likewise. (vadciq_m_u32): Likewise. (vadcq_s32): Likewise. (vadcq_u32): Likewise. (vadcq_m_s32): Likewise. (vadcq_m_u32): Likewise. (vsbciq_s32): Likewise. (vsbciq_u32): Likewise. (vsbciq_m_s32): Likewise. (vsbciq_m_u32): Likewise. (vsbcq_s32): Likewise. (vsbcq_u32): Likewise. (vsbcq_m_s32): Likewise. (vsbcq_m_u32): Likewise. (__arm_vadciq_s32): Define intrinsic. (__arm_vadciq_u32): Likewise. (__arm_vadciq_m_s32): Likewise. (__arm_vadciq_m_u32): Likewise. (__arm_vadcq_s32): Likewise. (__arm_vadcq_u32): Likewise. (__arm_vadcq_m_s32): Likewise. (__arm_vadcq_m_u32): Likewise. (__arm_vsbciq_s32): Likewise. (__arm_vsbciq_u32): Likewise. (__arm_vsbciq_m_s32): Likewise. (__arm_vsbciq_m_u32): Likewise. (__arm_vsbcq_s32): Likewise. (__arm_vsbcq_u32): Likewise. (__arm_vsbcq_m_s32): Likewise. (__arm_vsbcq_m_u32): Likewise. (vadciq_m): Define polymorphic variant. (vadciq): Likewise. (vadcq_m): Likewise. (vadcq): Likewise. (vsbciq_m): Likewise. (vsbciq): Likewise. (vsbcq_m): Likewise. (vsbcq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin qualifier. (BINOP_UNONE_UNONE_UNONE): Likewise. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VADCIQ): Define iterator. (VADCIQ_M): Likewise. (VSBCQ): Likewise. (VSBCQ_M): Likewise. (VSBCIQ): Likewise. (VSBCIQ_M): Likewise. (VADCQ): Likewise. (VADCQ_M): Likewise. (mve_vadciq_m_v4si): Define RTL pattern. (mve_vadciq_v4si): Likewise. (mve_vadcq_m_v4si): Likewise. (mve_vadcq_v4si): Likewise. (mve_vsbciq_m_v4si): Likewise. (mve_vsbciq_v4si): Likewise. (mve_vsbcq_m_v4si): Likewise. (mve_vsbcq_v4si): Likewise. (get_fpscr_nzcvqc): Define isns. (set_fpscr_nzcvqc): Define isns. * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define. (UNSPEC_SET_FPSCR_NZCVQC): Define. 2020-03-20 Srinath Parvathaneni * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro. (vddupq_x_n_u16): Likewise. (vddupq_x_n_u32): Likewise. (vddupq_x_wb_u8): Likewise. (vddupq_x_wb_u16): Likewise. (vddupq_x_wb_u32): Likewise. (vdwdupq_x_n_u8): Likewise. (vdwdupq_x_n_u16): Likewise. (vdwdupq_x_n_u32): Likewise. (vdwdupq_x_wb_u8): Likewise. (vdwdupq_x_wb_u16): Likewise. (vdwdupq_x_wb_u32): Likewise. (vidupq_x_n_u8): Likewise. (vidupq_x_n_u16): Likewise. (vidupq_x_n_u32): Likewise. (vidupq_x_wb_u8): Likewise. (vidupq_x_wb_u16): Likewise. (vidupq_x_wb_u32): Likewise. (viwdupq_x_n_u8): Likewise. (viwdupq_x_n_u16): Likewise. (viwdupq_x_n_u32): Likewise. (viwdupq_x_wb_u8): Likewise. (viwdupq_x_wb_u16): Likewise. (viwdupq_x_wb_u32): Likewise. (vdupq_x_n_s8): Likewise. (vdupq_x_n_s16): Likewise. (vdupq_x_n_s32): Likewise. (vdupq_x_n_u8): Likewise. (vdupq_x_n_u16): Likewise. (vdupq_x_n_u32): Likewise. (vminq_x_s8): Likewise. (vminq_x_s16): Likewise. (vminq_x_s32): Likewise. (vminq_x_u8): Likewise. (vminq_x_u16): Likewise. (vminq_x_u32): Likewise. (vmaxq_x_s8): Likewise. (vmaxq_x_s16): Likewise. (vmaxq_x_s32): Likewise. (vmaxq_x_u8): Likewise. (vmaxq_x_u16): Likewise. (vmaxq_x_u32): Likewise. (vabdq_x_s8): Likewise. (vabdq_x_s16): Likewise. (vabdq_x_s32): Likewise. (vabdq_x_u8): Likewise. (vabdq_x_u16): Likewise. (vabdq_x_u32): Likewise. (vabsq_x_s8): Likewise. (vabsq_x_s16): Likewise. (vabsq_x_s32): Likewise. (vaddq_x_s8): Likewise. (vaddq_x_s16): Likewise. (vaddq_x_s32): Likewise. (vaddq_x_n_s8): Likewise. (vaddq_x_n_s16): Likewise. (vaddq_x_n_s32): Likewise. (vaddq_x_u8): Likewise. (vaddq_x_u16): Likewise. (vaddq_x_u32): Likewise. (vaddq_x_n_u8): Likewise. (vaddq_x_n_u16): Likewise. (vaddq_x_n_u32): Likewise. (vclsq_x_s8): Likewise. (vclsq_x_s16): Likewise. (vclsq_x_s32): Likewise. (vclzq_x_s8): Likewise. (vclzq_x_s16): Likewise. (vclzq_x_s32): Likewise. (vclzq_x_u8): Likewise. (vclzq_x_u16): Likewise. (vclzq_x_u32): Likewise. (vnegq_x_s8): Likewise. (vnegq_x_s16): Likewise. (vnegq_x_s32): Likewise. (vmulhq_x_s8): Likewise. (vmulhq_x_s16): Likewise. (vmulhq_x_s32): Likewise. (vmulhq_x_u8): Likewise. (vmulhq_x_u16): Likewise. (vmulhq_x_u32): Likewise. (vmullbq_poly_x_p8): Likewise. (vmullbq_poly_x_p16): Likewise. (vmullbq_int_x_s8): Likewise. (vmullbq_int_x_s16): Likewise. (vmullbq_int_x_s32): Likewise. (vmullbq_int_x_u8): Likewise. (vmullbq_int_x_u16): Likewise. (vmullbq_int_x_u32): Likewise. (vmulltq_poly_x_p8): Likewise. (vmulltq_poly_x_p16): Likewise. (vmulltq_int_x_s8): Likewise. (vmulltq_int_x_s16): Likewise. (vmulltq_int_x_s32): Likewise. (vmulltq_int_x_u8): Likewise. (vmulltq_int_x_u16): Likewise. (vmulltq_int_x_u32): Likewise. (vmulq_x_s8): Likewise. (vmulq_x_s16): Likewise. (vmulq_x_s32): Likewise. (vmulq_x_n_s8): Likewise. (vmulq_x_n_s16): Likewise. (vmulq_x_n_s32): Likewise. (vmulq_x_u8): Likewise. (vmulq_x_u16): Likewise. (vmulq_x_u32): Likewise. (vmulq_x_n_u8): Likewise. (vmulq_x_n_u16): Likewise. (vmulq_x_n_u32): Likewise. (vsubq_x_s8): Likewise. (vsubq_x_s16): Likewise. (vsubq_x_s32): Likewise. (vsubq_x_n_s8): Likewise. (vsubq_x_n_s16): Likewise. (vsubq_x_n_s32): Likewise. (vsubq_x_u8): Likewise. (vsubq_x_u16): Likewise. (vsubq_x_u32): Likewise. (vsubq_x_n_u8): Likewise. (vsubq_x_n_u16): Likewise. (vsubq_x_n_u32): Likewise. (vcaddq_rot90_x_s8): Likewise. (vcaddq_rot90_x_s16): Likewise. (vcaddq_rot90_x_s32): Likewise. (vcaddq_rot90_x_u8): Likewise. (vcaddq_rot90_x_u16): Likewise. (vcaddq_rot90_x_u32): Likewise. (vcaddq_rot270_x_s8): Likewise. (vcaddq_rot270_x_s16): Likewise. (vcaddq_rot270_x_s32): Likewise. (vcaddq_rot270_x_u8): Likewise. (vcaddq_rot270_x_u16): Likewise. (vcaddq_rot270_x_u32): Likewise. (vhaddq_x_n_s8): Likewise. (vhaddq_x_n_s16): Likewise. (vhaddq_x_n_s32): Likewise. (vhaddq_x_n_u8): Likewise. (vhaddq_x_n_u16): Likewise. (vhaddq_x_n_u32): Likewise. (vhaddq_x_s8): Likewise. (vhaddq_x_s16): Likewise. (vhaddq_x_s32): Likewise. (vhaddq_x_u8): Likewise. (vhaddq_x_u16): Likewise. (vhaddq_x_u32): Likewise. (vhcaddq_rot90_x_s8): Likewise. (vhcaddq_rot90_x_s16): Likewise. (vhcaddq_rot90_x_s32): Likewise. (vhcaddq_rot270_x_s8): Likewise. (vhcaddq_rot270_x_s16): Likewise. (vhcaddq_rot270_x_s32): Likewise. (vhsubq_x_n_s8): Likewise. (vhsubq_x_n_s16): Likewise. (vhsubq_x_n_s32): Likewise. (vhsubq_x_n_u8): Likewise. (vhsubq_x_n_u16): Likewise. (vhsubq_x_n_u32): Likewise. (vhsubq_x_s8): Likewise. (vhsubq_x_s16): Likewise. (vhsubq_x_s32): Likewise. (vhsubq_x_u8): Likewise. (vhsubq_x_u16): Likewise. (vhsubq_x_u32): Likewise. (vrhaddq_x_s8): Likewise. (vrhaddq_x_s16): Likewise. (vrhaddq_x_s32): Likewise. (vrhaddq_x_u8): Likewise. (vrhaddq_x_u16): Likewise. (vrhaddq_x_u32): Likewise. (vrmulhq_x_s8): Likewise. (vrmulhq_x_s16): Likewise. (vrmulhq_x_s32): Likewise. (vrmulhq_x_u8): Likewise. (vrmulhq_x_u16): Likewise. (vrmulhq_x_u32): Likewise. (vandq_x_s8): Likewise. (vandq_x_s16): Likewise. (vandq_x_s32): Likewise. (vandq_x_u8): Likewise. (vandq_x_u16): Likewise. (vandq_x_u32): Likewise. (vbicq_x_s8): Likewise. (vbicq_x_s16): Likewise. (vbicq_x_s32): Likewise. (vbicq_x_u8): Likewise. (vbicq_x_u16): Likewise. (vbicq_x_u32): Likewise. (vbrsrq_x_n_s8): Likewise. (vbrsrq_x_n_s16): Likewise. (vbrsrq_x_n_s32): Likewise. (vbrsrq_x_n_u8): Likewise. (vbrsrq_x_n_u16): Likewise. (vbrsrq_x_n_u32): Likewise. (veorq_x_s8): Likewise. (veorq_x_s16): Likewise. (veorq_x_s32): Likewise. (veorq_x_u8): Likewise. (veorq_x_u16): Likewise. (veorq_x_u32): Likewise. (vmovlbq_x_s8): Likewise. (vmovlbq_x_s16): Likewise. (vmovlbq_x_u8): Likewise. (vmovlbq_x_u16): Likewise. (vmovltq_x_s8): Likewise. (vmovltq_x_s16): Likewise. (vmovltq_x_u8): Likewise. (vmovltq_x_u16): Likewise. (vmvnq_x_s8): Likewise. (vmvnq_x_s16): Likewise. (vmvnq_x_s32): Likewise. (vmvnq_x_u8): Likewise. (vmvnq_x_u16): Likewise. (vmvnq_x_u32): Likewise. (vmvnq_x_n_s16): Likewise. (vmvnq_x_n_s32): Likewise. (vmvnq_x_n_u16): Likewise. (vmvnq_x_n_u32): Likewise. (vornq_x_s8): Likewise. (vornq_x_s16): Likewise. (vornq_x_s32): Likewise. (vornq_x_u8): Likewise. (vornq_x_u16): Likewise. (vornq_x_u32): Likewise. (vorrq_x_s8): Likewise. (vorrq_x_s16): Likewise. (vorrq_x_s32): Likewise. (vorrq_x_u8): Likewise. (vorrq_x_u16): Likewise. (vorrq_x_u32): Likewise. (vrev16q_x_s8): Likewise. (vrev16q_x_u8): Likewise. (vrev32q_x_s8): Likewise. (vrev32q_x_s16): Likewise. (vrev32q_x_u8): Likewise. (vrev32q_x_u16): Likewise. (vrev64q_x_s8): Likewise. (vrev64q_x_s16): Likewise. (vrev64q_x_s32): Likewise. (vrev64q_x_u8): Likewise. (vrev64q_x_u16): Likewise. (vrev64q_x_u32): Likewise. (vrshlq_x_s8): Likewise. (vrshlq_x_s16): Likewise. (vrshlq_x_s32): Likewise. (vrshlq_x_u8): Likewise. (vrshlq_x_u16): Likewise. (vrshlq_x_u32): Likewise. (vshllbq_x_n_s8): Likewise. (vshllbq_x_n_s16): Likewise. (vshllbq_x_n_u8): Likewise. (vshllbq_x_n_u16): Likewise. (vshlltq_x_n_s8): Likewise. (vshlltq_x_n_s16): Likewise. (vshlltq_x_n_u8): Likewise. (vshlltq_x_n_u16): Likewise. (vshlq_x_s8): Likewise. (vshlq_x_s16): Likewise. (vshlq_x_s32): Likewise. (vshlq_x_u8): Likewise. (vshlq_x_u16): Likewise. (vshlq_x_u32): Likewise. (vshlq_x_n_s8): Likewise. (vshlq_x_n_s16): Likewise. (vshlq_x_n_s32): Likewise. (vshlq_x_n_u8): Likewise. (vshlq_x_n_u16): Likewise. (vshlq_x_n_u32): Likewise. (vrshrq_x_n_s8): Likewise. (vrshrq_x_n_s16): Likewise. (vrshrq_x_n_s32): Likewise. (vrshrq_x_n_u8): Likewise. (vrshrq_x_n_u16): Likewise. (vrshrq_x_n_u32): Likewise. (vshrq_x_n_s8): Likewise. (vshrq_x_n_s16): Likewise. (vshrq_x_n_s32): Likewise. (vshrq_x_n_u8): Likewise. (vshrq_x_n_u16): Likewise. (vshrq_x_n_u32): Likewise. (vdupq_x_n_f16): Likewise. (vdupq_x_n_f32): Likewise. (vminnmq_x_f16): Likewise. (vminnmq_x_f32): Likewise. (vmaxnmq_x_f16): Likewise. (vmaxnmq_x_f32): Likewise. (vabdq_x_f16): Likewise. (vabdq_x_f32): Likewise. (vabsq_x_f16): Likewise. (vabsq_x_f32): Likewise. (vaddq_x_f16): Likewise. (vaddq_x_f32): Likewise. (vaddq_x_n_f16): Likewise. (vaddq_x_n_f32): Likewise. (vnegq_x_f16): Likewise. (vnegq_x_f32): Likewise. (vmulq_x_f16): Likewise. (vmulq_x_f32): Likewise. (vmulq_x_n_f16): Likewise. (vmulq_x_n_f32): Likewise. (vsubq_x_f16): Likewise. (vsubq_x_f32): Likewise. (vsubq_x_n_f16): Likewise. (vsubq_x_n_f32): Likewise. (vcaddq_rot90_x_f16): Likewise. (vcaddq_rot90_x_f32): Likewise. (vcaddq_rot270_x_f16): Likewise. (vcaddq_rot270_x_f32): Likewise. (vcmulq_x_f16): Likewise. (vcmulq_x_f32): Likewise. (vcmulq_rot90_x_f16): Likewise. (vcmulq_rot90_x_f32): Likewise. (vcmulq_rot180_x_f16): Likewise. (vcmulq_rot180_x_f32): Likewise. (vcmulq_rot270_x_f16): Likewise. (vcmulq_rot270_x_f32): Likewise. (vcvtaq_x_s16_f16): Likewise. (vcvtaq_x_s32_f32): Likewise. (vcvtaq_x_u16_f16): Likewise. (vcvtaq_x_u32_f32): Likewise. (vcvtnq_x_s16_f16): Likewise. (vcvtnq_x_s32_f32): Likewise. (vcvtnq_x_u16_f16): Likewise. (vcvtnq_x_u32_f32): Likewise. (vcvtpq_x_s16_f16): Likewise. (vcvtpq_x_s32_f32): Likewise. (vcvtpq_x_u16_f16): Likewise. (vcvtpq_x_u32_f32): Likewise. (vcvtmq_x_s16_f16): Likewise. (vcvtmq_x_s32_f32): Likewise. (vcvtmq_x_u16_f16): Likewise. (vcvtmq_x_u32_f32): Likewise. (vcvtbq_x_f32_f16): Likewise. (vcvttq_x_f32_f16): Likewise. (vcvtq_x_f16_u16): Likewise. (vcvtq_x_f16_s16): Likewise. (vcvtq_x_f32_s32): Likewise. (vcvtq_x_f32_u32): Likewise. (vcvtq_x_n_f16_s16): Likewise. (vcvtq_x_n_f16_u16): Likewise. (vcvtq_x_n_f32_s32): Likewise. (vcvtq_x_n_f32_u32): Likewise. (vcvtq_x_s16_f16): Likewise. (vcvtq_x_s32_f32): Likewise. (vcvtq_x_u16_f16): Likewise. (vcvtq_x_u32_f32): Likewise. (vcvtq_x_n_s16_f16): Likewise. (vcvtq_x_n_s32_f32): Likewise. (vcvtq_x_n_u16_f16): Likewise. (vcvtq_x_n_u32_f32): Likewise. (vrndq_x_f16): Likewise. (vrndq_x_f32): Likewise. (vrndnq_x_f16): Likewise. (vrndnq_x_f32): Likewise. (vrndmq_x_f16): Likewise. (vrndmq_x_f32): Likewise. (vrndpq_x_f16): Likewise. (vrndpq_x_f32): Likewise. (vrndaq_x_f16): Likewise. (vrndaq_x_f32): Likewise. (vrndxq_x_f16): Likewise. (vrndxq_x_f32): Likewise. (vandq_x_f16): Likewise. (vandq_x_f32): Likewise. (vbicq_x_f16): Likewise. (vbicq_x_f32): Likewise. (vbrsrq_x_n_f16): Likewise. (vbrsrq_x_n_f32): Likewise. (veorq_x_f16): Likewise. (veorq_x_f32): Likewise. (vornq_x_f16): Likewise. (vornq_x_f32): Likewise. (vorrq_x_f16): Likewise. (vorrq_x_f32): Likewise. (vrev32q_x_f16): Likewise. (vrev64q_x_f16): Likewise. (vrev64q_x_f32): Likewise. (__arm_vddupq_x_n_u8): Define intrinsic. (__arm_vddupq_x_n_u16): Likewise. (__arm_vddupq_x_n_u32): Likewise. (__arm_vddupq_x_wb_u8): Likewise. (__arm_vddupq_x_wb_u16): Likewise. (__arm_vddupq_x_wb_u32): Likewise. (__arm_vdwdupq_x_n_u8): Likewise. (__arm_vdwdupq_x_n_u16): Likewise. (__arm_vdwdupq_x_n_u32): Likewise. (__arm_vdwdupq_x_wb_u8): Likewise. (__arm_vdwdupq_x_wb_u16): Likewise. (__arm_vdwdupq_x_wb_u32): Likewise. (__arm_vidupq_x_n_u8): Likewise. (__arm_vidupq_x_n_u16): Likewise. (__arm_vidupq_x_n_u32): Likewise. (__arm_vidupq_x_wb_u8): Likewise. (__arm_vidupq_x_wb_u16): Likewise. (__arm_vidupq_x_wb_u32): Likewise. (__arm_viwdupq_x_n_u8): Likewise. (__arm_viwdupq_x_n_u16): Likewise. (__arm_viwdupq_x_n_u32): Likewise. (__arm_viwdupq_x_wb_u8): Likewise. (__arm_viwdupq_x_wb_u16): Likewise. (__arm_viwdupq_x_wb_u32): Likewise. (__arm_vdupq_x_n_s8): Likewise. (__arm_vdupq_x_n_s16): Likewise. (__arm_vdupq_x_n_s32): Likewise. (__arm_vdupq_x_n_u8): Likewise. (__arm_vdupq_x_n_u16): Likewise. (__arm_vdupq_x_n_u32): Likewise. (__arm_vminq_x_s8): Likewise. (__arm_vminq_x_s16): Likewise. (__arm_vminq_x_s32): Likewise. (__arm_vminq_x_u8): Likewise. (__arm_vminq_x_u16): Likewise. (__arm_vminq_x_u32): Likewise. (__arm_vmaxq_x_s8): Likewise. (__arm_vmaxq_x_s16): Likewise. (__arm_vmaxq_x_s32): Likewise. (__arm_vmaxq_x_u8): Likewise. (__arm_vmaxq_x_u16): Likewise. (__arm_vmaxq_x_u32): Likewise. (__arm_vabdq_x_s8): Likewise. (__arm_vabdq_x_s16): Likewise. (__arm_vabdq_x_s32): Likewise. (__arm_vabdq_x_u8): Likewise. (__arm_vabdq_x_u16): Likewise. (__arm_vabdq_x_u32): Likewise. (__arm_vabsq_x_s8): Likewise. (__arm_vabsq_x_s16): Likewise. (__arm_vabsq_x_s32): Likewise. (__arm_vaddq_x_s8): Likewise. (__arm_vaddq_x_s16): Likewise. (__arm_vaddq_x_s32): Likewise. (__arm_vaddq_x_n_s8): Likewise. (__arm_vaddq_x_n_s16): Likewise. (__arm_vaddq_x_n_s32): Likewise. (__arm_vaddq_x_u8): Likewise. (__arm_vaddq_x_u16): Likewise. (__arm_vaddq_x_u32): Likewise. (__arm_vaddq_x_n_u8): Likewise. (__arm_vaddq_x_n_u16): Likewise. (__arm_vaddq_x_n_u32): Likewise. (__arm_vclsq_x_s8): Likewise. (__arm_vclsq_x_s16): Likewise. (__arm_vclsq_x_s32): Likewise. (__arm_vclzq_x_s8): Likewise. (__arm_vclzq_x_s16): Likewise. (__arm_vclzq_x_s32): Likewise. (__arm_vclzq_x_u8): Likewise. (__arm_vclzq_x_u16): Likewise. (__arm_vclzq_x_u32): Likewise. (__arm_vnegq_x_s8): Likewise. (__arm_vnegq_x_s16): Likewise. (__arm_vnegq_x_s32): Likewise. (__arm_vmulhq_x_s8): Likewise. (__arm_vmulhq_x_s16): Likewise. (__arm_vmulhq_x_s32): Likewise. (__arm_vmulhq_x_u8): Likewise. (__arm_vmulhq_x_u16): Likewise. (__arm_vmulhq_x_u32): Likewise. (__arm_vmullbq_poly_x_p8): Likewise. (__arm_vmullbq_poly_x_p16): Likewise. (__arm_vmullbq_int_x_s8): Likewise. (__arm_vmullbq_int_x_s16): Likewise. (__arm_vmullbq_int_x_s32): Likewise. (__arm_vmullbq_int_x_u8): Likewise. (__arm_vmullbq_int_x_u16): Likewise. (__arm_vmullbq_int_x_u32): Likewise. (__arm_vmulltq_poly_x_p8): Likewise. (__arm_vmulltq_poly_x_p16): Likewise. (__arm_vmulltq_int_x_s8): Likewise. (__arm_vmulltq_int_x_s16): Likewise. (__arm_vmulltq_int_x_s32): Likewise. (__arm_vmulltq_int_x_u8): Likewise. (__arm_vmulltq_int_x_u16): Likewise. (__arm_vmulltq_int_x_u32): Likewise. (__arm_vmulq_x_s8): Likewise. (__arm_vmulq_x_s16): Likewise. (__arm_vmulq_x_s32): Likewise. (__arm_vmulq_x_n_s8): Likewise. (__arm_vmulq_x_n_s16): Likewise. (__arm_vmulq_x_n_s32): Likewise. (__arm_vmulq_x_u8): Likewise. (__arm_vmulq_x_u16): Likewise. (__arm_vmulq_x_u32): Likewise. (__arm_vmulq_x_n_u8): Likewise. (__arm_vmulq_x_n_u16): Likewise. (__arm_vmulq_x_n_u32): Likewise. (__arm_vsubq_x_s8): Likewise. (__arm_vsubq_x_s16): Likewise. (__arm_vsubq_x_s32): Likewise. (__arm_vsubq_x_n_s8): Likewise. (__arm_vsubq_x_n_s16): Likewise. (__arm_vsubq_x_n_s32): Likewise. (__arm_vsubq_x_u8): Likewise. (__arm_vsubq_x_u16): Likewise. (__arm_vsubq_x_u32): Likewise. (__arm_vsubq_x_n_u8): Likewise. (__arm_vsubq_x_n_u16): Likewise. (__arm_vsubq_x_n_u32): Likewise. (__arm_vcaddq_rot90_x_s8): Likewise. (__arm_vcaddq_rot90_x_s16): Likewise. (__arm_vcaddq_rot90_x_s32): Likewise. (__arm_vcaddq_rot90_x_u8): Likewise. (__arm_vcaddq_rot90_x_u16): Likewise. (__arm_vcaddq_rot90_x_u32): Likewise. (__arm_vcaddq_rot270_x_s8): Likewise. (__arm_vcaddq_rot270_x_s16): Likewise. (__arm_vcaddq_rot270_x_s32): Likewise. (__arm_vcaddq_rot270_x_u8): Likewise. (__arm_vcaddq_rot270_x_u16): Likewise. (__arm_vcaddq_rot270_x_u32): Likewise. (__arm_vhaddq_x_n_s8): Likewise. (__arm_vhaddq_x_n_s16): Likewise. (__arm_vhaddq_x_n_s32): Likewise. (__arm_vhaddq_x_n_u8): Likewise. (__arm_vhaddq_x_n_u16): Likewise. (__arm_vhaddq_x_n_u32): Likewise. (__arm_vhaddq_x_s8): Likewise. (__arm_vhaddq_x_s16): Likewise. (__arm_vhaddq_x_s32): Likewise. (__arm_vhaddq_x_u8): Likewise. (__arm_vhaddq_x_u16): Likewise. (__arm_vhaddq_x_u32): Likewise. (__arm_vhcaddq_rot90_x_s8): Likewise. (__arm_vhcaddq_rot90_x_s16): Likewise. (__arm_vhcaddq_rot90_x_s32): Likewise. (__arm_vhcaddq_rot270_x_s8): Likewise. (__arm_vhcaddq_rot270_x_s16): Likewise. (__arm_vhcaddq_rot270_x_s32): Likewise. (__arm_vhsubq_x_n_s8): Likewise. (__arm_vhsubq_x_n_s16): Likewise. (__arm_vhsubq_x_n_s32): Likewise. (__arm_vhsubq_x_n_u8): Likewise. (__arm_vhsubq_x_n_u16): Likewise. (__arm_vhsubq_x_n_u32): Likewise. (__arm_vhsubq_x_s8): Likewise. (__arm_vhsubq_x_s16): Likewise. (__arm_vhsubq_x_s32): Likewise. (__arm_vhsubq_x_u8): Likewise. (__arm_vhsubq_x_u16): Likewise. (__arm_vhsubq_x_u32): Likewise. (__arm_vrhaddq_x_s8): Likewise. (__arm_vrhaddq_x_s16): Likewise. (__arm_vrhaddq_x_s32): Likewise. (__arm_vrhaddq_x_u8): Likewise. (__arm_vrhaddq_x_u16): Likewise. (__arm_vrhaddq_x_u32): Likewise. (__arm_vrmulhq_x_s8): Likewise. (__arm_vrmulhq_x_s16): Likewise. (__arm_vrmulhq_x_s32): Likewise. (__arm_vrmulhq_x_u8): Likewise. (__arm_vrmulhq_x_u16): Likewise. (__arm_vrmulhq_x_u32): Likewise. (__arm_vandq_x_s8): Likewise. (__arm_vandq_x_s16): Likewise. (__arm_vandq_x_s32): Likewise. (__arm_vandq_x_u8): Likewise. (__arm_vandq_x_u16): Likewise. (__arm_vandq_x_u32): Likewise. (__arm_vbicq_x_s8): Likewise. (__arm_vbicq_x_s16): Likewise. (__arm_vbicq_x_s32): Likewise. (__arm_vbicq_x_u8): Likewise. (__arm_vbicq_x_u16): Likewise. (__arm_vbicq_x_u32): Likewise. (__arm_vbrsrq_x_n_s8): Likewise. (__arm_vbrsrq_x_n_s16): Likewise. (__arm_vbrsrq_x_n_s32): Likewise. (__arm_vbrsrq_x_n_u8): Likewise. (__arm_vbrsrq_x_n_u16): Likewise. (__arm_vbrsrq_x_n_u32): Likewise. (__arm_veorq_x_s8): Likewise. (__arm_veorq_x_s16): Likewise. (__arm_veorq_x_s32): Likewise. (__arm_veorq_x_u8): Likewise. (__arm_veorq_x_u16): Likewise. (__arm_veorq_x_u32): Likewise. (__arm_vmovlbq_x_s8): Likewise. (__arm_vmovlbq_x_s16): Likewise. (__arm_vmovlbq_x_u8): Likewise. (__arm_vmovlbq_x_u16): Likewise. (__arm_vmovltq_x_s8): Likewise. (__arm_vmovltq_x_s16): Likewise. (__arm_vmovltq_x_u8): Likewise. (__arm_vmovltq_x_u16): Likewise. (__arm_vmvnq_x_s8): Likewise. (__arm_vmvnq_x_s16): Likewise. (__arm_vmvnq_x_s32): Likewise. (__arm_vmvnq_x_u8): Likewise. (__arm_vmvnq_x_u16): Likewise. (__arm_vmvnq_x_u32): Likewise. (__arm_vmvnq_x_n_s16): Likewise. (__arm_vmvnq_x_n_s32): Likewise. (__arm_vmvnq_x_n_u16): Likewise. (__arm_vmvnq_x_n_u32): Likewise. (__arm_vornq_x_s8): Likewise. (__arm_vornq_x_s16): Likewise. (__arm_vornq_x_s32): Likewise. (__arm_vornq_x_u8): Likewise. (__arm_vornq_x_u16): Likewise. (__arm_vornq_x_u32): Likewise. (__arm_vorrq_x_s8): Likewise. (__arm_vorrq_x_s16): Likewise. (__arm_vorrq_x_s32): Likewise. (__arm_vorrq_x_u8): Likewise. (__arm_vorrq_x_u16): Likewise. (__arm_vorrq_x_u32): Likewise. (__arm_vrev16q_x_s8): Likewise. (__arm_vrev16q_x_u8): Likewise. (__arm_vrev32q_x_s8): Likewise. (__arm_vrev32q_x_s16): Likewise. (__arm_vrev32q_x_u8): Likewise. (__arm_vrev32q_x_u16): Likewise. (__arm_vrev64q_x_s8): Likewise. (__arm_vrev64q_x_s16): Likewise. (__arm_vrev64q_x_s32): Likewise. (__arm_vrev64q_x_u8): Likewise. (__arm_vrev64q_x_u16): Likewise. (__arm_vrev64q_x_u32): Likewise. (__arm_vrshlq_x_s8): Likewise. (__arm_vrshlq_x_s16): Likewise. (__arm_vrshlq_x_s32): Likewise. (__arm_vrshlq_x_u8): Likewise. (__arm_vrshlq_x_u16): Likewise. (__arm_vrshlq_x_u32): Likewise. (__arm_vshllbq_x_n_s8): Likewise. (__arm_vshllbq_x_n_s16): Likewise. (__arm_vshllbq_x_n_u8): Likewise. (__arm_vshllbq_x_n_u16): Likewise. (__arm_vshlltq_x_n_s8): Likewise. (__arm_vshlltq_x_n_s16): Likewise. (__arm_vshlltq_x_n_u8): Likewise. (__arm_vshlltq_x_n_u16): Likewise. (__arm_vshlq_x_s8): Likewise. (__arm_vshlq_x_s16): Likewise. (__arm_vshlq_x_s32): Likewise. (__arm_vshlq_x_u8): Likewise. (__arm_vshlq_x_u16): Likewise. (__arm_vshlq_x_u32): Likewise. (__arm_vshlq_x_n_s8): Likewise. (__arm_vshlq_x_n_s16): Likewise. (__arm_vshlq_x_n_s32): Likewise. (__arm_vshlq_x_n_u8): Likewise. (__arm_vshlq_x_n_u16): Likewise. (__arm_vshlq_x_n_u32): Likewise. (__arm_vrshrq_x_n_s8): Likewise. (__arm_vrshrq_x_n_s16): Likewise. (__arm_vrshrq_x_n_s32): Likewise. (__arm_vrshrq_x_n_u8): Likewise. (__arm_vrshrq_x_n_u16): Likewise. (__arm_vrshrq_x_n_u32): Likewise. (__arm_vshrq_x_n_s8): Likewise. (__arm_vshrq_x_n_s16): Likewise. (__arm_vshrq_x_n_s32): Likewise. (__arm_vshrq_x_n_u8): Likewise. (__arm_vshrq_x_n_u16): Likewise. (__arm_vshrq_x_n_u32): Likewise. (__arm_vdupq_x_n_f16): Likewise. (__arm_vdupq_x_n_f32): Likewise. (__arm_vminnmq_x_f16): Likewise. (__arm_vminnmq_x_f32): Likewise. (__arm_vmaxnmq_x_f16): Likewise. (__arm_vmaxnmq_x_f32): Likewise. (__arm_vabdq_x_f16): Likewise. (__arm_vabdq_x_f32): Likewise. (__arm_vabsq_x_f16): Likewise. (__arm_vabsq_x_f32): Likewise. (__arm_vaddq_x_f16): Likewise. (__arm_vaddq_x_f32): Likewise. (__arm_vaddq_x_n_f16): Likewise. (__arm_vaddq_x_n_f32): Likewise. (__arm_vnegq_x_f16): Likewise. (__arm_vnegq_x_f32): Likewise. (__arm_vmulq_x_f16): Likewise. (__arm_vmulq_x_f32): Likewise. (__arm_vmulq_x_n_f16): Likewise. (__arm_vmulq_x_n_f32): Likewise. (__arm_vsubq_x_f16): Likewise. (__arm_vsubq_x_f32): Likewise. (__arm_vsubq_x_n_f16): Likewise. (__arm_vsubq_x_n_f32): Likewise. (__arm_vcaddq_rot90_x_f16): Likewise. (__arm_vcaddq_rot90_x_f32): Likewise. (__arm_vcaddq_rot270_x_f16): Likewise. (__arm_vcaddq_rot270_x_f32): Likewise. (__arm_vcmulq_x_f16): Likewise. (__arm_vcmulq_x_f32): Likewise. (__arm_vcmulq_rot90_x_f16): Likewise. (__arm_vcmulq_rot90_x_f32): Likewise. (__arm_vcmulq_rot180_x_f16): Likewise. (__arm_vcmulq_rot180_x_f32): Likewise. (__arm_vcmulq_rot270_x_f16): Likewise. (__arm_vcmulq_rot270_x_f32): Likewise. (__arm_vcvtaq_x_s16_f16): Likewise. (__arm_vcvtaq_x_s32_f32): Likewise. (__arm_vcvtaq_x_u16_f16): Likewise. (__arm_vcvtaq_x_u32_f32): Likewise. (__arm_vcvtnq_x_s16_f16): Likewise. (__arm_vcvtnq_x_s32_f32): Likewise. (__arm_vcvtnq_x_u16_f16): Likewise. (__arm_vcvtnq_x_u32_f32): Likewise. (__arm_vcvtpq_x_s16_f16): Likewise. (__arm_vcvtpq_x_s32_f32): Likewise. (__arm_vcvtpq_x_u16_f16): Likewise. (__arm_vcvtpq_x_u32_f32): Likewise. (__arm_vcvtmq_x_s16_f16): Likewise. (__arm_vcvtmq_x_s32_f32): Likewise. (__arm_vcvtmq_x_u16_f16): Likewise. (__arm_vcvtmq_x_u32_f32): Likewise. (__arm_vcvtbq_x_f32_f16): Likewise. (__arm_vcvttq_x_f32_f16): Likewise. (__arm_vcvtq_x_f16_u16): Likewise. (__arm_vcvtq_x_f16_s16): Likewise. (__arm_vcvtq_x_f32_s32): Likewise. (__arm_vcvtq_x_f32_u32): Likewise. (__arm_vcvtq_x_n_f16_s16): Likewise. (__arm_vcvtq_x_n_f16_u16): Likewise. (__arm_vcvtq_x_n_f32_s32): Likewise. (__arm_vcvtq_x_n_f32_u32): Likewise. (__arm_vcvtq_x_s16_f16): Likewise. (__arm_vcvtq_x_s32_f32): Likewise. (__arm_vcvtq_x_u16_f16): Likewise. (__arm_vcvtq_x_u32_f32): Likewise. (__arm_vcvtq_x_n_s16_f16): Likewise. (__arm_vcvtq_x_n_s32_f32): Likewise. (__arm_vcvtq_x_n_u16_f16): Likewise. (__arm_vcvtq_x_n_u32_f32): Likewise. (__arm_vrndq_x_f16): Likewise. (__arm_vrndq_x_f32): Likewise. (__arm_vrndnq_x_f16): Likewise. (__arm_vrndnq_x_f32): Likewise. (__arm_vrndmq_x_f16): Likewise. (__arm_vrndmq_x_f32): Likewise. (__arm_vrndpq_x_f16): Likewise. (__arm_vrndpq_x_f32): Likewise. (__arm_vrndaq_x_f16): Likewise. (__arm_vrndaq_x_f32): Likewise. (__arm_vrndxq_x_f16): Likewise. (__arm_vrndxq_x_f32): Likewise. (__arm_vandq_x_f16): Likewise. (__arm_vandq_x_f32): Likewise. (__arm_vbicq_x_f16): Likewise. (__arm_vbicq_x_f32): Likewise. (__arm_vbrsrq_x_n_f16): Likewise. (__arm_vbrsrq_x_n_f32): Likewise. (__arm_veorq_x_f16): Likewise. (__arm_veorq_x_f32): Likewise. (__arm_vornq_x_f16): Likewise. (__arm_vornq_x_f32): Likewise. (__arm_vorrq_x_f16): Likewise. (__arm_vorrq_x_f32): Likewise. (__arm_vrev32q_x_f16): Likewise. (__arm_vrev64q_x_f16): Likewise. (__arm_vrev64q_x_f32): Likewise. (vabdq_x): Define polymorphic variant. (vabsq_x): Likewise. (vaddq_x): Likewise. (vandq_x): Likewise. (vbicq_x): Likewise. (vbrsrq_x): Likewise. (vcaddq_rot270_x): Likewise. (vcaddq_rot90_x): Likewise. (vcmulq_rot180_x): Likewise. (vcmulq_rot270_x): Likewise. (vcmulq_x): Likewise. (vcvtq_x): Likewise. (vcvtq_x_n): Likewise. (vcvtnq_m): Likewise. (veorq_x): Likewise. (vmaxnmq_x): Likewise. (vminnmq_x): Likewise. (vmulq_x): Likewise. (vnegq_x): Likewise. (vornq_x): Likewise. (vorrq_x): Likewise. (vrev32q_x): Likewise. (vrev64q_x): Likewise. (vrndaq_x): Likewise. (vrndmq_x): Likewise. (vrndnq_x): Likewise. (vrndpq_x): Likewise. (vrndq_x): Likewise. (vrndxq_x): Likewise. (vsubq_x): Likewise. (vcmulq_rot90_x): Likewise. (vadciq): Likewise. (vclsq_x): Likewise. (vclzq_x): Likewise. (vhaddq_x): Likewise. (vhcaddq_rot270_x): Likewise. (vhcaddq_rot90_x): Likewise. (vhsubq_x): Likewise. (vmaxq_x): Likewise. (vminq_x): Likewise. (vmovlbq_x): Likewise. (vmovltq_x): Likewise. (vmulhq_x): Likewise. (vmullbq_int_x): Likewise. (vmullbq_poly_x): Likewise. (vmulltq_int_x): Likewise. (vmulltq_poly_x): Likewise. (vmvnq_x): Likewise. (vrev16q_x): Likewise. (vrhaddq_x): Likewise. (vrmulhq_x): Likewise. (vrshlq_x): Likewise. (vrshrq_x): Likewise. (vshllbq_x): Likewise. (vshlltq_x): Likewise. (vshlq_x_n): Likewise. (vshlq_x): Likewise. (vdwdupq_x_u8): Likewise. (vdwdupq_x_u16): Likewise. (vdwdupq_x_u32): Likewise. (viwdupq_x_u8): Likewise. (viwdupq_x_u16): Likewise. (viwdupq_x_u32): Likewise. (vidupq_x_u8): Likewise. (vddupq_x_u8): Likewise. (vidupq_x_u16): Likewise. (vddupq_x_u16): Likewise. (vidupq_x_u32): Likewise. (vddupq_x_u32): Likewise. (vshrq_x): Likewise. 2020-03-20 Richard Biener * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts to vectorize for CTOR defs. 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin qualifier. (LDRGBWBU_QUALIFIERS): Likewise. (LDRGBWBS_Z_QUALIFIERS): Likewise. (LDRGBWBU_Z_QUALIFIERS): Likewise. (STRSBWBS_QUALIFIERS): Likewise. (STRSBWBU_QUALIFIERS): Likewise. (STRSBWBS_P_QUALIFIERS): Likewise. (STRSBWBU_P_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro. (vldrdq_gather_base_wb_u64): Likewise. (vldrdq_gather_base_wb_z_s64): Likewise. (vldrdq_gather_base_wb_z_u64): Likewise. (vldrwq_gather_base_wb_f32): Likewise. (vldrwq_gather_base_wb_s32): Likewise. (vldrwq_gather_base_wb_u32): Likewise. (vldrwq_gather_base_wb_z_f32): Likewise. (vldrwq_gather_base_wb_z_s32): Likewise. (vldrwq_gather_base_wb_z_u32): Likewise. (vstrdq_scatter_base_wb_p_s64): Likewise. (vstrdq_scatter_base_wb_p_u64): Likewise. (vstrdq_scatter_base_wb_s64): Likewise. (vstrdq_scatter_base_wb_u64): Likewise. (vstrwq_scatter_base_wb_p_s32): Likewise. (vstrwq_scatter_base_wb_p_f32): Likewise. (vstrwq_scatter_base_wb_p_u32): Likewise. (vstrwq_scatter_base_wb_s32): Likewise. (vstrwq_scatter_base_wb_u32): Likewise. (vstrwq_scatter_base_wb_f32): Likewise. (__arm_vldrdq_gather_base_wb_s64): Define intrinsic. (__arm_vldrdq_gather_base_wb_u64): Likewise. (__arm_vldrdq_gather_base_wb_z_s64): Likewise. (__arm_vldrdq_gather_base_wb_z_u64): Likewise. (__arm_vldrwq_gather_base_wb_s32): Likewise. (__arm_vldrwq_gather_base_wb_u32): Likewise. (__arm_vldrwq_gather_base_wb_z_s32): Likewise. (__arm_vldrwq_gather_base_wb_z_u32): Likewise. (__arm_vstrdq_scatter_base_wb_s64): Likewise. (__arm_vstrdq_scatter_base_wb_u64): Likewise. (__arm_vstrdq_scatter_base_wb_p_s64): Likewise. (__arm_vstrdq_scatter_base_wb_p_u64): Likewise. (__arm_vstrwq_scatter_base_wb_p_s32): Likewise. (__arm_vstrwq_scatter_base_wb_p_u32): Likewise. (__arm_vstrwq_scatter_base_wb_s32): Likewise. (__arm_vstrwq_scatter_base_wb_u32): Likewise. (__arm_vldrwq_gather_base_wb_f32): Likewise. (__arm_vldrwq_gather_base_wb_z_f32): Likewise. (__arm_vstrwq_scatter_base_wb_f32): Likewise. (__arm_vstrwq_scatter_base_wb_p_f32): Likewise. (vstrwq_scatter_base_wb): Define polymorphic variant. (vstrwq_scatter_base_wb_p): Likewise. (vstrdq_scatter_base_wb_p): Likewise. (vstrdq_scatter_base_wb): Likewise. * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin qualifier. * config/arm/mve.md (mve_vstrwq_scatter_base_wb_v4si): Define RTL pattern. (mve_vstrwq_scatter_base_wb_add_v4si): Likewise. (mve_vstrwq_scatter_base_wb_v4si_insn): Likewise. (mve_vstrwq_scatter_base_wb_p_v4si): Likewise. (mve_vstrwq_scatter_base_wb_p_add_v4si): Likewise. (mve_vstrwq_scatter_base_wb_p_v4si_insn): Likewise. (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise. (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise. (mve_vstrdq_scatter_base_wb_v2di): Likewise. (mve_vstrdq_scatter_base_wb_add_v2di): Likewise. (mve_vstrdq_scatter_base_wb_v2di_insn): Likewise. (mve_vstrdq_scatter_base_wb_p_v2di): Likewise. (mve_vstrdq_scatter_base_wb_p_add_v2di): Likewise. (mve_vstrdq_scatter_base_wb_p_v2di_insn): Likewise. (mve_vldrwq_gather_base_wb_v4si): Likewise. (mve_vldrwq_gather_base_wb_v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_z_v4si): Likewise. (mve_vldrwq_gather_base_wb_z_v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_fv4sf): Likewise. (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise. (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. (mve_vldrdq_gather_base_wb_v2di): Likewise. (mve_vldrdq_gather_base_wb_v2di_insn): Likewise. (mve_vldrdq_gather_base_wb_z_v2di): Likewise. (mve_vldrdq_gather_base_wb_z_v2di_insn): Likewise. 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm-builtins.c (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary builtin qualifier. * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro. (vddupq_m_n_u32): Likewise. (vddupq_m_n_u16): Likewise. (vddupq_m_wb_u8): Likewise. (vddupq_m_wb_u16): Likewise. (vddupq_m_wb_u32): Likewise. (vddupq_n_u8): Likewise. (vddupq_n_u32): Likewise. (vddupq_n_u16): Likewise. (vddupq_wb_u8): Likewise. (vddupq_wb_u16): Likewise. (vddupq_wb_u32): Likewise. (vdwdupq_m_n_u8): Likewise. (vdwdupq_m_n_u32): Likewise. (vdwdupq_m_n_u16): Likewise. (vdwdupq_m_wb_u8): Likewise. (vdwdupq_m_wb_u32): Likewise. (vdwdupq_m_wb_u16): Likewise. (vdwdupq_n_u8): Likewise. (vdwdupq_n_u32): Likewise. (vdwdupq_n_u16): Likewise. (vdwdupq_wb_u8): Likewise. (vdwdupq_wb_u32): Likewise. (vdwdupq_wb_u16): Likewise. (vidupq_m_n_u8): Likewise. (vidupq_m_n_u32): Likewise. (vidupq_m_n_u16): Likewise. (vidupq_m_wb_u8): Likewise. (vidupq_m_wb_u16): Likewise. (vidupq_m_wb_u32): Likewise. (vidupq_n_u8): Likewise. (vidupq_n_u32): Likewise. (vidupq_n_u16): Likewise. (vidupq_wb_u8): Likewise. (vidupq_wb_u16): Likewise. (vidupq_wb_u32): Likewise. (viwdupq_m_n_u8): Likewise. (viwdupq_m_n_u32): Likewise. (viwdupq_m_n_u16): Likewise. (viwdupq_m_wb_u8): Likewise. (viwdupq_m_wb_u32): Likewise. (viwdupq_m_wb_u16): Likewise. (viwdupq_n_u8): Likewise. (viwdupq_n_u32): Likewise. (viwdupq_n_u16): Likewise. (viwdupq_wb_u8): Likewise. (viwdupq_wb_u32): Likewise. (viwdupq_wb_u16): Likewise. (__arm_vddupq_m_n_u8): Define intrinsic. (__arm_vddupq_m_n_u32): Likewise. (__arm_vddupq_m_n_u16): Likewise. (__arm_vddupq_m_wb_u8): Likewise. (__arm_vddupq_m_wb_u16): Likewise. (__arm_vddupq_m_wb_u32): Likewise. (__arm_vddupq_n_u8): Likewise. (__arm_vddupq_n_u32): Likewise. (__arm_vddupq_n_u16): Likewise. (__arm_vdwdupq_m_n_u8): Likewise. (__arm_vdwdupq_m_n_u32): Likewise. (__arm_vdwdupq_m_n_u16): Likewise. (__arm_vdwdupq_m_wb_u8): Likewise. (__arm_vdwdupq_m_wb_u32): Likewise. (__arm_vdwdupq_m_wb_u16): Likewise. (__arm_vdwdupq_n_u8): Likewise. (__arm_vdwdupq_n_u32): Likewise. (__arm_vdwdupq_n_u16): Likewise. (__arm_vdwdupq_wb_u8): Likewise. (__arm_vdwdupq_wb_u32): Likewise. (__arm_vdwdupq_wb_u16): Likewise. (__arm_vidupq_m_n_u8): Likewise. (__arm_vidupq_m_n_u32): Likewise. (__arm_vidupq_m_n_u16): Likewise. (__arm_vidupq_n_u8): Likewise. (__arm_vidupq_m_wb_u8): Likewise. (__arm_vidupq_m_wb_u16): Likewise. (__arm_vidupq_m_wb_u32): Likewise. (__arm_vidupq_n_u32): Likewise. (__arm_vidupq_n_u16): Likewise. (__arm_vidupq_wb_u8): Likewise. (__arm_vidupq_wb_u16): Likewise. (__arm_vidupq_wb_u32): Likewise. (__arm_vddupq_wb_u8): Likewise. (__arm_vddupq_wb_u16): Likewise. (__arm_vddupq_wb_u32): Likewise. (__arm_viwdupq_m_n_u8): Likewise. (__arm_viwdupq_m_n_u32): Likewise. (__arm_viwdupq_m_n_u16): Likewise. (__arm_viwdupq_m_wb_u8): Likewise. (__arm_viwdupq_m_wb_u32): Likewise. (__arm_viwdupq_m_wb_u16): Likewise. (__arm_viwdupq_n_u8): Likewise. (__arm_viwdupq_n_u32): Likewise. (__arm_viwdupq_n_u16): Likewise. (__arm_viwdupq_wb_u8): Likewise. (__arm_viwdupq_wb_u32): Likewise. (__arm_viwdupq_wb_u16): Likewise. (vidupq_m): Define polymorphic variant. (vddupq_m): Likewise. (vidupq_u16): Likewise. (vidupq_u32): Likewise. (vidupq_u8): Likewise. (vddupq_u16): Likewise. (vddupq_u32): Likewise. (vddupq_u8): Likewise. (viwdupq_m): Likewise. (viwdupq_u16): Likewise. (viwdupq_u32): Likewise. (viwdupq_u8): Likewise. (vdwdupq_m): Likewise. (vdwdupq_u16): Likewise. (vdwdupq_u32): Likewise. (vdwdupq_u8): Likewise. * config/arm/arm_mve_builtins.def (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin qualifier. * config/arm/mve.md (mve_vidupq_n_u): Define RTL pattern. (mve_vidupq_u_insn): Likewise. (mve_vidupq_m_n_u): Likewise. (mve_vidupq_m_wb_u_insn): Likewise. (mve_vddupq_n_u): Likewise. (mve_vddupq_u_insn): Likewise. (mve_vddupq_m_n_u): Likewise. (mve_vddupq_m_wb_u_insn): Likewise. (mve_vdwdupq_n_u): Likewise. (mve_vdwdupq_wb_u): Likewise. (mve_vdwdupq_wb_u_insn): Likewise. (mve_vdwdupq_m_n_u): Likewise. (mve_vdwdupq_m_wb_u): Likewise. (mve_vdwdupq_m_wb_u_insn): Likewise. (mve_viwdupq_n_u): Likewise. (mve_viwdupq_wb_u): Likewise. (mve_viwdupq_wb_u_insn): Likewise. (mve_viwdupq_m_n_u): Likewise. (mve_viwdupq_m_wb_u): Likewise. (mve_viwdupq_m_wb_u_insn): Likewise. 2020-03-20 Srinath Parvathaneni * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro. (vreinterpretq_s16_s64): Likewise. (vreinterpretq_s16_s8): Likewise. (vreinterpretq_s16_u16): Likewise. (vreinterpretq_s16_u32): Likewise. (vreinterpretq_s16_u64): Likewise. (vreinterpretq_s16_u8): Likewise. (vreinterpretq_s32_s16): Likewise. (vreinterpretq_s32_s64): Likewise. (vreinterpretq_s32_s8): Likewise. (vreinterpretq_s32_u16): Likewise. (vreinterpretq_s32_u32): Likewise. (vreinterpretq_s32_u64): Likewise. (vreinterpretq_s32_u8): Likewise. (vreinterpretq_s64_s16): Likewise. (vreinterpretq_s64_s32): Likewise. (vreinterpretq_s64_s8): Likewise. (vreinterpretq_s64_u16): Likewise. (vreinterpretq_s64_u32): Likewise. (vreinterpretq_s64_u64): Likewise. (vreinterpretq_s64_u8): Likewise. (vreinterpretq_s8_s16): Likewise. (vreinterpretq_s8_s32): Likewise. (vreinterpretq_s8_s64): Likewise. (vreinterpretq_s8_u16): Likewise. (vreinterpretq_s8_u32): Likewise. (vreinterpretq_s8_u64): Likewise. (vreinterpretq_s8_u8): Likewise. (vreinterpretq_u16_s16): Likewise. (vreinterpretq_u16_s32): Likewise. (vreinterpretq_u16_s64): Likewise. (vreinterpretq_u16_s8): Likewise. (vreinterpretq_u16_u32): Likewise. (vreinterpretq_u16_u64): Likewise. (vreinterpretq_u16_u8): Likewise. (vreinterpretq_u32_s16): Likewise. (vreinterpretq_u32_s32): Likewise. (vreinterpretq_u32_s64): Likewise. (vreinterpretq_u32_s8): Likewise. (vreinterpretq_u32_u16): Likewise. (vreinterpretq_u32_u64): Likewise. (vreinterpretq_u32_u8): Likewise. (vreinterpretq_u64_s16): Likewise. (vreinterpretq_u64_s32): Likewise. (vreinterpretq_u64_s64): Likewise. (vreinterpretq_u64_s8): Likewise. (vreinterpretq_u64_u16): Likewise. (vreinterpretq_u64_u32): Likewise. (vreinterpretq_u64_u8): Likewise. (vreinterpretq_u8_s16): Likewise. (vreinterpretq_u8_s32): Likewise. (vreinterpretq_u8_s64): Likewise. (vreinterpretq_u8_s8): Likewise. (vreinterpretq_u8_u16): Likewise. (vreinterpretq_u8_u32): Likewise. (vreinterpretq_u8_u64): Likewise. (vreinterpretq_s32_f16): Likewise. (vreinterpretq_s32_f32): Likewise. (vreinterpretq_u16_f16): Likewise. (vreinterpretq_u16_f32): Likewise. (vreinterpretq_u32_f16): Likewise. (vreinterpretq_u32_f32): Likewise. (vreinterpretq_u64_f16): Likewise. (vreinterpretq_u64_f32): Likewise. (vreinterpretq_u8_f16): Likewise. (vreinterpretq_u8_f32): Likewise. (vreinterpretq_f16_f32): Likewise. (vreinterpretq_f16_s16): Likewise. (vreinterpretq_f16_s32): Likewise. (vreinterpretq_f16_s64): Likewise. (vreinterpretq_f16_s8): Likewise. (vreinterpretq_f16_u16): Likewise. (vreinterpretq_f16_u32): Likewise. (vreinterpretq_f16_u64): Likewise. (vreinterpretq_f16_u8): Likewise. (vreinterpretq_f32_f16): Likewise. (vreinterpretq_f32_s16): Likewise. (vreinterpretq_f32_s32): Likewise. (vreinterpretq_f32_s64): Likewise. (vreinterpretq_f32_s8): Likewise. (vreinterpretq_f32_u16): Likewise. (vreinterpretq_f32_u32): Likewise. (vreinterpretq_f32_u64): Likewise. (vreinterpretq_f32_u8): Likewise. (vreinterpretq_s16_f16): Likewise. (vreinterpretq_s16_f32): Likewise. (vreinterpretq_s64_f16): Likewise. (vreinterpretq_s64_f32): Likewise. (vreinterpretq_s8_f16): Likewise. (vreinterpretq_s8_f32): Likewise. (vuninitializedq_u8): Likewise. (vuninitializedq_u16): Likewise. (vuninitializedq_u32): Likewise. (vuninitializedq_u64): Likewise. (vuninitializedq_s8): Likewise. (vuninitializedq_s16): Likewise. (vuninitializedq_s32): Likewise. (vuninitializedq_s64): Likewise. (vuninitializedq_f16): Likewise. (vuninitializedq_f32): Likewise. (__arm_vuninitializedq_u8): Define intrinsic. (__arm_vuninitializedq_u16): Likewise. (__arm_vuninitializedq_u32): Likewise. (__arm_vuninitializedq_u64): Likewise. (__arm_vuninitializedq_s8): Likewise. (__arm_vuninitializedq_s16): Likewise. (__arm_vuninitializedq_s32): Likewise. (__arm_vuninitializedq_s64): Likewise. (__arm_vreinterpretq_s16_s32): Likewise. (__arm_vreinterpretq_s16_s64): Likewise. (__arm_vreinterpretq_s16_s8): Likewise. (__arm_vreinterpretq_s16_u16): Likewise. (__arm_vreinterpretq_s16_u32): Likewise. (__arm_vreinterpretq_s16_u64): Likewise. (__arm_vreinterpretq_s16_u8): Likewise. (__arm_vreinterpretq_s32_s16): Likewise. (__arm_vreinterpretq_s32_s64): Likewise. (__arm_vreinterpretq_s32_s8): Likewise. (__arm_vreinterpretq_s32_u16): Likewise. (__arm_vreinterpretq_s32_u32): Likewise. (__arm_vreinterpretq_s32_u64): Likewise. (__arm_vreinterpretq_s32_u8): Likewise. (__arm_vreinterpretq_s64_s16): Likewise. (__arm_vreinterpretq_s64_s32): Likewise. (__arm_vreinterpretq_s64_s8): Likewise. (__arm_vreinterpretq_s64_u16): Likewise. (__arm_vreinterpretq_s64_u32): Likewise. (__arm_vreinterpretq_s64_u64): Likewise. (__arm_vreinterpretq_s64_u8): Likewise. (__arm_vreinterpretq_s8_s16): Likewise. (__arm_vreinterpretq_s8_s32): Likewise. (__arm_vreinterpretq_s8_s64): Likewise. (__arm_vreinterpretq_s8_u16): Likewise. (__arm_vreinterpretq_s8_u32): Likewise. (__arm_vreinterpretq_s8_u64): Likewise. (__arm_vreinterpretq_s8_u8): Likewise. (__arm_vreinterpretq_u16_s16): Likewise. (__arm_vreinterpretq_u16_s32): Likewise. (__arm_vreinterpretq_u16_s64): Likewise. (__arm_vreinterpretq_u16_s8): Likewise. (__arm_vreinterpretq_u16_u32): Likewise. (__arm_vreinterpretq_u16_u64): Likewise. (__arm_vreinterpretq_u16_u8): Likewise. (__arm_vreinterpretq_u32_s16): Likewise. (__arm_vreinterpretq_u32_s32): Likewise. (__arm_vreinterpretq_u32_s64): Likewise. (__arm_vreinterpretq_u32_s8): Likewise. (__arm_vreinterpretq_u32_u16): Likewise. (__arm_vreinterpretq_u32_u64): Likewise. (__arm_vreinterpretq_u32_u8): Likewise. (__arm_vreinterpretq_u64_s16): Likewise. (__arm_vreinterpretq_u64_s32): Likewise. (__arm_vreinterpretq_u64_s64): Likewise. (__arm_vreinterpretq_u64_s8): Likewise. (__arm_vreinterpretq_u64_u16): Likewise. (__arm_vreinterpretq_u64_u32): Likewise. (__arm_vreinterpretq_u64_u8): Likewise. (__arm_vreinterpretq_u8_s16): Likewise. (__arm_vreinterpretq_u8_s32): Likewise. (__arm_vreinterpretq_u8_s64): Likewise. (__arm_vreinterpretq_u8_s8): Likewise. (__arm_vreinterpretq_u8_u16): Likewise. (__arm_vreinterpretq_u8_u32): Likewise. (__arm_vreinterpretq_u8_u64): Likewise. (__arm_vuninitializedq_f16): Likewise. (__arm_vuninitializedq_f32): Likewise. (__arm_vreinterpretq_s32_f16): Likewise. (__arm_vreinterpretq_s32_f32): Likewise. (__arm_vreinterpretq_s16_f16): Likewise. (__arm_vreinterpretq_s16_f32): Likewise. (__arm_vreinterpretq_s64_f16): Likewise. (__arm_vreinterpretq_s64_f32): Likewise. (__arm_vreinterpretq_s8_f16): Likewise. (__arm_vreinterpretq_s8_f32): Likewise. (__arm_vreinterpretq_u16_f16): Likewise. (__arm_vreinterpretq_u16_f32): Likewise. (__arm_vreinterpretq_u32_f16): Likewise. (__arm_vreinterpretq_u32_f32): Likewise. (__arm_vreinterpretq_u64_f16): Likewise. (__arm_vreinterpretq_u64_f32): Likewise. (__arm_vreinterpretq_u8_f16): Likewise. (__arm_vreinterpretq_u8_f32): Likewise. (__arm_vreinterpretq_f16_f32): Likewise. (__arm_vreinterpretq_f16_s16): Likewise. (__arm_vreinterpretq_f16_s32): Likewise. (__arm_vreinterpretq_f16_s64): Likewise. (__arm_vreinterpretq_f16_s8): Likewise. (__arm_vreinterpretq_f16_u16): Likewise. (__arm_vreinterpretq_f16_u32): Likewise. (__arm_vreinterpretq_f16_u64): Likewise. (__arm_vreinterpretq_f16_u8): Likewise. (__arm_vreinterpretq_f32_f16): Likewise. (__arm_vreinterpretq_f32_s16): Likewise. (__arm_vreinterpretq_f32_s32): Likewise. (__arm_vreinterpretq_f32_s64): Likewise. (__arm_vreinterpretq_f32_s8): Likewise. (__arm_vreinterpretq_f32_u16): Likewise. (__arm_vreinterpretq_f32_u32): Likewise. (__arm_vreinterpretq_f32_u64): Likewise. (__arm_vreinterpretq_f32_u8): Likewise. (vuninitializedq): Define polymorphic variant. (vreinterpretq_f16): Likewise. (vreinterpretq_f32): Likewise. (vreinterpretq_s16): Likewise. (vreinterpretq_s32): Likewise. (vreinterpretq_s64): Likewise. (vreinterpretq_s8): Likewise. (vreinterpretq_u16): Likewise. (vreinterpretq_u32): Likewise. (vreinterpretq_u64): Likewise. (vreinterpretq_u8): Likewise. 2020-03-20 Srinath Parvathaneni Andre Vieira Mihail Ionescu * config/arm/arm_mve.h (vaddq_s8): Define macro. (vaddq_s16): Likewise. (vaddq_s32): Likewise. (vaddq_u8): Likewise. (vaddq_u16): Likewise. (vaddq_u32): Likewise. (vaddq_f16): Likewise. (vaddq_f32): Likewise. (__arm_vaddq_s8): Define intrinsic. (__arm_vaddq_s16): Likewise. (__arm_vaddq_s32): Likewise. (__arm_vaddq_u8): Likewise. (__arm_vaddq_u16): Likewise. (__arm_vaddq_u32): Likewise. (__arm_vaddq_f16): Likewise. (__arm_vaddq_f32): Likewise. (vaddq): Define polymorphic variant. * config/arm/iterators.md (VNIM): Define mode iterator for common types Neon, IWMMXT and MVE. (VNINOTM): Likewise. * config/arm/mve.md (mve_vaddq): Define RTL pattern. (mve_vaddq_f): Define RTL pattern. * config/arm/neon.md (add3): Rename to addv4hf3 RTL pattern. (addv8hf3_neon): Define RTL pattern. * config/arm/vec-common.md (add3): Modify standard add RTL pattern to support MVE. (addv8hf3): Define standard RTL pattern for MVE and Neon. (add3): Modify existing standard add RTL pattern for Neon and IWMMXT. 2020-03-20 Martin Liska PR ipa/94232 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously build_ref_for_offset function was used and it transforms off to bytes from bits. 2020-03-20 Richard Biener PR tree-optimization/94266 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the type of the underlying object to adjust for the containing field if available. 2020-03-20 Andre Vieira * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ... (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec. * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns. 2020-03-20 Andre Vieira * config/arm/mve.md (mve_mov): Fix R->R case. 2020-03-20 Jakub Jelinek PR tree-optimization/94224 * gimple-ssa-store-merging.c (imm_store_chain_info::coalesce_immediate): Don't consider overlapping or adjacent INTEGER_CST rhs_code stores as mergeable if they have different lp_nr. 2020-03-20 Andre Vieira * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve. 2020-03-19 Jan Hubicka PR ipa/94202 * cgraph.c (cgraph_node::function_symbol): Fix availability computation. (cgraph_node::function_or_virtual_thunk_symbol): Likewise. 2020-03-19 Jan Hubicka PR ipa/92372 * cgraphunit.c (process_function_and_variable_attributes): warn for flatten attribute on alias. * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias. 2020-03-19 Martin Liska * lto-section-in.c: Add ext_symtab. * lto-streamer-out.c (write_symbol_extension_info): New. (produce_symtab_extension): New. (produce_asm_for_decls): Stream also produce_symtab_extension. * lto-streamer.h (enum lto_section_type): New section. 2020-03-19 Jakub Jelinek PR tree-optimization/94211 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq instead of estimate_num_insns for bb_seq (middle_bb). Rename emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust all uses. 2020-03-19 Richard Biener PR ipa/94217 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr and build_ref_for_offset. 2020-03-19 Richard Biener PR middle-end/94216 * fold-const.c (fold_binary_loc): Avoid using build_fold_addr_expr when we really want an ADDR_EXPR. 2020-03-18 Segher Boessenkool * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented aliases for "wa". 2020-03-12 Richard Sandiford PR rtl-optimization/90275 * cse.c (cse_insn): Delete no-op register moves too. 2020-03-18 Martin Sebor PR ipa/92799 * cgraphunit.c (process_function_and_variable_attributes): Also complain about weakref function definitions and drop all effects of the attribute. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro. (vstrdq_scatter_base_p_u64): Likewise. (vstrdq_scatter_base_s64): Likewise. (vstrdq_scatter_base_u64): Likewise. (vstrdq_scatter_offset_p_s64): Likewise. (vstrdq_scatter_offset_p_u64): Likewise. (vstrdq_scatter_offset_s64): Likewise. (vstrdq_scatter_offset_u64): Likewise. (vstrdq_scatter_shifted_offset_p_s64): Likewise. (vstrdq_scatter_shifted_offset_p_u64): Likewise. (vstrdq_scatter_shifted_offset_s64): Likewise. (vstrdq_scatter_shifted_offset_u64): Likewise. (vstrhq_scatter_offset_f16): Likewise. (vstrhq_scatter_offset_p_f16): Likewise. (vstrhq_scatter_shifted_offset_f16): Likewise. (vstrhq_scatter_shifted_offset_p_f16): Likewise. (vstrwq_scatter_base_f32): Likewise. (vstrwq_scatter_base_p_f32): Likewise. (vstrwq_scatter_offset_f32): Likewise. (vstrwq_scatter_offset_p_f32): Likewise. (vstrwq_scatter_offset_p_s32): Likewise. (vstrwq_scatter_offset_p_u32): Likewise. (vstrwq_scatter_offset_s32): Likewise. (vstrwq_scatter_offset_u32): Likewise. (vstrwq_scatter_shifted_offset_f32): Likewise. (vstrwq_scatter_shifted_offset_p_f32): Likewise. (vstrwq_scatter_shifted_offset_p_s32): Likewise. (vstrwq_scatter_shifted_offset_p_u32): Likewise. (vstrwq_scatter_shifted_offset_s32): Likewise. (vstrwq_scatter_shifted_offset_u32): Likewise. (__arm_vstrdq_scatter_base_p_s64): Define intrinsic. (__arm_vstrdq_scatter_base_p_u64): Likewise. (__arm_vstrdq_scatter_base_s64): Likewise. (__arm_vstrdq_scatter_base_u64): Likewise. (__arm_vstrdq_scatter_offset_p_s64): Likewise. (__arm_vstrdq_scatter_offset_p_u64): Likewise. (__arm_vstrdq_scatter_offset_s64): Likewise. (__arm_vstrdq_scatter_offset_u64): Likewise. (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise. (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise. (__arm_vstrdq_scatter_shifted_offset_s64): Likewise. (__arm_vstrdq_scatter_shifted_offset_u64): Likewise. (__arm_vstrwq_scatter_offset_p_s32): Likewise. (__arm_vstrwq_scatter_offset_p_u32): Likewise. (__arm_vstrwq_scatter_offset_s32): Likewise. (__arm_vstrwq_scatter_offset_u32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise. (__arm_vstrwq_scatter_shifted_offset_s32): Likewise. (__arm_vstrwq_scatter_shifted_offset_u32): Likewise. (__arm_vstrhq_scatter_offset_f16): Likewise. (__arm_vstrhq_scatter_offset_p_f16): Likewise. (__arm_vstrhq_scatter_shifted_offset_f16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise. (__arm_vstrwq_scatter_base_f32): Likewise. (__arm_vstrwq_scatter_base_p_f32): Likewise. (__arm_vstrwq_scatter_offset_f32): Likewise. (__arm_vstrwq_scatter_offset_p_f32): Likewise. (__arm_vstrwq_scatter_shifted_offset_f32): Likewise. (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise. (vstrhq_scatter_offset): Define polymorphic variant. (vstrhq_scatter_offset_p): Likewise. (vstrhq_scatter_shifted_offset): Likewise. (vstrhq_scatter_shifted_offset_p): Likewise. (vstrwq_scatter_base): Likewise. (vstrwq_scatter_base_p): Likewise. (vstrwq_scatter_offset): Likewise. (vstrwq_scatter_offset_p): Likewise. (vstrwq_scatter_shifted_offset): Likewise. (vstrwq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_base_p): Likewise. (vstrdq_scatter_base): Likewise. (vstrdq_scatter_offset_p): Likewise. (vstrdq_scatter_offset): Likewise. (vstrdq_scatter_shifted_offset_p): Likewise. (vstrdq_scatter_shifted_offset): Likewise. * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier. (STRSBS_P): Likewise. (STRSBU): Likewise. (STRSBU_P): Likewise. (STRSS): Likewise. (STRSS_P): Likewise. (STRSU): Likewise. (STRSU_P): Likewise. * config/arm/constraints.md (Ri): Define. * config/arm/mve.md (VSTRDSBQ): Define iterator. (VSTRDSOQ): Likewise. (VSTRDSSOQ): Likewise. (VSTRWSOQ): Likewise. (VSTRWSSOQ): Likewise. (mve_vstrdq_scatter_base_p_v2di): Define RTL pattern. (mve_vstrdq_scatter_base_v2di): Likewise. (mve_vstrdq_scatter_offset_p_v2di): Likewise. (mve_vstrdq_scatter_offset_v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_p_v2di): Likewise. (mve_vstrdq_scatter_shifted_offset_v2di): Likewise. (mve_vstrhq_scatter_offset_fv8hf): Likewise. (mve_vstrhq_scatter_offset_p_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise. (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise. (mve_vstrwq_scatter_base_fv4sf): Likewise. (mve_vstrwq_scatter_base_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_p_v4si): Likewise. (mve_vstrwq_scatter_offset_v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise. (mve_vstrwq_scatter_shifted_offset_p_v4si): Likewise. (mve_vstrwq_scatter_shifted_offset_v4si): Likewise. * config/arm/predicates.md (Ri): Define predicate to check immediate is the range +/-1016 and multiple of 8. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vst1q_f32): Define macro. (vst1q_f16): Likewise. (vst1q_s8): Likewise. (vst1q_s32): Likewise. (vst1q_s16): Likewise. (vst1q_u8): Likewise. (vst1q_u32): Likewise. (vst1q_u16): Likewise. (vstrhq_f16): Likewise. (vstrhq_scatter_offset_s32): Likewise. (vstrhq_scatter_offset_s16): Likewise. (vstrhq_scatter_offset_u32): Likewise. (vstrhq_scatter_offset_u16): Likewise. (vstrhq_scatter_offset_p_s32): Likewise. (vstrhq_scatter_offset_p_s16): Likewise. (vstrhq_scatter_offset_p_u32): Likewise. (vstrhq_scatter_offset_p_u16): Likewise. (vstrhq_scatter_shifted_offset_s32): Likewise. (vstrhq_scatter_shifted_offset_s16): Likewise. (vstrhq_scatter_shifted_offset_u32): Likewise. (vstrhq_scatter_shifted_offset_u16): Likewise. (vstrhq_scatter_shifted_offset_p_s32): Likewise. (vstrhq_scatter_shifted_offset_p_s16): Likewise. (vstrhq_scatter_shifted_offset_p_u32): Likewise. (vstrhq_scatter_shifted_offset_p_u16): Likewise. (vstrhq_s32): Likewise. (vstrhq_s16): Likewise. (vstrhq_u32): Likewise. (vstrhq_u16): Likewise. (vstrhq_p_f16): Likewise. (vstrhq_p_s32): Likewise. (vstrhq_p_s16): Likewise. (vstrhq_p_u32): Likewise. (vstrhq_p_u16): Likewise. (vstrwq_f32): Likewise. (vstrwq_s32): Likewise. (vstrwq_u32): Likewise. (vstrwq_p_f32): Likewise. (vstrwq_p_s32): Likewise. (vstrwq_p_u32): Likewise. (__arm_vst1q_s8): Define intrinsic. (__arm_vst1q_s32): Likewise. (__arm_vst1q_s16): Likewise. (__arm_vst1q_u8): Likewise. (__arm_vst1q_u32): Likewise. (__arm_vst1q_u16): Likewise. (__arm_vstrhq_scatter_offset_s32): Likewise. (__arm_vstrhq_scatter_offset_s16): Likewise. (__arm_vstrhq_scatter_offset_u32): Likewise. (__arm_vstrhq_scatter_offset_u16): Likewise. (__arm_vstrhq_scatter_offset_p_s32): Likewise. (__arm_vstrhq_scatter_offset_p_s16): Likewise. (__arm_vstrhq_scatter_offset_p_u32): Likewise. (__arm_vstrhq_scatter_offset_p_u16): Likewise. (__arm_vstrhq_scatter_shifted_offset_s32): Likewise. (__arm_vstrhq_scatter_shifted_offset_s16): Likewise. (__arm_vstrhq_scatter_shifted_offset_u32): Likewise. (__arm_vstrhq_scatter_shifted_offset_u16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise. (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise. (__arm_vstrhq_s32): Likewise. (__arm_vstrhq_s16): Likewise. (__arm_vstrhq_u32): Likewise. (__arm_vstrhq_u16): Likewise. (__arm_vstrhq_p_s32): Likewise. (__arm_vstrhq_p_s16): Likewise. (__arm_vstrhq_p_u32): Likewise. (__arm_vstrhq_p_u16): Likewise. (__arm_vstrwq_s32): Likewise. (__arm_vstrwq_u32): Likewise. (__arm_vstrwq_p_s32): Likewise. (__arm_vstrwq_p_u32): Likewise. (__arm_vstrwq_p_f32): Likewise. (__arm_vstrwq_f32): Likewise. (__arm_vst1q_f32): Likewise. (__arm_vst1q_f16): Likewise. (__arm_vstrhq_f16): Likewise. (__arm_vstrhq_p_f16): Likewise. (vst1q): Define polymorphic variant. (vstrhq): Likewise. (vstrhq_p): Likewise. (vstrhq_scatter_offset_p): Likewise. (vstrhq_scatter_offset): Likewise. (vstrhq_scatter_shifted_offset_p): Likewise. (vstrhq_scatter_shifted_offset): Likewise. (vstrwq_p): Likewise. (vstrwq): Likewise. * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier. (STRS_P): Likewise. (STRSS): Likewise. (STRSS_P): Likewise. (STRSU): Likewise. (STRSU_P): Likewise. (STRU): Likewise. (STRU_P): Likewise. * config/arm/mve.md (VST1Q): Define iterator. (VSTRHSOQ): Likewise. (VSTRHSSOQ): Likewise. (VSTRHQ): Likewise. (VSTRWQ): Likewise. (mve_vstrhq_fv8hf): Define RTL pattern. (mve_vstrhq_p_fv8hf): Likewise. (mve_vstrhq_p_): Likewise. (mve_vstrhq_scatter_offset_p_): Likewise. (mve_vstrhq_scatter_offset_): Likewise. (mve_vstrhq_scatter_shifted_offset_p_): Likewise. (mve_vstrhq_scatter_shifted_offset_): Likewise. (mve_vstrhq_): Likewise. (mve_vstrwq_fv4sf): Likewise. (mve_vstrwq_p_fv4sf): Likewise. (mve_vstrwq_p_v4si): Likewise. (mve_vstrwq_v4si): Likewise. (mve_vst1q_f): Define expand. (mve_vst1q_): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16): Likewise. (vldrhq_gather_offset_s32): Likewise. (vldrhq_gather_offset_s16): Likewise. (vldrhq_gather_offset_u32): Likewise. (vldrhq_gather_offset_u16): Likewise. (vldrhq_gather_offset_z_s32): Likewise. (vldrhq_gather_offset_z_s16): Likewise. (vldrhq_gather_offset_z_u32): Likewise. (vldrhq_gather_offset_z_u16): Likewise. (vldrhq_gather_shifted_offset_s32): Likewise. (vldrhq_gather_shifted_offset_s16): Likewise. (vldrhq_gather_shifted_offset_u32): Likewise. (vldrhq_gather_shifted_offset_u16): Likewise. (vldrhq_gather_shifted_offset_z_s32): Likewise. (vldrhq_gather_shifted_offset_z_s16): Likewise. (vldrhq_gather_shifted_offset_z_u32): Likewise. (vldrhq_gather_shifted_offset_z_u16): Likewise. (vldrhq_s32): Likewise. (vldrhq_s16): Likewise. (vldrhq_u32): Likewise. (vldrhq_u16): Likewise. (vldrhq_z_s32): Likewise. (vldrhq_z_s16): Likewise. (vldrhq_z_u32): Likewise. (vldrhq_z_u16): Likewise. (vldrwq_s32): Likewise. (vldrwq_u32): Likewise. (vldrwq_z_s32): Likewise. (vldrwq_z_u32): Likewise. (vld1q_f32): Likewise. (vld1q_f16): Likewise. (vldrhq_f16): Likewise. (vldrhq_z_f16): Likewise. (vldrwq_f32): Likewise. (vldrwq_z_f32): Likewise. (__arm_vld1q_s8): Define intrinsic. (__arm_vld1q_s32): Likewise. (__arm_vld1q_s16): Likewise. (__arm_vld1q_u8): Likewise. (__arm_vld1q_u32): Likewise. (__arm_vld1q_u16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_s32): Likewise. (__arm_vldrhq_s16): Likewise. (__arm_vldrhq_u32): Likewise. (__arm_vldrhq_u16): Likewise. (__arm_vldrhq_z_s32): Likewise. (__arm_vldrhq_z_s16): Likewise. (__arm_vldrhq_z_u32): Likewise. (__arm_vldrhq_z_u16): Likewise. (__arm_vldrwq_s32): Likewise. (__arm_vldrwq_u32): Likewise. (__arm_vldrwq_z_s32): Likewise. (__arm_vldrwq_z_u32): Likewise. (__arm_vld1q_f32): Likewise. (__arm_vld1q_f16): Likewise. (__arm_vldrwq_f32): Likewise. (__arm_vldrwq_z_f32): Likewise. (__arm_vldrhq_z_f16): Likewise. (__arm_vldrhq_f16): Likewise. (vld1q): Define polymorphic variant. (vldrhq_gather_offset): Likewise. (vldrhq_gather_offset_z): Likewise. (vldrhq_gather_shifted_offset): Likewise. (vldrhq_gather_shifted_offset_z): Likewise. * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. (LDRS): Likewise. (LDRU_Z): Likewise. (LDRS_Z): Likewise. (LDRGU_Z): Likewise. (LDRGU): Likewise. (LDRGS_Z): Likewise. (LDRGS): Likewise. * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. (V_sz_elem1): Likewise. (VLD1Q): Define iterator. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (mve_vldrhq_fv8hf): Define RTL pattern. (mve_vldrhq_gather_offset_): Likewise. (mve_vldrhq_gather_offset_z_): Likewise. (mve_vldrhq_gather_shifted_offset_): Likewise. (mve_vldrhq_gather_shifted_offset_z_): Likewise. (mve_vldrhq_): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrhq_z_): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vldrwq_z_v4si): Likewise. (mve_vld1q_f): Define RTL expand pattern. (mve_vld1q_): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16): Likewise. (vldrhq_gather_offset_s32): Likewise. (vldrhq_gather_offset_s16): Likewise. (vldrhq_gather_offset_u32): Likewise. (vldrhq_gather_offset_u16): Likewise. (vldrhq_gather_offset_z_s32): Likewise. (vldrhq_gather_offset_z_s16): Likewise. (vldrhq_gather_offset_z_u32): Likewise. (vldrhq_gather_offset_z_u16): Likewise. (vldrhq_gather_shifted_offset_s32): Likewise. (vldrhq_gather_shifted_offset_s16): Likewise. (vldrhq_gather_shifted_offset_u32): Likewise. (vldrhq_gather_shifted_offset_u16): Likewise. (vldrhq_gather_shifted_offset_z_s32): Likewise. (vldrhq_gather_shifted_offset_z_s16): Likewise. (vldrhq_gather_shifted_offset_z_u32): Likewise. (vldrhq_gather_shifted_offset_z_u16): Likewise. (vldrhq_s32): Likewise. (vldrhq_s16): Likewise. (vldrhq_u32): Likewise. (vldrhq_u16): Likewise. (vldrhq_z_s32): Likewise. (vldrhq_z_s16): Likewise. (vldrhq_z_u32): Likewise. (vldrhq_z_u16): Likewise. (vldrwq_s32): Likewise. (vldrwq_u32): Likewise. (vldrwq_z_s32): Likewise. (vldrwq_z_u32): Likewise. (vld1q_f32): Likewise. (vld1q_f16): Likewise. (vldrhq_f16): Likewise. (vldrhq_z_f16): Likewise. (vldrwq_f32): Likewise. (vldrwq_z_f32): Likewise. (__arm_vld1q_s8): Define intrinsic. (__arm_vld1q_s32): Likewise. (__arm_vld1q_s16): Likewise. (__arm_vld1q_u8): Likewise. (__arm_vld1q_u32): Likewise. (__arm_vld1q_u16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_s32): Likewise. (__arm_vldrhq_s16): Likewise. (__arm_vldrhq_u32): Likewise. (__arm_vldrhq_u16): Likewise. (__arm_vldrhq_z_s32): Likewise. (__arm_vldrhq_z_s16): Likewise. (__arm_vldrhq_z_u32): Likewise. (__arm_vldrhq_z_u16): Likewise. (__arm_vldrwq_s32): Likewise. (__arm_vldrwq_u32): Likewise. (__arm_vldrwq_z_s32): Likewise. (__arm_vldrwq_z_u32): Likewise. (__arm_vld1q_f32): Likewise. (__arm_vld1q_f16): Likewise. (__arm_vldrwq_f32): Likewise. (__arm_vldrwq_z_f32): Likewise. (__arm_vldrhq_z_f16): Likewise. (__arm_vldrhq_f16): Likewise. (vld1q): Define polymorphic variant. (vldrhq_gather_offset): Likewise. (vldrhq_gather_offset_z): Likewise. (vldrhq_gather_shifted_offset): Likewise. (vldrhq_gather_shifted_offset_z): Likewise. * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. (LDRS): Likewise. (LDRU_Z): Likewise. (LDRS_Z): Likewise. (LDRGU_Z): Likewise. (LDRGU): Likewise. (LDRGS_Z): Likewise. (LDRGS): Likewise. * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. (V_sz_elem1): Likewise. (VLD1Q): Define iterator. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (mve_vldrhq_fv8hf): Define RTL pattern. (mve_vldrhq_gather_offset_): Likewise. (mve_vldrhq_gather_offset_z_): Likewise. (mve_vldrhq_gather_shifted_offset_): Likewise. (mve_vldrhq_gather_shifted_offset_z_): Likewise. (mve_vldrhq_): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrhq_z_): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vldrwq_z_v4si): Likewise. (mve_vld1q_f): Define RTL expand pattern. (mve_vld1q_): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro. (vldrbq_gather_offset_z_u8): Likewise. (vldrbq_gather_offset_z_s32): Likewise. (vldrbq_gather_offset_z_u16): Likewise. (vldrbq_gather_offset_z_u32): Likewise. (vldrbq_gather_offset_z_s8): Likewise. (vldrbq_z_s16): Likewise. (vldrbq_z_u8): Likewise. (vldrbq_z_s8): Likewise. (vldrbq_z_s32): Likewise. (vldrbq_z_u16): Likewise. (vldrbq_z_u32): Likewise. (vldrwq_gather_base_z_u32): Likewise. (vldrwq_gather_base_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s8): Define intrinsic. (__arm_vldrbq_gather_offset_z_s32): Likewise. (__arm_vldrbq_gather_offset_z_s16): Likewise. (__arm_vldrbq_gather_offset_z_u8): Likewise. (__arm_vldrbq_gather_offset_z_u32): Likewise. (__arm_vldrbq_gather_offset_z_u16): Likewise. (__arm_vldrbq_z_s8): Likewise. (__arm_vldrbq_z_s32): Likewise. (__arm_vldrbq_z_s16): Likewise. (__arm_vldrbq_z_u8): Likewise. (__arm_vldrbq_z_u32): Likewise. (__arm_vldrbq_z_u16): Likewise. (__arm_vldrwq_gather_base_z_s32): Likewise. (__arm_vldrwq_gather_base_z_u32): Likewise. (vldrbq_gather_offset_z): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin qualifier. (LDRGBU_Z_QUALIFIERS): Likewise. (LDRGS_Z_QUALIFIERS): Likewise. (LDRGU_Z_QUALIFIERS): Likewise. (LDRS_Z_QUALIFIERS): Likewise. (LDRU_Z_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vldrbq_gather_offset_z_): Define RTL pattern. (mve_vldrbq_z_): Likewise. (mve_vldrwq_gather_base_z_v4si): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin qualifier. (STRU_P_QUALIFIERS): Likewise. (STRSU_P_QUALIFIERS): Likewise. (STRSS_P_QUALIFIERS): Likewise. (STRSBS_P_QUALIFIERS): Likewise. (STRSBU_P_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vstrbq_p_s8): Define macro. (vstrbq_p_s32): Likewise. (vstrbq_p_s16): Likewise. (vstrbq_p_u8): Likewise. (vstrbq_p_u32): Likewise. (vstrbq_p_u16): Likewise. (vstrbq_scatter_offset_p_s8): Likewise. (vstrbq_scatter_offset_p_s32): Likewise. (vstrbq_scatter_offset_p_s16): Likewise. (vstrbq_scatter_offset_p_u8): Likewise. (vstrbq_scatter_offset_p_u32): Likewise. (vstrbq_scatter_offset_p_u16): Likewise. (vstrwq_scatter_base_p_s32): Likewise. (vstrwq_scatter_base_p_u32): Likewise. (__arm_vstrbq_p_s8): Define intrinsic. (__arm_vstrbq_p_s32): Likewise. (__arm_vstrbq_p_s16): Likewise. (__arm_vstrbq_p_u8): Likewise. (__arm_vstrbq_p_u32): Likewise. (__arm_vstrbq_p_u16): Likewise. (__arm_vstrbq_scatter_offset_p_s8): Likewise. (__arm_vstrbq_scatter_offset_p_s32): Likewise. (__arm_vstrbq_scatter_offset_p_s16): Likewise. (__arm_vstrbq_scatter_offset_p_u8): Likewise. (__arm_vstrbq_scatter_offset_p_u32): Likewise. (__arm_vstrbq_scatter_offset_p_u16): Likewise. (__arm_vstrwq_scatter_base_p_s32): Likewise. (__arm_vstrwq_scatter_base_p_u32): Likewise. (vstrbq_p): Define polymorphic variant. (vstrbq_scatter_offset_p): Likewise. (vstrwq_scatter_base_p): Likewise. * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin qualifier. (STRU_P_QUALIFIERS): Likewise. (STRSU_P_QUALIFIERS): Likewise. (STRSS_P_QUALIFIERS): Likewise. (STRSBS_P_QUALIFIERS): Likewise. (STRSBU_P_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vstrbq_scatter_offset_p_): Define RTL pattern. (mve_vstrwq_scatter_base_p_v4si): Likewise. (mve_vstrbq_p_): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro. (vldrbq_gather_offset_s8): Likewise. (vldrbq_s8): Likewise. (vldrbq_u8): Likewise. (vldrbq_gather_offset_u16): Likewise. (vldrbq_gather_offset_s16): Likewise. (vldrbq_s16): Likewise. (vldrbq_u16): Likewise. (vldrbq_gather_offset_u32): Likewise. (vldrbq_gather_offset_s32): Likewise. (vldrbq_s32): Likewise. (vldrbq_u32): Likewise. (vldrwq_gather_base_s32): Likewise. (vldrwq_gather_base_u32): Likewise. (__arm_vldrbq_gather_offset_u8): Define intrinsic. (__arm_vldrbq_gather_offset_s8): Likewise. (__arm_vldrbq_s8): Likewise. (__arm_vldrbq_u8): Likewise. (__arm_vldrbq_gather_offset_u16): Likewise. (__arm_vldrbq_gather_offset_s16): Likewise. (__arm_vldrbq_s16): Likewise. (__arm_vldrbq_u16): Likewise. (__arm_vldrbq_gather_offset_u32): Likewise. (__arm_vldrbq_gather_offset_s32): Likewise. (__arm_vldrbq_s32): Likewise. (__arm_vldrbq_u32): Likewise. (__arm_vldrwq_gather_base_s32): Likewise. (__arm_vldrwq_gather_base_u32): Likewise. (vldrbq_gather_offset): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/mve.md (VLDRBGOQ): Define iterator. (VLDRBQ): Likewise. (VLDRWGBQ): Likewise. (mve_vldrbq_gather_offset_): Define RTL pattern. (mve_vldrbq_): Likewise. (mve_vldrwq_gather_base_v4si): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vstrbq_s8): Define macro. (vstrbq_u8): Likewise. (vstrbq_u16): Likewise. (vstrbq_scatter_offset_s8): Likewise. (vstrbq_scatter_offset_u8): Likewise. (vstrbq_scatter_offset_u16): Likewise. (vstrbq_s16): Likewise. (vstrbq_u32): Likewise. (vstrbq_scatter_offset_s16): Likewise. (vstrbq_scatter_offset_u32): Likewise. (vstrbq_s32): Likewise. (vstrbq_scatter_offset_s32): Likewise. (vstrwq_scatter_base_s32): Likewise. (vstrwq_scatter_base_u32): Likewise. (__arm_vstrbq_scatter_offset_s8): Define intrinsic. (__arm_vstrbq_scatter_offset_s32): Likewise. (__arm_vstrbq_scatter_offset_s16): Likewise. (__arm_vstrbq_scatter_offset_u8): Likewise. (__arm_vstrbq_scatter_offset_u32): Likewise. (__arm_vstrbq_scatter_offset_u16): Likewise. (__arm_vstrbq_s8): Likewise. (__arm_vstrbq_s32): Likewise. (__arm_vstrbq_s16): Likewise. (__arm_vstrbq_u8): Likewise. (__arm_vstrbq_u32): Likewise. (__arm_vstrbq_u16): Likewise. (__arm_vstrwq_scatter_base_s32): Likewise. (__arm_vstrwq_scatter_base_u32): Likewise. (vstrbq): Define polymorphic variant. (vstrbq_scatter_offset): Likewise. (vstrwq_scatter_base): Likewise. * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin qualifier. (STRU_QUALIFIERS): Likewise. (STRSS_QUALIFIERS): Likewise. (STRSU_QUALIFIERS): Likewise. (STRSBS_QUALIFIERS): Likewise. (STRSBU_QUALIFIERS): Likewise. * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator. (VSTRWSBQ): Define iterators. (VSTRBSOQ): Likewise. (VSTRBQ): Likewise. (mve_vstrbq_): Define RTL pattern. (mve_vstrbq_scatter_offset_): Likewise. (mve_vstrwq_scatter_base_v4si): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vabdq_m_f32): Define macro. (vabdq_m_f16): Likewise. (vaddq_m_f32): Likewise. (vaddq_m_f16): Likewise. (vaddq_m_n_f32): Likewise. (vaddq_m_n_f16): Likewise. (vandq_m_f32): Likewise. (vandq_m_f16): Likewise. (vbicq_m_f32): Likewise. (vbicq_m_f16): Likewise. (vbrsrq_m_n_f32): Likewise. (vbrsrq_m_n_f16): Likewise. (vcaddq_rot270_m_f32): Likewise. (vcaddq_rot270_m_f16): Likewise. (vcaddq_rot90_m_f32): Likewise. (vcaddq_rot90_m_f16): Likewise. (vcmlaq_m_f32): Likewise. (vcmlaq_m_f16): Likewise. (vcmlaq_rot180_m_f32): Likewise. (vcmlaq_rot180_m_f16): Likewise. (vcmlaq_rot270_m_f32): Likewise. (vcmlaq_rot270_m_f16): Likewise. (vcmlaq_rot90_m_f32): Likewise. (vcmlaq_rot90_m_f16): Likewise. (vcmulq_m_f32): Likewise. (vcmulq_m_f16): Likewise. (vcmulq_rot180_m_f32): Likewise. (vcmulq_rot180_m_f16): Likewise. (vcmulq_rot270_m_f32): Likewise. (vcmulq_rot270_m_f16): Likewise. (vcmulq_rot90_m_f32): Likewise. (vcmulq_rot90_m_f16): Likewise. (vcvtq_m_n_s32_f32): Likewise. (vcvtq_m_n_s16_f16): Likewise. (vcvtq_m_n_u32_f32): Likewise. (vcvtq_m_n_u16_f16): Likewise. (veorq_m_f32): Likewise. (veorq_m_f16): Likewise. (vfmaq_m_f32): Likewise. (vfmaq_m_f16): Likewise. (vfmaq_m_n_f32): Likewise. (vfmaq_m_n_f16): Likewise. (vfmasq_m_n_f32): Likewise. (vfmasq_m_n_f16): Likewise. (vfmsq_m_f32): Likewise. (vfmsq_m_f16): Likewise. (vmaxnmq_m_f32): Likewise. (vmaxnmq_m_f16): Likewise. (vminnmq_m_f32): Likewise. (vminnmq_m_f16): Likewise. (vmulq_m_f32): Likewise. (vmulq_m_f16): Likewise. (vmulq_m_n_f32): Likewise. (vmulq_m_n_f16): Likewise. (vornq_m_f32): Likewise. (vornq_m_f16): Likewise. (vorrq_m_f32): Likewise. (vorrq_m_f16): Likewise. (vsubq_m_f32): Likewise. (vsubq_m_f16): Likewise. (vsubq_m_n_f32): Likewise. (vsubq_m_n_f16): Likewise. (__attribute__): Likewise. (__arm_vabdq_m_f32): Likewise. (__arm_vabdq_m_f16): Likewise. (__arm_vaddq_m_f32): Likewise. (__arm_vaddq_m_f16): Likewise. (__arm_vaddq_m_n_f32): Likewise. (__arm_vaddq_m_n_f16): Likewise. (__arm_vandq_m_f32): Likewise. (__arm_vandq_m_f16): Likewise. (__arm_vbicq_m_f32): Likewise. (__arm_vbicq_m_f16): Likewise. (__arm_vbrsrq_m_n_f32): Likewise. (__arm_vbrsrq_m_n_f16): Likewise. (__arm_vcaddq_rot270_m_f32): Likewise. (__arm_vcaddq_rot270_m_f16): Likewise. (__arm_vcaddq_rot90_m_f32): Likewise. (__arm_vcaddq_rot90_m_f16): Likewise. (__arm_vcmlaq_m_f32): Likewise. (__arm_vcmlaq_m_f16): Likewise. (__arm_vcmlaq_rot180_m_f32): Likewise. (__arm_vcmlaq_rot180_m_f16): Likewise. (__arm_vcmlaq_rot270_m_f32): Likewise. (__arm_vcmlaq_rot270_m_f16): Likewise. (__arm_vcmlaq_rot90_m_f32): Likewise. (__arm_vcmlaq_rot90_m_f16): Likewise. (__arm_vcmulq_m_f32): Likewise. (__arm_vcmulq_m_f16): Likewise. (__arm_vcmulq_rot180_m_f32): Define intrinsic. (__arm_vcmulq_rot180_m_f16): Likewise. (__arm_vcmulq_rot270_m_f32): Likewise. (__arm_vcmulq_rot270_m_f16): Likewise. (__arm_vcmulq_rot90_m_f32): Likewise. (__arm_vcmulq_rot90_m_f16): Likewise. (__arm_vcvtq_m_n_s32_f32): Likewise. (__arm_vcvtq_m_n_s16_f16): Likewise. (__arm_vcvtq_m_n_u32_f32): Likewise. (__arm_vcvtq_m_n_u16_f16): Likewise. (__arm_veorq_m_f32): Likewise. (__arm_veorq_m_f16): Likewise. (__arm_vfmaq_m_f32): Likewise. (__arm_vfmaq_m_f16): Likewise. (__arm_vfmaq_m_n_f32): Likewise. (__arm_vfmaq_m_n_f16): Likewise. (__arm_vfmasq_m_n_f32): Likewise. (__arm_vfmasq_m_n_f16): Likewise. (__arm_vfmsq_m_f32): Likewise. (__arm_vfmsq_m_f16): Likewise. (__arm_vmaxnmq_m_f32): Likewise. (__arm_vmaxnmq_m_f16): Likewise. (__arm_vminnmq_m_f32): Likewise. (__arm_vminnmq_m_f16): Likewise. (__arm_vmulq_m_f32): Likewise. (__arm_vmulq_m_f16): Likewise. (__arm_vmulq_m_n_f32): Likewise. (__arm_vmulq_m_n_f16): Likewise. (__arm_vornq_m_f32): Likewise. (__arm_vornq_m_f16): Likewise. (__arm_vorrq_m_f32): Likewise. (__arm_vorrq_m_f16): Likewise. (__arm_vsubq_m_f32): Likewise. (__arm_vsubq_m_f16): Likewise. (__arm_vsubq_m_n_f32): Likewise. (__arm_vsubq_m_n_f16): Likewise. (vabdq_m): Define polymorphic variant. (vaddq_m): Likewise. (vaddq_m_n): Likewise. (vandq_m): Likewise. (vbicq_m): Likewise. (vbrsrq_m_n): Likewise. (vcaddq_rot270_m): Likewise. (vcaddq_rot90_m): Likewise. (vcmlaq_m): Likewise. (vcmlaq_rot180_m): Likewise. (vcmlaq_rot270_m): Likewise. (vcmlaq_rot90_m): Likewise. (vcmulq_m): Likewise. (vcmulq_rot180_m): Likewise. (vcmulq_rot270_m): Likewise. (vcmulq_rot90_m): Likewise. (veorq_m): Likewise. (vfmaq_m): Likewise. (vfmaq_m_n): Likewise. (vfmasq_m_n): Likewise. (vfmsq_m): Likewise. (vmaxnmq_m): Likewise. (vminnmq_m): Likewise. (vmulq_m): Likewise. (vmulq_m_n): Likewise. (vornq_m): Likewise. (vsubq_m): Likewise. (vsubq_m_n): Likewise. (vorrq_m): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. * config/arm/mve.md (mve_vabdq_m_f): Define RTL pattern. (mve_vaddq_m_f): Likewise. (mve_vaddq_m_n_f): Likewise. (mve_vandq_m_f): Likewise. (mve_vbicq_m_f): Likewise. (mve_vbrsrq_m_n_f): Likewise. (mve_vcaddq_rot270_m_f): Likewise. (mve_vcaddq_rot90_m_f): Likewise. (mve_vcmlaq_m_f): Likewise. (mve_vcmlaq_rot180_m_f): Likewise. (mve_vcmlaq_rot270_m_f): Likewise. (mve_vcmlaq_rot90_m_f): Likewise. (mve_vcmulq_m_f): Likewise. (mve_vcmulq_rot180_m_f): Likewise. (mve_vcmulq_rot270_m_f): Likewise. (mve_vcmulq_rot90_m_f): Likewise. (mve_veorq_m_f): Likewise. (mve_vfmaq_m_f): Likewise. (mve_vfmaq_m_n_f): Likewise. (mve_vfmasq_m_n_f): Likewise. (mve_vfmsq_m_f): Likewise. (mve_vmaxnmq_m_f): Likewise. (mve_vminnmq_m_f): Likewise. (mve_vmulq_m_f): Likewise. (mve_vmulq_m_n_f): Likewise. (mve_vornq_m_f): Likewise. (mve_vorrq_m_f): Likewise. (mve_vsubq_m_f): Likewise. (mve_vsubq_m_n_f): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-protos.h (arm_mve_immediate_check): * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check mode and interger value. * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro. (vmlaldavaq_p_s16): Likewise. (vmlaldavaq_p_u32): Likewise. (vmlaldavaq_p_u16): Likewise. (vmlaldavaxq_p_s32): Likewise. (vmlaldavaxq_p_s16): Likewise. (vmlaldavaxq_p_u32): Likewise. (vmlaldavaxq_p_u16): Likewise. (vmlsldavaq_p_s32): Likewise. (vmlsldavaq_p_s16): Likewise. (vmlsldavaxq_p_s32): Likewise. (vmlsldavaxq_p_s16): Likewise. (vmullbq_poly_m_p8): Likewise. (vmullbq_poly_m_p16): Likewise. (vmulltq_poly_m_p8): Likewise. (vmulltq_poly_m_p16): Likewise. (vqdmullbq_m_n_s32): Likewise. (vqdmullbq_m_n_s16): Likewise. (vqdmullbq_m_s32): Likewise. (vqdmullbq_m_s16): Likewise. (vqdmulltq_m_n_s32): Likewise. (vqdmulltq_m_n_s16): Likewise. (vqdmulltq_m_s32): Likewise. (vqdmulltq_m_s16): Likewise. (vqrshrnbq_m_n_s32): Likewise. (vqrshrnbq_m_n_s16): Likewise. (vqrshrnbq_m_n_u32): Likewise. (vqrshrnbq_m_n_u16): Likewise. (vqrshrntq_m_n_s32): Likewise. (vqrshrntq_m_n_s16): Likewise. (vqrshrntq_m_n_u32): Likewise. (vqrshrntq_m_n_u16): Likewise. (vqrshrunbq_m_n_s32): Likewise. (vqrshrunbq_m_n_s16): Likewise. (vqrshruntq_m_n_s32): Likewise. (vqrshruntq_m_n_s16): Likewise. (vqshrnbq_m_n_s32): Likewise. (vqshrnbq_m_n_s16): Likewise. (vqshrnbq_m_n_u32): Likewise. (vqshrnbq_m_n_u16): Likewise. (vqshrntq_m_n_s32): Likewise. (vqshrntq_m_n_s16): Likewise. (vqshrntq_m_n_u32): Likewise. (vqshrntq_m_n_u16): Likewise. (vqshrunbq_m_n_s32): Likewise. (vqshrunbq_m_n_s16): Likewise. (vqshruntq_m_n_s32): Likewise. (vqshruntq_m_n_s16): Likewise. (vrmlaldavhaq_p_s32): Likewise. (vrmlaldavhaq_p_u32): Likewise. (vrmlaldavhaxq_p_s32): Likewise. (vrmlsldavhaq_p_s32): Likewise. (vrmlsldavhaxq_p_s32): Likewise. (vrshrnbq_m_n_s32): Likewise. (vrshrnbq_m_n_s16): Likewise. (vrshrnbq_m_n_u32): Likewise. (vrshrnbq_m_n_u16): Likewise. (vrshrntq_m_n_s32): Likewise. (vrshrntq_m_n_s16): Likewise. (vrshrntq_m_n_u32): Likewise. (vrshrntq_m_n_u16): Likewise. (vshllbq_m_n_s8): Likewise. (vshllbq_m_n_s16): Likewise. (vshllbq_m_n_u8): Likewise. (vshllbq_m_n_u16): Likewise. (vshlltq_m_n_s8): Likewise. (vshlltq_m_n_s16): Likewise. (vshlltq_m_n_u8): Likewise. (vshlltq_m_n_u16): Likewise. (vshrnbq_m_n_s32): Likewise. (vshrnbq_m_n_s16): Likewise. (vshrnbq_m_n_u32): Likewise. (vshrnbq_m_n_u16): Likewise. (vshrntq_m_n_s32): Likewise. (vshrntq_m_n_s16): Likewise. (vshrntq_m_n_u32): Likewise. (vshrntq_m_n_u16): Likewise. (__arm_vmlaldavaq_p_s32): Define intrinsic. (__arm_vmlaldavaq_p_s16): Likewise. (__arm_vmlaldavaq_p_u32): Likewise. (__arm_vmlaldavaq_p_u16): Likewise. (__arm_vmlaldavaxq_p_s32): Likewise. (__arm_vmlaldavaxq_p_s16): Likewise. (__arm_vmlaldavaxq_p_u32): Likewise. (__arm_vmlaldavaxq_p_u16): Likewise. (__arm_vmlsldavaq_p_s32): Likewise. (__arm_vmlsldavaq_p_s16): Likewise. (__arm_vmlsldavaxq_p_s32): Likewise. (__arm_vmlsldavaxq_p_s16): Likewise. (__arm_vmullbq_poly_m_p8): Likewise. (__arm_vmullbq_poly_m_p16): Likewise. (__arm_vmulltq_poly_m_p8): Likewise. (__arm_vmulltq_poly_m_p16): Likewise. (__arm_vqdmullbq_m_n_s32): Likewise. (__arm_vqdmullbq_m_n_s16): Likewise. (__arm_vqdmullbq_m_s32): Likewise. (__arm_vqdmullbq_m_s16): Likewise. (__arm_vqdmulltq_m_n_s32): Likewise. (__arm_vqdmulltq_m_n_s16): Likewise. (__arm_vqdmulltq_m_s32): Likewise. (__arm_vqdmulltq_m_s16): Likewise. (__arm_vqrshrnbq_m_n_s32): Likewise. (__arm_vqrshrnbq_m_n_s16): Likewise. (__arm_vqrshrnbq_m_n_u32): Likewise. (__arm_vqrshrnbq_m_n_u16): Likewise. (__arm_vqrshrntq_m_n_s32): Likewise. (__arm_vqrshrntq_m_n_s16): Likewise. (__arm_vqrshrntq_m_n_u32): Likewise. (__arm_vqrshrntq_m_n_u16): Likewise. (__arm_vqrshrunbq_m_n_s32): Likewise. (__arm_vqrshrunbq_m_n_s16): Likewise. (__arm_vqrshruntq_m_n_s32): Likewise. (__arm_vqrshruntq_m_n_s16): Likewise. (__arm_vqshrnbq_m_n_s32): Likewise. (__arm_vqshrnbq_m_n_s16): Likewise. (__arm_vqshrnbq_m_n_u32): Likewise. (__arm_vqshrnbq_m_n_u16): Likewise. (__arm_vqshrntq_m_n_s32): Likewise. (__arm_vqshrntq_m_n_s16): Likewise. (__arm_vqshrntq_m_n_u32): Likewise. (__arm_vqshrntq_m_n_u16): Likewise. (__arm_vqshrunbq_m_n_s32): Likewise. (__arm_vqshrunbq_m_n_s16): Likewise. (__arm_vqshruntq_m_n_s32): Likewise. (__arm_vqshruntq_m_n_s16): Likewise. (__arm_vrmlaldavhaq_p_s32): Likewise. (__arm_vrmlaldavhaq_p_u32): Likewise. (__arm_vrmlaldavhaxq_p_s32): Likewise. (__arm_vrmlsldavhaq_p_s32): Likewise. (__arm_vrmlsldavhaxq_p_s32): Likewise. (__arm_vrshrnbq_m_n_s32): Likewise. (__arm_vrshrnbq_m_n_s16): Likewise. (__arm_vrshrnbq_m_n_u32): Likewise. (__arm_vrshrnbq_m_n_u16): Likewise. (__arm_vrshrntq_m_n_s32): Likewise. (__arm_vrshrntq_m_n_s16): Likewise. (__arm_vrshrntq_m_n_u32): Likewise. (__arm_vrshrntq_m_n_u16): Likewise. (__arm_vshllbq_m_n_s8): Likewise. (__arm_vshllbq_m_n_s16): Likewise. (__arm_vshllbq_m_n_u8): Likewise. (__arm_vshllbq_m_n_u16): Likewise. (__arm_vshlltq_m_n_s8): Likewise. (__arm_vshlltq_m_n_s16): Likewise. (__arm_vshlltq_m_n_u8): Likewise. (__arm_vshlltq_m_n_u16): Likewise. (__arm_vshrnbq_m_n_s32): Likewise. (__arm_vshrnbq_m_n_s16): Likewise. (__arm_vshrnbq_m_n_u32): Likewise. (__arm_vshrnbq_m_n_u16): Likewise. (__arm_vshrntq_m_n_s32): Likewise. (__arm_vshrntq_m_n_s16): Likewise. (__arm_vshrntq_m_n_u32): Likewise. (__arm_vshrntq_m_n_u16): Likewise. (vmullbq_poly_m): Define polymorphic variant. (vmulltq_poly_m): Likewise. (vshllbq_m): Likewise. (vshrntq_m_n): Likewise. (vshrnbq_m_n): Likewise. (vshlltq_m_n): Likewise. (vshllbq_m_n): Likewise. (vrshrntq_m_n): Likewise. (vrshrnbq_m_n): Likewise. (vqshruntq_m_n): Likewise. (vqshrunbq_m_n): Likewise. (vqdmullbq_m_n): Likewise. (vqdmullbq_m): Likewise. (vqdmulltq_m_n): Likewise. (vqdmulltq_m): Likewise. (vqrshrnbq_m_n): Likewise. (vqrshrntq_m_n): Likewise. (vqrshrunbq_m_n): Likewise. (vqrshruntq_m_n): Likewise. (vqshrnbq_m_n): Likewise. (vqshrntq_m_n): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifiers. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VMLALDAVAQ_P): Define iterator. (VMLALDAVAXQ_P): Likewise. (VQRSHRNBQ_M_N): Likewise. (VQRSHRNTQ_M_N): Likewise. (VQSHRNBQ_M_N): Likewise. (VQSHRNTQ_M_N): Likewise. (VRSHRNBQ_M_N): Likewise. (VRSHRNTQ_M_N): Likewise. (VSHLLBQ_M_N): Likewise. (VSHLLTQ_M_N): Likewise. (VSHRNBQ_M_N): Likewise. (VSHRNTQ_M_N): Likewise. (mve_vmlaldavaq_p_): Define RTL pattern. (mve_vmlaldavaxq_p_): Likewise. (mve_vqrshrnbq_m_n_): Likewise. (mve_vqrshrntq_m_n_): Likewise. (mve_vqshrnbq_m_n_): Likewise. (mve_vqshrntq_m_n_): Likewise. (mve_vrmlaldavhaq_p_sv4si): Likewise. (mve_vrshrnbq_m_n_): Likewise. (mve_vrshrntq_m_n_): Likewise. (mve_vshllbq_m_n_): Likewise. (mve_vshlltq_m_n_): Likewise. (mve_vshrnbq_m_n_): Likewise. (mve_vshrntq_m_n_): Likewise. (mve_vmlsldavaq_p_s): Likewise. (mve_vmlsldavaxq_p_s): Likewise. (mve_vmullbq_poly_m_p): Likewise. (mve_vmulltq_poly_m_p): Likewise. (mve_vqdmullbq_m_n_s): Likewise. (mve_vqdmullbq_m_s): Likewise. (mve_vqdmulltq_m_n_s): Likewise. (mve_vqdmulltq_m_s): Likewise. (mve_vqrshrunbq_m_n_s): Likewise. (mve_vqrshruntq_m_n_s): Likewise. (mve_vqshrunbq_m_n_s): Likewise. (mve_vqshruntq_m_n_s): Likewise. (mve_vrmlaldavhaq_p_uv4si): Likewise. (mve_vrmlaldavhaxq_p_sv4si): Likewise. (mve_vrmlsldavhaq_p_sv4si): Likewise. (mve_vrmlsldavhaxq_p_sv4si): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vabdq_m_s8): Define macro. (vabdq_m_s32): Likewise. (vabdq_m_s16): Likewise. (vabdq_m_u8): Likewise. (vabdq_m_u32): Likewise. (vabdq_m_u16): Likewise. (vaddq_m_n_s8): Likewise. (vaddq_m_n_s32): Likewise. (vaddq_m_n_s16): Likewise. (vaddq_m_n_u8): Likewise. (vaddq_m_n_u32): Likewise. (vaddq_m_n_u16): Likewise. (vaddq_m_s8): Likewise. (vaddq_m_s32): Likewise. (vaddq_m_s16): Likewise. (vaddq_m_u8): Likewise. (vaddq_m_u32): Likewise. (vaddq_m_u16): Likewise. (vandq_m_s8): Likewise. (vandq_m_s32): Likewise. (vandq_m_s16): Likewise. (vandq_m_u8): Likewise. (vandq_m_u32): Likewise. (vandq_m_u16): Likewise. (vbicq_m_s8): Likewise. (vbicq_m_s32): Likewise. (vbicq_m_s16): Likewise. (vbicq_m_u8): Likewise. (vbicq_m_u32): Likewise. (vbicq_m_u16): Likewise. (vbrsrq_m_n_s8): Likewise. (vbrsrq_m_n_s32): Likewise. (vbrsrq_m_n_s16): Likewise. (vbrsrq_m_n_u8): Likewise. (vbrsrq_m_n_u32): Likewise. (vbrsrq_m_n_u16): Likewise. (vcaddq_rot270_m_s8): Likewise. (vcaddq_rot270_m_s32): Likewise. (vcaddq_rot270_m_s16): Likewise. (vcaddq_rot270_m_u8): Likewise. (vcaddq_rot270_m_u32): Likewise. (vcaddq_rot270_m_u16): Likewise. (vcaddq_rot90_m_s8): Likewise. (vcaddq_rot90_m_s32): Likewise. (vcaddq_rot90_m_s16): Likewise. (vcaddq_rot90_m_u8): Likewise. (vcaddq_rot90_m_u32): Likewise. (vcaddq_rot90_m_u16): Likewise. (veorq_m_s8): Likewise. (veorq_m_s32): Likewise. (veorq_m_s16): Likewise. (veorq_m_u8): Likewise. (veorq_m_u32): Likewise. (veorq_m_u16): Likewise. (vhaddq_m_n_s8): Likewise. (vhaddq_m_n_s32): Likewise. (vhaddq_m_n_s16): Likewise. (vhaddq_m_n_u8): Likewise. (vhaddq_m_n_u32): Likewise. (vhaddq_m_n_u16): Likewise. (vhaddq_m_s8): Likewise. (vhaddq_m_s32): Likewise. (vhaddq_m_s16): Likewise. (vhaddq_m_u8): Likewise. (vhaddq_m_u32): Likewise. (vhaddq_m_u16): Likewise. (vhcaddq_rot270_m_s8): Likewise. (vhcaddq_rot270_m_s32): Likewise. (vhcaddq_rot270_m_s16): Likewise. (vhcaddq_rot90_m_s8): Likewise. (vhcaddq_rot90_m_s32): Likewise. (vhcaddq_rot90_m_s16): Likewise. (vhsubq_m_n_s8): Likewise. (vhsubq_m_n_s32): Likewise. (vhsubq_m_n_s16): Likewise. (vhsubq_m_n_u8): Likewise. (vhsubq_m_n_u32): Likewise. (vhsubq_m_n_u16): Likewise. (vhsubq_m_s8): Likewise. (vhsubq_m_s32): Likewise. (vhsubq_m_s16): Likewise. (vhsubq_m_u8): Likewise. (vhsubq_m_u32): Likewise. (vhsubq_m_u16): Likewise. (vmaxq_m_s8): Likewise. (vmaxq_m_s32): Likewise. (vmaxq_m_s16): Likewise. (vmaxq_m_u8): Likewise. (vmaxq_m_u32): Likewise. (vmaxq_m_u16): Likewise. (vminq_m_s8): Likewise. (vminq_m_s32): Likewise. (vminq_m_s16): Likewise. (vminq_m_u8): Likewise. (vminq_m_u32): Likewise. (vminq_m_u16): Likewise. (vmladavaq_p_s8): Likewise. (vmladavaq_p_s32): Likewise. (vmladavaq_p_s16): Likewise. (vmladavaq_p_u8): Likewise. (vmladavaq_p_u32): Likewise. (vmladavaq_p_u16): Likewise. (vmladavaxq_p_s8): Likewise. (vmladavaxq_p_s32): Likewise. (vmladavaxq_p_s16): Likewise. (vmlaq_m_n_s8): Likewise. (vmlaq_m_n_s32): Likewise. (vmlaq_m_n_s16): Likewise. (vmlaq_m_n_u8): Likewise. (vmlaq_m_n_u32): Likewise. (vmlaq_m_n_u16): Likewise. (vmlasq_m_n_s8): Likewise. (vmlasq_m_n_s32): Likewise. (vmlasq_m_n_s16): Likewise. (vmlasq_m_n_u8): Likewise. (vmlasq_m_n_u32): Likewise. (vmlasq_m_n_u16): Likewise. (vmlsdavaq_p_s8): Likewise. (vmlsdavaq_p_s32): Likewise. (vmlsdavaq_p_s16): Likewise. (vmlsdavaxq_p_s8): Likewise. (vmlsdavaxq_p_s32): Likewise. (vmlsdavaxq_p_s16): Likewise. (vmulhq_m_s8): Likewise. (vmulhq_m_s32): Likewise. (vmulhq_m_s16): Likewise. (vmulhq_m_u8): Likewise. (vmulhq_m_u32): Likewise. (vmulhq_m_u16): Likewise. (vmullbq_int_m_s8): Likewise. (vmullbq_int_m_s32): Likewise. (vmullbq_int_m_s16): Likewise. (vmullbq_int_m_u8): Likewise. (vmullbq_int_m_u32): Likewise. (vmullbq_int_m_u16): Likewise. (vmulltq_int_m_s8): Likewise. (vmulltq_int_m_s32): Likewise. (vmulltq_int_m_s16): Likewise. (vmulltq_int_m_u8): Likewise. (vmulltq_int_m_u32): Likewise. (vmulltq_int_m_u16): Likewise. (vmulq_m_n_s8): Likewise. (vmulq_m_n_s32): Likewise. (vmulq_m_n_s16): Likewise. (vmulq_m_n_u8): Likewise. (vmulq_m_n_u32): Likewise. (vmulq_m_n_u16): Likewise. (vmulq_m_s8): Likewise. (vmulq_m_s32): Likewise. (vmulq_m_s16): Likewise. (vmulq_m_u8): Likewise. (vmulq_m_u32): Likewise. (vmulq_m_u16): Likewise. (vornq_m_s8): Likewise. (vornq_m_s32): Likewise. (vornq_m_s16): Likewise. (vornq_m_u8): Likewise. (vornq_m_u32): Likewise. (vornq_m_u16): Likewise. (vorrq_m_s8): Likewise. (vorrq_m_s32): Likewise. (vorrq_m_s16): Likewise. (vorrq_m_u8): Likewise. (vorrq_m_u32): Likewise. (vorrq_m_u16): Likewise. (vqaddq_m_n_s8): Likewise. (vqaddq_m_n_s32): Likewise. (vqaddq_m_n_s16): Likewise. (vqaddq_m_n_u8): Likewise. (vqaddq_m_n_u32): Likewise. (vqaddq_m_n_u16): Likewise. (vqaddq_m_s8): Likewise. (vqaddq_m_s32): Likewise. (vqaddq_m_s16): Likewise. (vqaddq_m_u8): Likewise. (vqaddq_m_u32): Likewise. (vqaddq_m_u16): Likewise. (vqdmladhq_m_s8): Likewise. (vqdmladhq_m_s32): Likewise. (vqdmladhq_m_s16): Likewise. (vqdmladhxq_m_s8): Likewise. (vqdmladhxq_m_s32): Likewise. (vqdmladhxq_m_s16): Likewise. (vqdmlahq_m_n_s8): Likewise. (vqdmlahq_m_n_s32): Likewise. (vqdmlahq_m_n_s16): Likewise. (vqdmlahq_m_n_u8): Likewise. (vqdmlahq_m_n_u32): Likewise. (vqdmlahq_m_n_u16): Likewise. (vqdmlsdhq_m_s8): Likewise. (vqdmlsdhq_m_s32): Likewise. (vqdmlsdhq_m_s16): Likewise. (vqdmlsdhxq_m_s8): Likewise. (vqdmlsdhxq_m_s32): Likewise. (vqdmlsdhxq_m_s16): Likewise. (vqdmulhq_m_n_s8): Likewise. (vqdmulhq_m_n_s32): Likewise. (vqdmulhq_m_n_s16): Likewise. (vqdmulhq_m_s8): Likewise. (vqdmulhq_m_s32): Likewise. (vqdmulhq_m_s16): Likewise. (vqrdmladhq_m_s8): Likewise. (vqrdmladhq_m_s32): Likewise. (vqrdmladhq_m_s16): Likewise. (vqrdmladhxq_m_s8): Likewise. (vqrdmladhxq_m_s32): Likewise. (vqrdmladhxq_m_s16): Likewise. (vqrdmlahq_m_n_s8): Likewise. (vqrdmlahq_m_n_s32): Likewise. (vqrdmlahq_m_n_s16): Likewise. (vqrdmlahq_m_n_u8): Likewise. (vqrdmlahq_m_n_u32): Likewise. (vqrdmlahq_m_n_u16): Likewise. (vqrdmlashq_m_n_s8): Likewise. (vqrdmlashq_m_n_s32): Likewise. (vqrdmlashq_m_n_s16): Likewise. (vqrdmlashq_m_n_u8): Likewise. (vqrdmlashq_m_n_u32): Likewise. (vqrdmlashq_m_n_u16): Likewise. (vqrdmlsdhq_m_s8): Likewise. (vqrdmlsdhq_m_s32): Likewise. (vqrdmlsdhq_m_s16): Likewise. (vqrdmlsdhxq_m_s8): Likewise. (vqrdmlsdhxq_m_s32): Likewise. (vqrdmlsdhxq_m_s16): Likewise. (vqrdmulhq_m_n_s8): Likewise. (vqrdmulhq_m_n_s32): Likewise. (vqrdmulhq_m_n_s16): Likewise. (vqrdmulhq_m_s8): Likewise. (vqrdmulhq_m_s32): Likewise. (vqrdmulhq_m_s16): Likewise. (vqrshlq_m_s8): Likewise. (vqrshlq_m_s32): Likewise. (vqrshlq_m_s16): Likewise. (vqrshlq_m_u8): Likewise. (vqrshlq_m_u32): Likewise. (vqrshlq_m_u16): Likewise. (vqshlq_m_n_s8): Likewise. (vqshlq_m_n_s32): Likewise. (vqshlq_m_n_s16): Likewise. (vqshlq_m_n_u8): Likewise. (vqshlq_m_n_u32): Likewise. (vqshlq_m_n_u16): Likewise. (vqshlq_m_s8): Likewise. (vqshlq_m_s32): Likewise. (vqshlq_m_s16): Likewise. (vqshlq_m_u8): Likewise. (vqshlq_m_u32): Likewise. (vqshlq_m_u16): Likewise. (vqsubq_m_n_s8): Likewise. (vqsubq_m_n_s32): Likewise. (vqsubq_m_n_s16): Likewise. (vqsubq_m_n_u8): Likewise. (vqsubq_m_n_u32): Likewise. (vqsubq_m_n_u16): Likewise. (vqsubq_m_s8): Likewise. (vqsubq_m_s32): Likewise. (vqsubq_m_s16): Likewise. (vqsubq_m_u8): Likewise. (vqsubq_m_u32): Likewise. (vqsubq_m_u16): Likewise. (vrhaddq_m_s8): Likewise. (vrhaddq_m_s32): Likewise. (vrhaddq_m_s16): Likewise. (vrhaddq_m_u8): Likewise. (vrhaddq_m_u32): Likewise. (vrhaddq_m_u16): Likewise. (vrmulhq_m_s8): Likewise. (vrmulhq_m_s32): Likewise. (vrmulhq_m_s16): Likewise. (vrmulhq_m_u8): Likewise. (vrmulhq_m_u32): Likewise. (vrmulhq_m_u16): Likewise. (vrshlq_m_s8): Likewise. (vrshlq_m_s32): Likewise. (vrshlq_m_s16): Likewise. (vrshlq_m_u8): Likewise. (vrshlq_m_u32): Likewise. (vrshlq_m_u16): Likewise. (vrshrq_m_n_s8): Likewise. (vrshrq_m_n_s32): Likewise. (vrshrq_m_n_s16): Likewise. (vrshrq_m_n_u8): Likewise. (vrshrq_m_n_u32): Likewise. (vrshrq_m_n_u16): Likewise. (vshlq_m_n_s8): Likewise. (vshlq_m_n_s32): Likewise. (vshlq_m_n_s16): Likewise. (vshlq_m_n_u8): Likewise. (vshlq_m_n_u32): Likewise. (vshlq_m_n_u16): Likewise. (vshrq_m_n_s8): Likewise. (vshrq_m_n_s32): Likewise. (vshrq_m_n_s16): Likewise. (vshrq_m_n_u8): Likewise. (vshrq_m_n_u32): Likewise. (vshrq_m_n_u16): Likewise. (vsliq_m_n_s8): Likewise. (vsliq_m_n_s32): Likewise. (vsliq_m_n_s16): Likewise. (vsliq_m_n_u8): Likewise. (vsliq_m_n_u32): Likewise. (vsliq_m_n_u16): Likewise. (vsubq_m_n_s8): Likewise. (vsubq_m_n_s32): Likewise. (vsubq_m_n_s16): Likewise. (vsubq_m_n_u8): Likewise. (vsubq_m_n_u32): Likewise. (vsubq_m_n_u16): Likewise. (__arm_vabdq_m_s8): Define intrinsic. (__arm_vabdq_m_s32): Likewise. (__arm_vabdq_m_s16): Likewise. (__arm_vabdq_m_u8): Likewise. (__arm_vabdq_m_u32): Likewise. (__arm_vabdq_m_u16): Likewise. (__arm_vaddq_m_n_s8): Likewise. (__arm_vaddq_m_n_s32): Likewise. (__arm_vaddq_m_n_s16): Likewise. (__arm_vaddq_m_n_u8): Likewise. (__arm_vaddq_m_n_u32): Likewise. (__arm_vaddq_m_n_u16): Likewise. (__arm_vaddq_m_s8): Likewise. (__arm_vaddq_m_s32): Likewise. (__arm_vaddq_m_s16): Likewise. (__arm_vaddq_m_u8): Likewise. (__arm_vaddq_m_u32): Likewise. (__arm_vaddq_m_u16): Likewise. (__arm_vandq_m_s8): Likewise. (__arm_vandq_m_s32): Likewise. (__arm_vandq_m_s16): Likewise. (__arm_vandq_m_u8): Likewise. (__arm_vandq_m_u32): Likewise. (__arm_vandq_m_u16): Likewise. (__arm_vbicq_m_s8): Likewise. (__arm_vbicq_m_s32): Likewise. (__arm_vbicq_m_s16): Likewise. (__arm_vbicq_m_u8): Likewise. (__arm_vbicq_m_u32): Likewise. (__arm_vbicq_m_u16): Likewise. (__arm_vbrsrq_m_n_s8): Likewise. (__arm_vbrsrq_m_n_s32): Likewise. (__arm_vbrsrq_m_n_s16): Likewise. (__arm_vbrsrq_m_n_u8): Likewise. (__arm_vbrsrq_m_n_u32): Likewise. (__arm_vbrsrq_m_n_u16): Likewise. (__arm_vcaddq_rot270_m_s8): Likewise. (__arm_vcaddq_rot270_m_s32): Likewise. (__arm_vcaddq_rot270_m_s16): Likewise. (__arm_vcaddq_rot270_m_u8): Likewise. (__arm_vcaddq_rot270_m_u32): Likewise. (__arm_vcaddq_rot270_m_u16): Likewise. (__arm_vcaddq_rot90_m_s8): Likewise. (__arm_vcaddq_rot90_m_s32): Likewise. (__arm_vcaddq_rot90_m_s16): Likewise. (__arm_vcaddq_rot90_m_u8): Likewise. (__arm_vcaddq_rot90_m_u32): Likewise. (__arm_vcaddq_rot90_m_u16): Likewise. (__arm_veorq_m_s8): Likewise. (__arm_veorq_m_s32): Likewise. (__arm_veorq_m_s16): Likewise. (__arm_veorq_m_u8): Likewise. (__arm_veorq_m_u32): Likewise. (__arm_veorq_m_u16): Likewise. (__arm_vhaddq_m_n_s8): Likewise. (__arm_vhaddq_m_n_s32): Likewise. (__arm_vhaddq_m_n_s16): Likewise. (__arm_vhaddq_m_n_u8): Likewise. (__arm_vhaddq_m_n_u32): Likewise. (__arm_vhaddq_m_n_u16): Likewise. (__arm_vhaddq_m_s8): Likewise. (__arm_vhaddq_m_s32): Likewise. (__arm_vhaddq_m_s16): Likewise. (__arm_vhaddq_m_u8): Likewise. (__arm_vhaddq_m_u32): Likewise. (__arm_vhaddq_m_u16): Likewise. (__arm_vhcaddq_rot270_m_s8): Likewise. (__arm_vhcaddq_rot270_m_s32): Likewise. (__arm_vhcaddq_rot270_m_s16): Likewise. (__arm_vhcaddq_rot90_m_s8): Likewise. (__arm_vhcaddq_rot90_m_s32): Likewise. (__arm_vhcaddq_rot90_m_s16): Likewise. (__arm_vhsubq_m_n_s8): Likewise. (__arm_vhsubq_m_n_s32): Likewise. (__arm_vhsubq_m_n_s16): Likewise. (__arm_vhsubq_m_n_u8): Likewise. (__arm_vhsubq_m_n_u32): Likewise. (__arm_vhsubq_m_n_u16): Likewise. (__arm_vhsubq_m_s8): Likewise. (__arm_vhsubq_m_s32): Likewise. (__arm_vhsubq_m_s16): Likewise. (__arm_vhsubq_m_u8): Likewise. (__arm_vhsubq_m_u32): Likewise. (__arm_vhsubq_m_u16): Likewise. (__arm_vmaxq_m_s8): Likewise. (__arm_vmaxq_m_s32): Likewise. (__arm_vmaxq_m_s16): Likewise. (__arm_vmaxq_m_u8): Likewise. (__arm_vmaxq_m_u32): Likewise. (__arm_vmaxq_m_u16): Likewise. (__arm_vminq_m_s8): Likewise. (__arm_vminq_m_s32): Likewise. (__arm_vminq_m_s16): Likewise. (__arm_vminq_m_u8): Likewise. (__arm_vminq_m_u32): Likewise. (__arm_vminq_m_u16): Likewise. (__arm_vmladavaq_p_s8): Likewise. (__arm_vmladavaq_p_s32): Likewise. (__arm_vmladavaq_p_s16): Likewise. (__arm_vmladavaq_p_u8): Likewise. (__arm_vmladavaq_p_u32): Likewise. (__arm_vmladavaq_p_u16): Likewise. (__arm_vmladavaxq_p_s8): Likewise. (__arm_vmladavaxq_p_s32): Likewise. (__arm_vmladavaxq_p_s16): Likewise. (__arm_vmlaq_m_n_s8): Likewise. (__arm_vmlaq_m_n_s32): Likewise. (__arm_vmlaq_m_n_s16): Likewise. (__arm_vmlaq_m_n_u8): Likewise. (__arm_vmlaq_m_n_u32): Likewise. (__arm_vmlaq_m_n_u16): Likewise. (__arm_vmlasq_m_n_s8): Likewise. (__arm_vmlasq_m_n_s32): Likewise. (__arm_vmlasq_m_n_s16): Likewise. (__arm_vmlasq_m_n_u8): Likewise. (__arm_vmlasq_m_n_u32): Likewise. (__arm_vmlasq_m_n_u16): Likewise. (__arm_vmlsdavaq_p_s8): Likewise. (__arm_vmlsdavaq_p_s32): Likewise. (__arm_vmlsdavaq_p_s16): Likewise. (__arm_vmlsdavaxq_p_s8): Likewise. (__arm_vmlsdavaxq_p_s32): Likewise. (__arm_vmlsdavaxq_p_s16): Likewise. (__arm_vmulhq_m_s8): Likewise. (__arm_vmulhq_m_s32): Likewise. (__arm_vmulhq_m_s16): Likewise. (__arm_vmulhq_m_u8): Likewise. (__arm_vmulhq_m_u32): Likewise. (__arm_vmulhq_m_u16): Likewise. (__arm_vmullbq_int_m_s8): Likewise. (__arm_vmullbq_int_m_s32): Likewise. (__arm_vmullbq_int_m_s16): Likewise. (__arm_vmullbq_int_m_u8): Likewise. (__arm_vmullbq_int_m_u32): Likewise. (__arm_vmullbq_int_m_u16): Likewise. (__arm_vmulltq_int_m_s8): Likewise. (__arm_vmulltq_int_m_s32): Likewise. (__arm_vmulltq_int_m_s16): Likewise. (__arm_vmulltq_int_m_u8): Likewise. (__arm_vmulltq_int_m_u32): Likewise. (__arm_vmulltq_int_m_u16): Likewise. (__arm_vmulq_m_n_s8): Likewise. (__arm_vmulq_m_n_s32): Likewise. (__arm_vmulq_m_n_s16): Likewise. (__arm_vmulq_m_n_u8): Likewise. (__arm_vmulq_m_n_u32): Likewise. (__arm_vmulq_m_n_u16): Likewise. (__arm_vmulq_m_s8): Likewise. (__arm_vmulq_m_s32): Likewise. (__arm_vmulq_m_s16): Likewise. (__arm_vmulq_m_u8): Likewise. (__arm_vmulq_m_u32): Likewise. (__arm_vmulq_m_u16): Likewise. (__arm_vornq_m_s8): Likewise. (__arm_vornq_m_s32): Likewise. (__arm_vornq_m_s16): Likewise. (__arm_vornq_m_u8): Likewise. (__arm_vornq_m_u32): Likewise. (__arm_vornq_m_u16): Likewise. (__arm_vorrq_m_s8): Likewise. (__arm_vorrq_m_s32): Likewise. (__arm_vorrq_m_s16): Likewise. (__arm_vorrq_m_u8): Likewise. (__arm_vorrq_m_u32): Likewise. (__arm_vorrq_m_u16): Likewise. (__arm_vqaddq_m_n_s8): Likewise. (__arm_vqaddq_m_n_s32): Likewise. (__arm_vqaddq_m_n_s16): Likewise. (__arm_vqaddq_m_n_u8): Likewise. (__arm_vqaddq_m_n_u32): Likewise. (__arm_vqaddq_m_n_u16): Likewise. (__arm_vqaddq_m_s8): Likewise. (__arm_vqaddq_m_s32): Likewise. (__arm_vqaddq_m_s16): Likewise. (__arm_vqaddq_m_u8): Likewise. (__arm_vqaddq_m_u32): Likewise. (__arm_vqaddq_m_u16): Likewise. (__arm_vqdmladhq_m_s8): Likewise. (__arm_vqdmladhq_m_s32): Likewise. (__arm_vqdmladhq_m_s16): Likewise. (__arm_vqdmladhxq_m_s8): Likewise. (__arm_vqdmladhxq_m_s32): Likewise. (__arm_vqdmladhxq_m_s16): Likewise. (__arm_vqdmlahq_m_n_s8): Likewise. (__arm_vqdmlahq_m_n_s32): Likewise. (__arm_vqdmlahq_m_n_s16): Likewise. (__arm_vqdmlahq_m_n_u8): Likewise. (__arm_vqdmlahq_m_n_u32): Likewise. (__arm_vqdmlahq_m_n_u16): Likewise. (__arm_vqdmlsdhq_m_s8): Likewise. (__arm_vqdmlsdhq_m_s32): Likewise. (__arm_vqdmlsdhq_m_s16): Likewise. (__arm_vqdmlsdhxq_m_s8): Likewise. (__arm_vqdmlsdhxq_m_s32): Likewise. (__arm_vqdmlsdhxq_m_s16): Likewise. (__arm_vqdmulhq_m_n_s8): Likewise. (__arm_vqdmulhq_m_n_s32): Likewise. (__arm_vqdmulhq_m_n_s16): Likewise. (__arm_vqdmulhq_m_s8): Likewise. (__arm_vqdmulhq_m_s32): Likewise. (__arm_vqdmulhq_m_s16): Likewise. (__arm_vqrdmladhq_m_s8): Likewise. (__arm_vqrdmladhq_m_s32): Likewise. (__arm_vqrdmladhq_m_s16): Likewise. (__arm_vqrdmladhxq_m_s8): Likewise. (__arm_vqrdmladhxq_m_s32): Likewise. (__arm_vqrdmladhxq_m_s16): Likewise. (__arm_vqrdmlahq_m_n_s8): Likewise. (__arm_vqrdmlahq_m_n_s32): Likewise. (__arm_vqrdmlahq_m_n_s16): Likewise. (__arm_vqrdmlahq_m_n_u8): Likewise. (__arm_vqrdmlahq_m_n_u32): Likewise. (__arm_vqrdmlahq_m_n_u16): Likewise. (__arm_vqrdmlashq_m_n_s8): Likewise. (__arm_vqrdmlashq_m_n_s32): Likewise. (__arm_vqrdmlashq_m_n_s16): Likewise. (__arm_vqrdmlashq_m_n_u8): Likewise. (__arm_vqrdmlashq_m_n_u32): Likewise. (__arm_vqrdmlashq_m_n_u16): Likewise. (__arm_vqrdmlsdhq_m_s8): Likewise. (__arm_vqrdmlsdhq_m_s32): Likewise. (__arm_vqrdmlsdhq_m_s16): Likewise. (__arm_vqrdmlsdhxq_m_s8): Likewise. (__arm_vqrdmlsdhxq_m_s32): Likewise. (__arm_vqrdmlsdhxq_m_s16): Likewise. (__arm_vqrdmulhq_m_n_s8): Likewise. (__arm_vqrdmulhq_m_n_s32): Likewise. (__arm_vqrdmulhq_m_n_s16): Likewise. (__arm_vqrdmulhq_m_s8): Likewise. (__arm_vqrdmulhq_m_s32): Likewise. (__arm_vqrdmulhq_m_s16): Likewise. (__arm_vqrshlq_m_s8): Likewise. (__arm_vqrshlq_m_s32): Likewise. (__arm_vqrshlq_m_s16): Likewise. (__arm_vqrshlq_m_u8): Likewise. (__arm_vqrshlq_m_u32): Likewise. (__arm_vqrshlq_m_u16): Likewise. (__arm_vqshlq_m_n_s8): Likewise. (__arm_vqshlq_m_n_s32): Likewise. (__arm_vqshlq_m_n_s16): Likewise. (__arm_vqshlq_m_n_u8): Likewise. (__arm_vqshlq_m_n_u32): Likewise. (__arm_vqshlq_m_n_u16): Likewise. (__arm_vqshlq_m_s8): Likewise. (__arm_vqshlq_m_s32): Likewise. (__arm_vqshlq_m_s16): Likewise. (__arm_vqshlq_m_u8): Likewise. (__arm_vqshlq_m_u32): Likewise. (__arm_vqshlq_m_u16): Likewise. (__arm_vqsubq_m_n_s8): Likewise. (__arm_vqsubq_m_n_s32): Likewise. (__arm_vqsubq_m_n_s16): Likewise. (__arm_vqsubq_m_n_u8): Likewise. (__arm_vqsubq_m_n_u32): Likewise. (__arm_vqsubq_m_n_u16): Likewise. (__arm_vqsubq_m_s8): Likewise. (__arm_vqsubq_m_s32): Likewise. (__arm_vqsubq_m_s16): Likewise. (__arm_vqsubq_m_u8): Likewise. (__arm_vqsubq_m_u32): Likewise. (__arm_vqsubq_m_u16): Likewise. (__arm_vrhaddq_m_s8): Likewise. (__arm_vrhaddq_m_s32): Likewise. (__arm_vrhaddq_m_s16): Likewise. (__arm_vrhaddq_m_u8): Likewise. (__arm_vrhaddq_m_u32): Likewise. (__arm_vrhaddq_m_u16): Likewise. (__arm_vrmulhq_m_s8): Likewise. (__arm_vrmulhq_m_s32): Likewise. (__arm_vrmulhq_m_s16): Likewise. (__arm_vrmulhq_m_u8): Likewise. (__arm_vrmulhq_m_u32): Likewise. (__arm_vrmulhq_m_u16): Likewise. (__arm_vrshlq_m_s8): Likewise. (__arm_vrshlq_m_s32): Likewise. (__arm_vrshlq_m_s16): Likewise. (__arm_vrshlq_m_u8): Likewise. (__arm_vrshlq_m_u32): Likewise. (__arm_vrshlq_m_u16): Likewise. (__arm_vrshrq_m_n_s8): Likewise. (__arm_vrshrq_m_n_s32): Likewise. (__arm_vrshrq_m_n_s16): Likewise. (__arm_vrshrq_m_n_u8): Likewise. (__arm_vrshrq_m_n_u32): Likewise. (__arm_vrshrq_m_n_u16): Likewise. (__arm_vshlq_m_n_s8): Likewise. (__arm_vshlq_m_n_s32): Likewise. (__arm_vshlq_m_n_s16): Likewise. (__arm_vshlq_m_n_u8): Likewise. (__arm_vshlq_m_n_u32): Likewise. (__arm_vshlq_m_n_u16): Likewise. (__arm_vshrq_m_n_s8): Likewise. (__arm_vshrq_m_n_s32): Likewise. (__arm_vshrq_m_n_s16): Likewise. (__arm_vshrq_m_n_u8): Likewise. (__arm_vshrq_m_n_u32): Likewise. (__arm_vshrq_m_n_u16): Likewise. (__arm_vsliq_m_n_s8): Likewise. (__arm_vsliq_m_n_s32): Likewise. (__arm_vsliq_m_n_s16): Likewise. (__arm_vsliq_m_n_u8): Likewise. (__arm_vsliq_m_n_u32): Likewise. (__arm_vsliq_m_n_u16): Likewise. (__arm_vsubq_m_n_s8): Likewise. (__arm_vsubq_m_n_s32): Likewise. (__arm_vsubq_m_n_s16): Likewise. (__arm_vsubq_m_n_u8): Likewise. (__arm_vsubq_m_n_u32): Likewise. (__arm_vsubq_m_n_u16): Likewise. (vqdmladhq_m): Define polymorphic variant. (vqdmladhxq_m): Likewise. (vqdmlsdhq_m): Likewise. (vqdmlsdhxq_m): Likewise. (vabdq_m): Likewise. (vandq_m): Likewise. (vbicq_m): Likewise. (vbrsrq_m_n): Likewise. (vcaddq_rot270_m): Likewise. (vcaddq_rot90_m): Likewise. (veorq_m): Likewise. (vmaxq_m): Likewise. (vminq_m): Likewise. (vmladavaq_p): Likewise. (vmlaq_m_n): Likewise. (vmlasq_m_n): Likewise. (vmulhq_m): Likewise. (vmullbq_int_m): Likewise. (vmulltq_int_m): Likewise. (vornq_m): Likewise. (vorrq_m): Likewise. (vqdmlahq_m_n): Likewise. (vqrdmlahq_m_n): Likewise. (vqrdmlashq_m_n): Likewise. (vqrshlq_m): Likewise. (vqshlq_m_n): Likewise. (vqshlq_m): Likewise. (vrhaddq_m): Likewise. (vrmulhq_m): Likewise. (vrshlq_m): Likewise. (vrshrq_m_n): Likewise. (vshlq_m_n): Likewise. (vshrq_m_n): Likewise. (vsliq_m): Likewise. (vaddq_m_n): Likewise. (vaddq_m): Likewise. (vhaddq_m_n): Likewise. (vhaddq_m): Likewise. (vhcaddq_rot270_m): Likewise. (vhcaddq_rot90_m): Likewise. (vhsubq_m): Likewise. (vhsubq_m_n): Likewise. (vmulq_m_n): Likewise. (vmulq_m): Likewise. (vqaddq_m_n): Likewise. (vqaddq_m): Likewise. (vqdmulhq_m_n): Likewise. (vqdmulhq_m): Likewise. (vsubq_m_n): Likewise. (vsliq_m_n): Likewise. (vqsubq_m_n): Likewise. (vqsubq_m): Likewise. (vqrdmulhq_m): Likewise. (vqrdmulhq_m_n): Likewise. (vqrdmlsdhxq_m): Likewise. (vqrdmlsdhq_m): Likewise. (vqrdmladhq_m): Likewise. (vqrdmladhxq_m): Likewise. (vmlsdavaxq_p): Likewise. (vmlsdavaq_p): Likewise. (vmladavaxq_p): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (VHSUBQ_M): Define iterators. (VSLIQ_M_N): Likewise. (VQRDMLAHQ_M_N): Likewise. (VRSHLQ_M): Likewise. (VMINQ_M): Likewise. (VMULLBQ_INT_M): Likewise. (VMULHQ_M): Likewise. (VMULQ_M): Likewise. (VHSUBQ_M_N): Likewise. (VHADDQ_M_N): Likewise. (VORRQ_M): Likewise. (VRMULHQ_M): Likewise. (VQADDQ_M): Likewise. (VRSHRQ_M_N): Likewise. (VQSUBQ_M_N): Likewise. (VADDQ_M): Likewise. (VORNQ_M): Likewise. (VQDMLAHQ_M_N): Likewise. (VRHADDQ_M): Likewise. (VQSHLQ_M): Likewise. (VANDQ_M): Likewise. (VBICQ_M): Likewise. (VSHLQ_M_N): Likewise. (VCADDQ_ROT270_M): Likewise. (VQRSHLQ_M): Likewise. (VQADDQ_M_N): Likewise. (VADDQ_M_N): Likewise. (VMAXQ_M): Likewise. (VQSUBQ_M): Likewise. (VMLASQ_M_N): Likewise. (VMLADAVAQ_P): Likewise. (VBRSRQ_M_N): Likewise. (VMULQ_M_N): Likewise. (VCADDQ_ROT90_M): Likewise. (VMULLTQ_INT_M): Likewise. (VEORQ_M): Likewise. (VSHRQ_M_N): Likewise. (VSUBQ_M_N): Likewise. (VHADDQ_M): Likewise. (VABDQ_M): Likewise. (VQRDMLASHQ_M_N): Likewise. (VMLAQ_M_N): Likewise. (VQSHLQ_M_N): Likewise. (mve_vabdq_m_): Define RTL pattern. (mve_vaddq_m_n_): Likewise. (mve_vaddq_m_): Likewise. (mve_vandq_m_): Likewise. (mve_vbicq_m_): Likewise. (mve_vbrsrq_m_n_): Likewise. (mve_vcaddq_rot270_m_): Likewise. (mve_vcaddq_rot90_m_): Likewise. (mve_veorq_m_): Likewise. (mve_vhaddq_m_n_): Likewise. (mve_vhaddq_m_): Likewise. (mve_vhsubq_m_n_): Likewise. (mve_vhsubq_m_): Likewise. (mve_vmaxq_m_): Likewise. (mve_vminq_m_): Likewise. (mve_vmladavaq_p_): Likewise. (mve_vmlaq_m_n_): Likewise. (mve_vmlasq_m_n_): Likewise. (mve_vmulhq_m_): Likewise. (mve_vmullbq_int_m_): Likewise. (mve_vmulltq_int_m_): Likewise. (mve_vmulq_m_n_): Likewise. (mve_vmulq_m_): Likewise. (mve_vornq_m_): Likewise. (mve_vorrq_m_): Likewise. (mve_vqaddq_m_n_): Likewise. (mve_vqaddq_m_): Likewise. (mve_vqdmlahq_m_n_): Likewise. (mve_vqrdmlahq_m_n_): Likewise. (mve_vqrdmlashq_m_n_): Likewise. (mve_vqrshlq_m_): Likewise. (mve_vqshlq_m_n_): Likewise. (mve_vqshlq_m_): Likewise. (mve_vqsubq_m_n_): Likewise. (mve_vqsubq_m_): Likewise. (mve_vrhaddq_m_): Likewise. (mve_vrmulhq_m_): Likewise. (mve_vrshlq_m_): Likewise. (mve_vrshrq_m_n_): Likewise. (mve_vshlq_m_n_): Likewise. (mve_vshrq_m_n_): Likewise. (mve_vsliq_m_n_): Likewise. (mve_vsubq_m_n_): Likewise. (mve_vhcaddq_rot270_m_s): Likewise. (mve_vhcaddq_rot90_m_s): Likewise. (mve_vmladavaxq_p_s): Likewise. (mve_vmlsdavaq_p_s): Likewise. (mve_vmlsdavaxq_p_s): Likewise. (mve_vqdmladhq_m_s): Likewise. (mve_vqdmladhxq_m_s): Likewise. (mve_vqdmlsdhq_m_s): Likewise. (mve_vqdmlsdhxq_m_s): Likewise. (mve_vqdmulhq_m_n_s): Likewise. (mve_vqdmulhq_m_s): Likewise. (mve_vqrdmladhq_m_s): Likewise. (mve_vqrdmladhxq_m_s): Likewise. (mve_vqrdmlsdhq_m_s): Likewise. (mve_vqrdmlsdhxq_m_s): Likewise. (mve_vqrdmulhq_m_n_s): Likewise. (mve_vqrdmulhq_m_s): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Define builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro. (vsubq_m_s8): Likewise. (vcvtq_m_n_f16_u16): Likewise. (vqshluq_m_n_s8): Likewise. (vabavq_p_s8): Likewise. (vsriq_m_n_u8): Likewise. (vshlq_m_u8): Likewise. (vsubq_m_u8): Likewise. (vabavq_p_u8): Likewise. (vshlq_m_s8): Likewise. (vcvtq_m_n_f16_s16): Likewise. (vsriq_m_n_s16): Likewise. (vsubq_m_s16): Likewise. (vcvtq_m_n_f32_u32): Likewise. (vqshluq_m_n_s16): Likewise. (vabavq_p_s16): Likewise. (vsriq_m_n_u16): Likewise. (vshlq_m_u16): Likewise. (vsubq_m_u16): Likewise. (vabavq_p_u16): Likewise. (vshlq_m_s16): Likewise. (vcvtq_m_n_f32_s32): Likewise. (vsriq_m_n_s32): Likewise. (vsubq_m_s32): Likewise. (vqshluq_m_n_s32): Likewise. (vabavq_p_s32): Likewise. (vsriq_m_n_u32): Likewise. (vshlq_m_u32): Likewise. (vsubq_m_u32): Likewise. (vabavq_p_u32): Likewise. (vshlq_m_s32): Likewise. (__arm_vsriq_m_n_s8): Define intrinsic. (__arm_vsubq_m_s8): Likewise. (__arm_vqshluq_m_n_s8): Likewise. (__arm_vabavq_p_s8): Likewise. (__arm_vsriq_m_n_u8): Likewise. (__arm_vshlq_m_u8): Likewise. (__arm_vsubq_m_u8): Likewise. (__arm_vabavq_p_u8): Likewise. (__arm_vshlq_m_s8): Likewise. (__arm_vsriq_m_n_s16): Likewise. (__arm_vsubq_m_s16): Likewise. (__arm_vqshluq_m_n_s16): Likewise. (__arm_vabavq_p_s16): Likewise. (__arm_vsriq_m_n_u16): Likewise. (__arm_vshlq_m_u16): Likewise. (__arm_vsubq_m_u16): Likewise. (__arm_vabavq_p_u16): Likewise. (__arm_vshlq_m_s16): Likewise. (__arm_vsriq_m_n_s32): Likewise. (__arm_vsubq_m_s32): Likewise. (__arm_vqshluq_m_n_s32): Likewise. (__arm_vabavq_p_s32): Likewise. (__arm_vsriq_m_n_u32): Likewise. (__arm_vshlq_m_u32): Likewise. (__arm_vsubq_m_u32): Likewise. (__arm_vabavq_p_u32): Likewise. (__arm_vshlq_m_s32): Likewise. (__arm_vcvtq_m_n_f16_u16): Likewise. (__arm_vcvtq_m_n_f16_s16): Likewise. (__arm_vcvtq_m_n_f32_u32): Likewise. (__arm_vcvtq_m_n_f32_s32): Likewise. (vcvtq_m_n): Define polymorphic variant. (vqshluq_m_n): Likewise. (vshlq_m): Likewise. (vsriq_m_n): Likewise. (vsubq_m): Likewise. (vabavq_p): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/mve.md (VABAVQ_P): Define iterator. (VSHLQ_M): Likewise. (VSRIQ_M_N): Likewise. (VSUBQ_M): Likewise. (VCVTQ_M_N_TO_F): Likewise. (mve_vabavq_p_): Define RTL pattern. (mve_vqshluq_m_n_s): Likewise. (mve_vshlq_m_): Likewise. (mve_vsriq_m_n_): Likewise. (mve_vsubq_m_): Likewise. (mve_vcvtq_m_n_to_f_): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro. (vrmlsldavhaq_s32): Likewise. (vrmlsldavhaxq_s32): Likewise. (vaddlvaq_p_s32): Likewise. (vcvtbq_m_f16_f32): Likewise. (vcvtbq_m_f32_f16): Likewise. (vcvttq_m_f16_f32): Likewise. (vcvttq_m_f32_f16): Likewise. (vrev16q_m_s8): Likewise. (vrev32q_m_f16): Likewise. (vrmlaldavhq_p_s32): Likewise. (vrmlaldavhxq_p_s32): Likewise. (vrmlsldavhq_p_s32): Likewise. (vrmlsldavhxq_p_s32): Likewise. (vaddlvaq_p_u32): Likewise. (vrev16q_m_u8): Likewise. (vrmlaldavhq_p_u32): Likewise. (vmvnq_m_n_s16): Likewise. (vorrq_m_n_s16): Likewise. (vqrshrntq_n_s16): Likewise. (vqshrnbq_n_s16): Likewise. (vqshrntq_n_s16): Likewise. (vrshrnbq_n_s16): Likewise. (vrshrntq_n_s16): Likewise. (vshrnbq_n_s16): Likewise. (vshrntq_n_s16): Likewise. (vcmlaq_f16): Likewise. (vcmlaq_rot180_f16): Likewise. (vcmlaq_rot270_f16): Likewise. (vcmlaq_rot90_f16): Likewise. (vfmaq_f16): Likewise. (vfmaq_n_f16): Likewise. (vfmasq_n_f16): Likewise. (vfmsq_f16): Likewise. (vmlaldavaq_s16): Likewise. (vmlaldavaxq_s16): Likewise. (vmlsldavaq_s16): Likewise. (vmlsldavaxq_s16): Likewise. (vabsq_m_f16): Likewise. (vcvtmq_m_s16_f16): Likewise. (vcvtnq_m_s16_f16): Likewise. (vcvtpq_m_s16_f16): Likewise. (vcvtq_m_s16_f16): Likewise. (vdupq_m_n_f16): Likewise. (vmaxnmaq_m_f16): Likewise. (vmaxnmavq_p_f16): Likewise. (vmaxnmvq_p_f16): Likewise. (vminnmaq_m_f16): Likewise. (vminnmavq_p_f16): Likewise. (vminnmvq_p_f16): Likewise. (vmlaldavq_p_s16): Likewise. (vmlaldavxq_p_s16): Likewise. (vmlsldavq_p_s16): Likewise. (vmlsldavxq_p_s16): Likewise. (vmovlbq_m_s8): Likewise. (vmovltq_m_s8): Likewise. (vmovnbq_m_s16): Likewise. (vmovntq_m_s16): Likewise. (vnegq_m_f16): Likewise. (vpselq_f16): Likewise. (vqmovnbq_m_s16): Likewise. (vqmovntq_m_s16): Likewise. (vrev32q_m_s8): Likewise. (vrev64q_m_f16): Likewise. (vrndaq_m_f16): Likewise. (vrndmq_m_f16): Likewise. (vrndnq_m_f16): Likewise. (vrndpq_m_f16): Likewise. (vrndq_m_f16): Likewise. (vrndxq_m_f16): Likewise. (vcmpeqq_m_n_f16): Likewise. (vcmpgeq_m_f16): Likewise. (vcmpgeq_m_n_f16): Likewise. (vcmpgtq_m_f16): Likewise. (vcmpgtq_m_n_f16): Likewise. (vcmpleq_m_f16): Likewise. (vcmpleq_m_n_f16): Likewise. (vcmpltq_m_f16): Likewise. (vcmpltq_m_n_f16): Likewise. (vcmpneq_m_f16): Likewise. (vcmpneq_m_n_f16): Likewise. (vmvnq_m_n_u16): Likewise. (vorrq_m_n_u16): Likewise. (vqrshruntq_n_s16): Likewise. (vqshrunbq_n_s16): Likewise. (vqshruntq_n_s16): Likewise. (vcvtmq_m_u16_f16): Likewise. (vcvtnq_m_u16_f16): Likewise. (vcvtpq_m_u16_f16): Likewise. (vcvtq_m_u16_f16): Likewise. (vqmovunbq_m_s16): Likewise. (vqmovuntq_m_s16): Likewise. (vqrshrntq_n_u16): Likewise. (vqshrnbq_n_u16): Likewise. (vqshrntq_n_u16): Likewise. (vrshrnbq_n_u16): Likewise. (vrshrntq_n_u16): Likewise. (vshrnbq_n_u16): Likewise. (vshrntq_n_u16): Likewise. (vmlaldavaq_u16): Likewise. (vmlaldavaxq_u16): Likewise. (vmlaldavq_p_u16): Likewise. (vmlaldavxq_p_u16): Likewise. (vmovlbq_m_u8): Likewise. (vmovltq_m_u8): Likewise. (vmovnbq_m_u16): Likewise. (vmovntq_m_u16): Likewise. (vqmovnbq_m_u16): Likewise. (vqmovntq_m_u16): Likewise. (vrev32q_m_u8): Likewise. (vmvnq_m_n_s32): Likewise. (vorrq_m_n_s32): Likewise. (vqrshrntq_n_s32): Likewise. (vqshrnbq_n_s32): Likewise. (vqshrntq_n_s32): Likewise. (vrshrnbq_n_s32): Likewise. (vrshrntq_n_s32): Likewise. (vshrnbq_n_s32): Likewise. (vshrntq_n_s32): Likewise. (vcmlaq_f32): Likewise. (vcmlaq_rot180_f32): Likewise. (vcmlaq_rot270_f32): Likewise. (vcmlaq_rot90_f32): Likewise. (vfmaq_f32): Likewise. (vfmaq_n_f32): Likewise. (vfmasq_n_f32): Likewise. (vfmsq_f32): Likewise. (vmlaldavaq_s32): Likewise. (vmlaldavaxq_s32): Likewise. (vmlsldavaq_s32): Likewise. (vmlsldavaxq_s32): Likewise. (vabsq_m_f32): Likewise. (vcvtmq_m_s32_f32): Likewise. (vcvtnq_m_s32_f32): Likewise. (vcvtpq_m_s32_f32): Likewise. (vcvtq_m_s32_f32): Likewise. (vdupq_m_n_f32): Likewise. (vmaxnmaq_m_f32): Likewise. (vmaxnmavq_p_f32): Likewise. (vmaxnmvq_p_f32): Likewise. (vminnmaq_m_f32): Likewise. (vminnmavq_p_f32): Likewise. (vminnmvq_p_f32): Likewise. (vmlaldavq_p_s32): Likewise. (vmlaldavxq_p_s32): Likewise. (vmlsldavq_p_s32): Likewise. (vmlsldavxq_p_s32): Likewise. (vmovlbq_m_s16): Likewise. (vmovltq_m_s16): Likewise. (vmovnbq_m_s32): Likewise. (vmovntq_m_s32): Likewise. (vnegq_m_f32): Likewise. (vpselq_f32): Likewise. (vqmovnbq_m_s32): Likewise. (vqmovntq_m_s32): Likewise. (vrev32q_m_s16): Likewise. (vrev64q_m_f32): Likewise. (vrndaq_m_f32): Likewise. (vrndmq_m_f32): Likewise. (vrndnq_m_f32): Likewise. (vrndpq_m_f32): Likewise. (vrndq_m_f32): Likewise. (vrndxq_m_f32): Likewise. (vcmpeqq_m_n_f32): Likewise. (vcmpgeq_m_f32): Likewise. (vcmpgeq_m_n_f32): Likewise. (vcmpgtq_m_f32): Likewise. (vcmpgtq_m_n_f32): Likewise. (vcmpleq_m_f32): Likewise. (vcmpleq_m_n_f32): Likewise. (vcmpltq_m_f32): Likewise. (vcmpltq_m_n_f32): Likewise. (vcmpneq_m_f32): Likewise. (vcmpneq_m_n_f32): Likewise. (vmvnq_m_n_u32): Likewise. (vorrq_m_n_u32): Likewise. (vqrshruntq_n_s32): Likewise. (vqshrunbq_n_s32): Likewise. (vqshruntq_n_s32): Likewise. (vcvtmq_m_u32_f32): Likewise. (vcvtnq_m_u32_f32): Likewise. (vcvtpq_m_u32_f32): Likewise. (vcvtq_m_u32_f32): Likewise. (vqmovunbq_m_s32): Likewise. (vqmovuntq_m_s32): Likewise. (vqrshrntq_n_u32): Likewise. (vqshrnbq_n_u32): Likewise. (vqshrntq_n_u32): Likewise. (vrshrnbq_n_u32): Likewise. (vrshrntq_n_u32): Likewise. (vshrnbq_n_u32): Likewise. (vshrntq_n_u32): Likewise. (vmlaldavaq_u32): Likewise. (vmlaldavaxq_u32): Likewise. (vmlaldavq_p_u32): Likewise. (vmlaldavxq_p_u32): Likewise. (vmovlbq_m_u16): Likewise. (vmovltq_m_u16): Likewise. (vmovnbq_m_u32): Likewise. (vmovntq_m_u32): Likewise. (vqmovnbq_m_u32): Likewise. (vqmovntq_m_u32): Likewise. (vrev32q_m_u16): Likewise. (__arm_vrmlaldavhaxq_s32): Define intrinsic. (__arm_vrmlsldavhaq_s32): Likewise. (__arm_vrmlsldavhaxq_s32): Likewise. (__arm_vaddlvaq_p_s32): Likewise. (__arm_vrev16q_m_s8): Likewise. (__arm_vrmlaldavhq_p_s32): Likewise. (__arm_vrmlaldavhxq_p_s32): Likewise. (__arm_vrmlsldavhq_p_s32): Likewise. (__arm_vrmlsldavhxq_p_s32): Likewise. (__arm_vaddlvaq_p_u32): Likewise. (__arm_vrev16q_m_u8): Likewise. (__arm_vrmlaldavhq_p_u32): Likewise. (__arm_vmvnq_m_n_s16): Likewise. (__arm_vorrq_m_n_s16): Likewise. (__arm_vqrshrntq_n_s16): Likewise. (__arm_vqshrnbq_n_s16): Likewise. (__arm_vqshrntq_n_s16): Likewise. (__arm_vrshrnbq_n_s16): Likewise. (__arm_vrshrntq_n_s16): Likewise. (__arm_vshrnbq_n_s16): Likewise. (__arm_vshrntq_n_s16): Likewise. (__arm_vmlaldavaq_s16): Likewise. (__arm_vmlaldavaxq_s16): Likewise. (__arm_vmlsldavaq_s16): Likewise. (__arm_vmlsldavaxq_s16): Likewise. (__arm_vmlaldavq_p_s16): Likewise. (__arm_vmlaldavxq_p_s16): Likewise. (__arm_vmlsldavq_p_s16): Likewise. (__arm_vmlsldavxq_p_s16): Likewise. (__arm_vmovlbq_m_s8): Likewise. (__arm_vmovltq_m_s8): Likewise. (__arm_vmovnbq_m_s16): Likewise. (__arm_vmovntq_m_s16): Likewise. (__arm_vqmovnbq_m_s16): Likewise. (__arm_vqmovntq_m_s16): Likewise. (__arm_vrev32q_m_s8): Likewise. (__arm_vmvnq_m_n_u16): Likewise. (__arm_vorrq_m_n_u16): Likewise. (__arm_vqrshruntq_n_s16): Likewise. (__arm_vqshrunbq_n_s16): Likewise. (__arm_vqshruntq_n_s16): Likewise. (__arm_vqmovunbq_m_s16): Likewise. (__arm_vqmovuntq_m_s16): Likewise. (__arm_vqrshrntq_n_u16): Likewise. (__arm_vqshrnbq_n_u16): Likewise. (__arm_vqshrntq_n_u16): Likewise. (__arm_vrshrnbq_n_u16): Likewise. (__arm_vrshrntq_n_u16): Likewise. (__arm_vshrnbq_n_u16): Likewise. (__arm_vshrntq_n_u16): Likewise. (__arm_vmlaldavaq_u16): Likewise. (__arm_vmlaldavaxq_u16): Likewise. (__arm_vmlaldavq_p_u16): Likewise. (__arm_vmlaldavxq_p_u16): Likewise. (__arm_vmovlbq_m_u8): Likewise. (__arm_vmovltq_m_u8): Likewise. (__arm_vmovnbq_m_u16): Likewise. (__arm_vmovntq_m_u16): Likewise. (__arm_vqmovnbq_m_u16): Likewise. (__arm_vqmovntq_m_u16): Likewise. (__arm_vrev32q_m_u8): Likewise. (__arm_vmvnq_m_n_s32): Likewise. (__arm_vorrq_m_n_s32): Likewise. (__arm_vqrshrntq_n_s32): Likewise. (__arm_vqshrnbq_n_s32): Likewise. (__arm_vqshrntq_n_s32): Likewise. (__arm_vrshrnbq_n_s32): Likewise. (__arm_vrshrntq_n_s32): Likewise. (__arm_vshrnbq_n_s32): Likewise. (__arm_vshrntq_n_s32): Likewise. (__arm_vmlaldavaq_s32): Likewise. (__arm_vmlaldavaxq_s32): Likewise. (__arm_vmlsldavaq_s32): Likewise. (__arm_vmlsldavaxq_s32): Likewise. (__arm_vmlaldavq_p_s32): Likewise. (__arm_vmlaldavxq_p_s32): Likewise. (__arm_vmlsldavq_p_s32): Likewise. (__arm_vmlsldavxq_p_s32): Likewise. (__arm_vmovlbq_m_s16): Likewise. (__arm_vmovltq_m_s16): Likewise. (__arm_vmovnbq_m_s32): Likewise. (__arm_vmovntq_m_s32): Likewise. (__arm_vqmovnbq_m_s32): Likewise. (__arm_vqmovntq_m_s32): Likewise. (__arm_vrev32q_m_s16): Likewise. (__arm_vmvnq_m_n_u32): Likewise. (__arm_vorrq_m_n_u32): Likewise. (__arm_vqrshruntq_n_s32): Likewise. (__arm_vqshrunbq_n_s32): Likewise. (__arm_vqshruntq_n_s32): Likewise. (__arm_vqmovunbq_m_s32): Likewise. (__arm_vqmovuntq_m_s32): Likewise. (__arm_vqrshrntq_n_u32): Likewise. (__arm_vqshrnbq_n_u32): Likewise. (__arm_vqshrntq_n_u32): Likewise. (__arm_vrshrnbq_n_u32): Likewise. (__arm_vrshrntq_n_u32): Likewise. (__arm_vshrnbq_n_u32): Likewise. (__arm_vshrntq_n_u32): Likewise. (__arm_vmlaldavaq_u32): Likewise. (__arm_vmlaldavaxq_u32): Likewise. (__arm_vmlaldavq_p_u32): Likewise. (__arm_vmlaldavxq_p_u32): Likewise. (__arm_vmovlbq_m_u16): Likewise. (__arm_vmovltq_m_u16): Likewise. (__arm_vmovnbq_m_u32): Likewise. (__arm_vmovntq_m_u32): Likewise. (__arm_vqmovnbq_m_u32): Likewise. (__arm_vqmovntq_m_u32): Likewise. (__arm_vrev32q_m_u16): Likewise. (__arm_vcvtbq_m_f16_f32): Likewise. (__arm_vcvtbq_m_f32_f16): Likewise. (__arm_vcvttq_m_f16_f32): Likewise. (__arm_vcvttq_m_f32_f16): Likewise. (__arm_vrev32q_m_f16): Likewise. (__arm_vcmlaq_f16): Likewise. (__arm_vcmlaq_rot180_f16): Likewise. (__arm_vcmlaq_rot270_f16): Likewise. (__arm_vcmlaq_rot90_f16): Likewise. (__arm_vfmaq_f16): Likewise. (__arm_vfmaq_n_f16): Likewise. (__arm_vfmasq_n_f16): Likewise. (__arm_vfmsq_f16): Likewise. (__arm_vabsq_m_f16): Likewise. (__arm_vcvtmq_m_s16_f16): Likewise. (__arm_vcvtnq_m_s16_f16): Likewise. (__arm_vcvtpq_m_s16_f16): Likewise. (__arm_vcvtq_m_s16_f16): Likewise. (__arm_vdupq_m_n_f16): Likewise. (__arm_vmaxnmaq_m_f16): Likewise. (__arm_vmaxnmavq_p_f16): Likewise. (__arm_vmaxnmvq_p_f16): Likewise. (__arm_vminnmaq_m_f16): Likewise. (__arm_vminnmavq_p_f16): Likewise. (__arm_vminnmvq_p_f16): Likewise. (__arm_vnegq_m_f16): Likewise. (__arm_vpselq_f16): Likewise. (__arm_vrev64q_m_f16): Likewise. (__arm_vrndaq_m_f16): Likewise. (__arm_vrndmq_m_f16): Likewise. (__arm_vrndnq_m_f16): Likewise. (__arm_vrndpq_m_f16): Likewise. (__arm_vrndq_m_f16): Likewise. (__arm_vrndxq_m_f16): Likewise. (__arm_vcmpeqq_m_n_f16): Likewise. (__arm_vcmpgeq_m_f16): Likewise. (__arm_vcmpgeq_m_n_f16): Likewise. (__arm_vcmpgtq_m_f16): Likewise. (__arm_vcmpgtq_m_n_f16): Likewise. (__arm_vcmpleq_m_f16): Likewise. (__arm_vcmpleq_m_n_f16): Likewise. (__arm_vcmpltq_m_f16): Likewise. (__arm_vcmpltq_m_n_f16): Likewise. (__arm_vcmpneq_m_f16): Likewise. (__arm_vcmpneq_m_n_f16): Likewise. (__arm_vcvtmq_m_u16_f16): Likewise. (__arm_vcvtnq_m_u16_f16): Likewise. (__arm_vcvtpq_m_u16_f16): Likewise. (__arm_vcvtq_m_u16_f16): Likewise. (__arm_vcmlaq_f32): Likewise. (__arm_vcmlaq_rot180_f32): Likewise. (__arm_vcmlaq_rot270_f32): Likewise. (__arm_vcmlaq_rot90_f32): Likewise. (__arm_vfmaq_f32): Likewise. (__arm_vfmaq_n_f32): Likewise. (__arm_vfmasq_n_f32): Likewise. (__arm_vfmsq_f32): Likewise. (__arm_vabsq_m_f32): Likewise. (__arm_vcvtmq_m_s32_f32): Likewise. (__arm_vcvtnq_m_s32_f32): Likewise. (__arm_vcvtpq_m_s32_f32): Likewise. (__arm_vcvtq_m_s32_f32): Likewise. (__arm_vdupq_m_n_f32): Likewise. (__arm_vmaxnmaq_m_f32): Likewise. (__arm_vmaxnmavq_p_f32): Likewise. (__arm_vmaxnmvq_p_f32): Likewise. (__arm_vminnmaq_m_f32): Likewise. (__arm_vminnmavq_p_f32): Likewise. (__arm_vminnmvq_p_f32): Likewise. (__arm_vnegq_m_f32): Likewise. (__arm_vpselq_f32): Likewise. (__arm_vrev64q_m_f32): Likewise. (__arm_vrndaq_m_f32): Likewise. (__arm_vrndmq_m_f32): Likewise. (__arm_vrndnq_m_f32): Likewise. (__arm_vrndpq_m_f32): Likewise. (__arm_vrndq_m_f32): Likewise. (__arm_vrndxq_m_f32): Likewise. (__arm_vcmpeqq_m_n_f32): Likewise. (__arm_vcmpgeq_m_f32): Likewise. (__arm_vcmpgeq_m_n_f32): Likewise. (__arm_vcmpgtq_m_f32): Likewise. (__arm_vcmpgtq_m_n_f32): Likewise. (__arm_vcmpleq_m_f32): Likewise. (__arm_vcmpleq_m_n_f32): Likewise. (__arm_vcmpltq_m_f32): Likewise. (__arm_vcmpltq_m_n_f32): Likewise. (__arm_vcmpneq_m_f32): Likewise. (__arm_vcmpneq_m_n_f32): Likewise. (__arm_vcvtmq_m_u32_f32): Likewise. (__arm_vcvtnq_m_u32_f32): Likewise. (__arm_vcvtpq_m_u32_f32): Likewise. (__arm_vcvtq_m_u32_f32): Likewise. (vcvtq_m): Define polymorphic variant. (vabsq_m): Likewise. (vcmlaq): Likewise. (vcmlaq_rot180): Likewise. (vcmlaq_rot270): Likewise. (vcmlaq_rot90): Likewise. (vcmpeqq_m_n): Likewise. (vcmpgeq_m_n): Likewise. (vrndxq_m): Likewise. (vrndq_m): Likewise. (vrndpq_m): Likewise. (vcmpgtq_m_n): Likewise. (vcmpgtq_m): Likewise. (vcmpleq_m): Likewise. (vcmpleq_m_n): Likewise. (vcmpltq_m_n): Likewise. (vcmpltq_m): Likewise. (vcmpneq_m): Likewise. (vcmpneq_m_n): Likewise. (vcvtbq_m): Likewise. (vcvttq_m): Likewise. (vcvtmq_m): Likewise. (vcvtnq_m): Likewise. (vcvtpq_m): Likewise. (vdupq_m_n): Likewise. (vfmaq_n): Likewise. (vfmaq): Likewise. (vfmasq_n): Likewise. (vfmsq): Likewise. (vmaxnmaq_m): Likewise. (vmaxnmavq_m): Likewise. (vmaxnmvq_m): Likewise. (vmaxnmavq_p): Likewise. (vmaxnmvq_p): Likewise. (vminnmaq_m): Likewise. (vminnmavq_p): Likewise. (vminnmvq_p): Likewise. (vrndnq_m): Likewise. (vrndaq_m): Likewise. (vrndmq_m): Likewise. (vrev64q_m): Likewise. (vrev32q_m): Likewise. (vpselq): Likewise. (vnegq_m): Likewise. (vcmpgeq_m): Likewise. (vshrntq_n): Likewise. (vrshrntq_n): Likewise. (vmovlbq_m): Likewise. (vmovnbq_m): Likewise. (vmovntq_m): Likewise. (vmvnq_m_n): Likewise. (vmvnq_m): Likewise. (vshrnbq_n): Likewise. (vrshrnbq_n): Likewise. (vqshruntq_n): Likewise. (vrev16q_m): Likewise. (vqshrunbq_n): Likewise. (vqshrntq_n): Likewise. (vqrshruntq_n): Likewise. (vqrshrntq_n): Likewise. (vqshrnbq_n): Likewise. (vqmovuntq_m): Likewise. (vqmovntq_m): Likewise. (vqmovnbq_m): Likewise. (vorrq_m_n): Likewise. (vmovltq_m): Likewise. (vqmovunbq_m): Likewise. (vaddlvaq_p): Likewise. (vmlaldavaq): Likewise. (vmlaldavaxq): Likewise. (vmlaldavq_p): Likewise. (vmlaldavxq_p): Likewise. (vmlsldavaq): Likewise. (vmlsldavaxq): Likewise. (vmlsldavq_p): Likewise. (vmlsldavxq_p): Likewise. (vrmlaldavhaxq): Likewise. (vrmlaldavhq_p): Likewise. (vrmlaldavhxq_p): Likewise. (vrmlsldavhaq): Likewise. (vrmlsldavhaxq): Likewise. (vrmlsldavhq_p): Likewise. (vrmlsldavhxq_p): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use builtin qualifier. (TERNOP_NONE_NONE_NONE_IMM): Likewise. (TERNOP_NONE_NONE_NONE_NONE): Likewise. (TERNOP_NONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise. (TERNOP_UNONE_UNONE_NONE_IMM): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator. (MVE_pred3): Likewise. (MVE_constraint1): Likewise. (MVE_pred1): Likewise. (VMLALDAVQ_P): Define iterator. (VQMOVNBQ_M): Likewise. (VMOVLTQ_M): Likewise. (VMOVNBQ_M): Likewise. (VRSHRNTQ_N): Likewise. (VORRQ_M_N): Likewise. (VREV32Q_M): Likewise. (VREV16Q_M): Likewise. (VQRSHRNTQ_N): Likewise. (VMOVNTQ_M): Likewise. (VMOVLBQ_M): Likewise. (VMLALDAVAQ): Likewise. (VQSHRNBQ_N): Likewise. (VSHRNBQ_N): Likewise. (VRSHRNBQ_N): Likewise. (VMLALDAVXQ_P): Likewise. (VQMOVNTQ_M): Likewise. (VMVNQ_M_N): Likewise. (VQSHRNTQ_N): Likewise. (VMLALDAVAXQ): Likewise. (VSHRNTQ_N): Likewise. (VCVTMQ_M): Likewise. (VCVTNQ_M): Likewise. (VCVTPQ_M): Likewise. (VCVTQ_M_N_FROM_F): Likewise. (VCVTQ_M_FROM_F): Likewise. (VRMLALDAVHQ_P): Likewise. (VADDLVAQ_P): Likewise. (mve_vrndq_m_f): Define RTL pattern. (mve_vabsq_m_f): Likewise. (mve_vaddlvaq_p_v4si): Likewise. (mve_vcmlaq_f): Likewise. (mve_vcmlaq_rot180_f): Likewise. (mve_vcmlaq_rot270_f): Likewise. (mve_vcmlaq_rot90_f): Likewise. (mve_vcmpeqq_m_n_f): Likewise. (mve_vcmpgeq_m_f): Likewise. (mve_vcmpgeq_m_n_f): Likewise. (mve_vcmpgtq_m_f): Likewise. (mve_vcmpgtq_m_n_f): Likewise. (mve_vcmpleq_m_f): Likewise. (mve_vcmpleq_m_n_f): Likewise. (mve_vcmpltq_m_f): Likewise. (mve_vcmpltq_m_n_f): Likewise. (mve_vcmpneq_m_f): Likewise. (mve_vcmpneq_m_n_f): Likewise. (mve_vcvtbq_m_f16_f32v8hf): Likewise. (mve_vcvtbq_m_f32_f16v4sf): Likewise. (mve_vcvttq_m_f16_f32v8hf): Likewise. (mve_vcvttq_m_f32_f16v4sf): Likewise. (mve_vdupq_m_n_f): Likewise. (mve_vfmaq_f): Likewise. (mve_vfmaq_n_f): Likewise. (mve_vfmasq_n_f): Likewise. (mve_vfmsq_f): Likewise. (mve_vmaxnmaq_m_f): Likewise. (mve_vmaxnmavq_p_f): Likewise. (mve_vmaxnmvq_p_f): Likewise. (mve_vminnmaq_m_f): Likewise. (mve_vminnmavq_p_f): Likewise. (mve_vminnmvq_p_f): Likewise. (mve_vmlaldavaq_): Likewise. (mve_vmlaldavaxq_): Likewise. (mve_vmlaldavq_p_): Likewise. (mve_vmlaldavxq_p_): Likewise. (mve_vmlsldavaq_s): Likewise. (mve_vmlsldavaxq_s): Likewise. (mve_vmlsldavq_p_s): Likewise. (mve_vmlsldavxq_p_s): Likewise. (mve_vmovlbq_m_): Likewise. (mve_vmovltq_m_): Likewise. (mve_vmovnbq_m_): Likewise. (mve_vmovntq_m_): Likewise. (mve_vmvnq_m_n_): Likewise. (mve_vnegq_m_f): Likewise. (mve_vorrq_m_n_): Likewise. (mve_vpselq_f): Likewise. (mve_vqmovnbq_m_): Likewise. (mve_vqmovntq_m_): Likewise. (mve_vqmovunbq_m_s): Likewise. (mve_vqmovuntq_m_s): Likewise. (mve_vqrshrntq_n_): Likewise. (mve_vqrshruntq_n_s): Likewise. (mve_vqshrnbq_n_): Likewise. (mve_vqshrntq_n_): Likewise. (mve_vqshrunbq_n_s): Likewise. (mve_vqshruntq_n_s): Likewise. (mve_vrev32q_m_fv8hf): Likewise. (mve_vrev32q_m_): Likewise. (mve_vrev64q_m_f): Likewise. (mve_vrmlaldavhaxq_sv4si): Likewise. (mve_vrmlaldavhxq_p_sv4si): Likewise. (mve_vrmlsldavhaxq_sv4si): Likewise. (mve_vrmlsldavhq_p_sv4si): Likewise. (mve_vrmlsldavhxq_p_sv4si): Likewise. (mve_vrndaq_m_f): Likewise. (mve_vrndmq_m_f): Likewise. (mve_vrndnq_m_f): Likewise. (mve_vrndpq_m_f): Likewise. (mve_vrndxq_m_f): Likewise. (mve_vrshrnbq_n_): Likewise. (mve_vrshrntq_n_): Likewise. (mve_vshrnbq_n_): Likewise. (mve_vshrntq_n_): Likewise. (mve_vcvtmq_m_): Likewise. (mve_vcvtpq_m_): Likewise. (mve_vcvtnq_m_): Likewise. (mve_vcvtq_m_n_from_f_): Likewise. (mve_vrev16q_m_v16qi): Likewise. (mve_vcvtq_m_from_f_): Likewise. (mve_vrmlaldavhq_p_v4si): Likewise. (mve_vrmlsldavhaq_sv4si): Likewise. 2020-03-18 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vpselq_u8): Define macro. (vpselq_s8): Likewise. (vrev64q_m_u8): Likewise. (vqrdmlashq_n_u8): Likewise. (vqrdmlahq_n_u8): Likewise. (vqdmlahq_n_u8): Likewise. (vmvnq_m_u8): Likewise. (vmlasq_n_u8): Likewise. (vmlaq_n_u8): Likewise. (vmladavq_p_u8): Likewise. (vmladavaq_u8): Likewise. (vminvq_p_u8): Likewise. (vmaxvq_p_u8): Likewise. (vdupq_m_n_u8): Likewise. (vcmpneq_m_u8): Likewise. (vcmpneq_m_n_u8): Likewise. (vcmphiq_m_u8): Likewise. (vcmphiq_m_n_u8): Likewise. (vcmpeqq_m_u8): Likewise. (vcmpeqq_m_n_u8): Likewise. (vcmpcsq_m_u8): Likewise. (vcmpcsq_m_n_u8): Likewise. (vclzq_m_u8): Likewise. (vaddvaq_p_u8): Likewise. (vsriq_n_u8): Likewise. (vsliq_n_u8): Likewise. (vshlq_m_r_u8): Likewise. (vrshlq_m_n_u8): Likewise. (vqshlq_m_r_u8): Likewise. (vqrshlq_m_n_u8): Likewise. (vminavq_p_s8): Likewise. (vminaq_m_s8): Likewise. (vmaxavq_p_s8): Likewise. (vmaxaq_m_s8): Likewise. (vcmpneq_m_s8): Likewise. (vcmpneq_m_n_s8): Likewise. (vcmpltq_m_s8): Likewise. (vcmpltq_m_n_s8): Likewise. (vcmpleq_m_s8): Likewise. (vcmpleq_m_n_s8): Likewise. (vcmpgtq_m_s8): Likewise. (vcmpgtq_m_n_s8): Likewise. (vcmpgeq_m_s8): Likewise. (vcmpgeq_m_n_s8): Likewise. (vcmpeqq_m_s8): Likewise. (vcmpeqq_m_n_s8): Likewise. (vshlq_m_r_s8): Likewise. (vrshlq_m_n_s8): Likewise. (vrev64q_m_s8): Likewise. (vqshlq_m_r_s8): Likewise. (vqrshlq_m_n_s8): Likewise. (vqnegq_m_s8): Likewise. (vqabsq_m_s8): Likewise. (vnegq_m_s8): Likewise. (vmvnq_m_s8): Likewise. (vmlsdavxq_p_s8): Likewise. (vmlsdavq_p_s8): Likewise. (vmladavxq_p_s8): Likewise. (vmladavq_p_s8): Likewise. (vminvq_p_s8): Likewise. (vmaxvq_p_s8): Likewise. (vdupq_m_n_s8): Likewise. (vclzq_m_s8): Likewise. (vclsq_m_s8): Likewise. (vaddvaq_p_s8): Likewise. (vabsq_m_s8): Likewise. (vqrdmlsdhxq_s8): Likewise. (vqrdmlsdhq_s8): Likewise. (vqrdmlashq_n_s8): Likewise. (vqrdmlahq_n_s8): Likewise. (vqrdmladhxq_s8): Likewise. (vqrdmladhq_s8): Likewise. (vqdmlsdhxq_s8): Likewise. (vqdmlsdhq_s8): Likewise. (vqdmlahq_n_s8): Likewise. (vqdmladhxq_s8): Likewise. (vqdmladhq_s8): Likewise. (vmlsdavaxq_s8): Likewise. (vmlsdavaq_s8): Likewise. (vmlasq_n_s8): Likewise. (vmlaq_n_s8): Likewise. (vmladavaxq_s8): Likewise. (vmladavaq_s8): Likewise. (vsriq_n_s8): Likewise. (vsliq_n_s8): Likewise. (vpselq_u16): Likewise. (vpselq_s16): Likewise. (vrev64q_m_u16): Likewise. (vqrdmlashq_n_u16): Likewise. (vqrdmlahq_n_u16): Likewise. (vqdmlahq_n_u16): Likewise. (vmvnq_m_u16): Likewise. (vmlasq_n_u16): Likewise. (vmlaq_n_u16): Likewise. (vmladavq_p_u16): Likewise. (vmladavaq_u16): Likewise. (vminvq_p_u16): Likewise. (vmaxvq_p_u16): Likewise. (vdupq_m_n_u16): Likewise. (vcmpneq_m_u16): Likewise. (vcmpneq_m_n_u16): Likewise. (vcmphiq_m_u16): Likewise. (vcmphiq_m_n_u16): Likewise. (vcmpeqq_m_u16): Likewise. (vcmpeqq_m_n_u16): Likewise. (vcmpcsq_m_u16): Likewise. (vcmpcsq_m_n_u16): Likewise. (vclzq_m_u16): Likewise. (vaddvaq_p_u16): Likewise. (vsriq_n_u16): Likewise. (vsliq_n_u16): Likewise. (vshlq_m_r_u16): Likewise. (vrshlq_m_n_u16): Likewise. (vqshlq_m_r_u16): Likewise. (vqrshlq_m_n_u16): Likewise. (vminavq_p_s16): Likewise. (vminaq_m_s16): Likewise. (vmaxavq_p_s16): Likewise. (vmaxaq_m_s16): Likewise. (vcmpneq_m_s16): Likewise. (vcmpneq_m_n_s16): Likewise. (vcmpltq_m_s16): Likewise. (vcmpltq_m_n_s16): Likewise. (vcmpleq_m_s16): Likewise. (vcmpleq_m_n_s16): Likewise. (vcmpgtq_m_s16): Likewise. (vcmpgtq_m_n_s16): Likewise. (vcmpgeq_m_s16): Likewise. (vcmpgeq_m_n_s16): Likewise. (vcmpeqq_m_s16): Likewise. (vcmpeqq_m_n_s16): Likewise. (vshlq_m_r_s16): Likewise. (vrshlq_m_n_s16): Likewise. (vrev64q_m_s16): Likewise. (vqshlq_m_r_s16): Likewise. (vqrshlq_m_n_s16): Likewise. (vqnegq_m_s16): Likewise. (vqabsq_m_s16): Likewise. (vnegq_m_s16): Likewise. (vmvnq_m_s16): Likewise. (vmlsdavxq_p_s16): Likewise. (vmlsdavq_p_s16): Likewise. (vmladavxq_p_s16): Likewise. (vmladavq_p_s16): Likewise. (vminvq_p_s16): Likewise. (vmaxvq_p_s16): Likewise. (vdupq_m_n_s16): Likewise. (vclzq_m_s16): Likewise. (vclsq_m_s16): Likewise. (vaddvaq_p_s16): Likewise. (vabsq_m_s16): Likewise. (vqrdmlsdhxq_s16): Likewise. (vqrdmlsdhq_s16): Likewise. (vqrdmlashq_n_s16): Likewise. (vqrdmlahq_n_s16): Likewise. (vqrdmladhxq_s16): Likewise. (vqrdmladhq_s16): Likewise. (vqdmlsdhxq_s16): Likewise. (vqdmlsdhq_s16): Likewise. (vqdmlahq_n_s16): Likewise. (vqdmladhxq_s16): Likewise. (vqdmladhq_s16): Likewise. (vmlsdavaxq_s16): Likewise. (vmlsdavaq_s16): Likewise. (vmlasq_n_s16): Likewise. (vmlaq_n_s16): Likewise. (vmladavaxq_s16): Likewise. (vmladavaq_s16): Likewise. (vsriq_n_s16): Likewise. (vsliq_n_s16): Likewise. (vpselq_u32): Likewise. (vpselq_s32): Likewise. (vrev64q_m_u32): Likewise. (vqrdmlashq_n_u32): Likewise. (vqrdmlahq_n_u32): Likewise. (vqdmlahq_n_u32): Likewise. (vmvnq_m_u32): Likewise. (vmlasq_n_u32): Likewise. (vmlaq_n_u32): Likewise. (vmladavq_p_u32): Likewise. (vmladavaq_u32): Likewise. (vminvq_p_u32): Likewise. (vmaxvq_p_u32): Likewise. (vdupq_m_n_u32): Likewise. (vcmpneq_m_u32): Likewise. (vcmpneq_m_n_u32): Likewise. (vcmphiq_m_u32): Likewise. (vcmphiq_m_n_u32): Likewise. (vcmpeqq_m_u32): Likewise. (vcmpeqq_m_n_u32): Likewise. (vcmpcsq_m_u32): Likewise. (vcmpcsq_m_n_u32): Likewise. (vclzq_m_u32): Likewise. (vaddvaq_p_u32): Likewise. (vsriq_n_u32): Likewise. (vsliq_n_u32): Likewise. (vshlq_m_r_u32): Likewise. (vrshlq_m_n_u32): Likewise. (vqshlq_m_r_u32): Likewise. (vqrshlq_m_n_u32): Likewise. (vminavq_p_s32): Likewise. (vminaq_m_s32): Likewise. (vmaxavq_p_s32): Likewise. (vmaxaq_m_s32): Likewise. (vcmpneq_m_s32): Likewise. (vcmpneq_m_n_s32): Likewise. (vcmpltq_m_s32): Likewise. (vcmpltq_m_n_s32): Likewise. (vcmpleq_m_s32): Likewise. (vcmpleq_m_n_s32): Likewise. (vcmpgtq_m_s32): Likewise. (vcmpgtq_m_n_s32): Likewise. (vcmpgeq_m_s32): Likewise. (vcmpgeq_m_n_s32): Likewise. (vcmpeqq_m_s32): Likewise. (vcmpeqq_m_n_s32): Likewise. (vshlq_m_r_s32): Likewise. (vrshlq_m_n_s32): Likewise. (vrev64q_m_s32): Likewise. (vqshlq_m_r_s32): Likewise. (vqrshlq_m_n_s32): Likewise. (vqnegq_m_s32): Likewise. (vqabsq_m_s32): Likewise. (vnegq_m_s32): Likewise. (vmvnq_m_s32): Likewise. (vmlsdavxq_p_s32): Likewise. (vmlsdavq_p_s32): Likewise. (vmladavxq_p_s32): Likewise. (vmladavq_p_s32): Likewise. (vminvq_p_s32): Likewise. (vmaxvq_p_s32): Likewise. (vdupq_m_n_s32): Likewise. (vclzq_m_s32): Likewise. (vclsq_m_s32): Likewise. (vaddvaq_p_s32): Likewise. (vabsq_m_s32): Likewise. (vqrdmlsdhxq_s32): Likewise. (vqrdmlsdhq_s32): Likewise. (vqrdmlashq_n_s32): Likewise. (vqrdmlahq_n_s32): Likewise. (vqrdmladhxq_s32): Likewise. (vqrdmladhq_s32): Likewise. (vqdmlsdhxq_s32): Likewise. (vqdmlsdhq_s32): Likewise. (vqdmlahq_n_s32): Likewise. (vqdmladhxq_s32): Likewise. (vqdmladhq_s32): Likewise. (vmlsdavaxq_s32): Likewise. (vmlsdavaq_s32): Likewise. (vmlasq_n_s32): Likewise. (vmlaq_n_s32): Likewise. (vmladavaxq_s32): Likewise. (vmladavaq_s32): Likewise. (vsriq_n_s32): Likewise. (vsliq_n_s32): Likewise. (vpselq_u64): Likewise. (vpselq_s64): Likewise. (__arm_vpselq_u8): Define intrinsic. (__arm_vpselq_s8): Likewise. (__arm_vrev64q_m_u8): Likewise. (__arm_vqrdmlashq_n_u8): Likewise. (__arm_vqrdmlahq_n_u8): Likewise. (__arm_vqdmlahq_n_u8): Likewise. (__arm_vmvnq_m_u8): Likewise. (__arm_vmlasq_n_u8): Likewise. (__arm_vmlaq_n_u8): Likewise. (__arm_vmladavq_p_u8): Likewise. (__arm_vmladavaq_u8): Likewise. (__arm_vminvq_p_u8): Likewise. (__arm_vmaxvq_p_u8): Likewise. (__arm_vdupq_m_n_u8): Likewise. (__arm_vcmpneq_m_u8): Likewise. (__arm_vcmpneq_m_n_u8): Likewise. (__arm_vcmphiq_m_u8): Likewise. (__arm_vcmphiq_m_n_u8): Likewise. (__arm_vcmpeqq_m_u8): Likewise. (__arm_vcmpeqq_m_n_u8): Likewise. (__arm_vcmpcsq_m_u8): Likewise. (__arm_vcmpcsq_m_n_u8): Likewise. (__arm_vclzq_m_u8): Likewise. (__arm_vaddvaq_p_u8): Likewise. (__arm_vsriq_n_u8): Likewise. (__arm_vsliq_n_u8): Likewise. (__arm_vshlq_m_r_u8): Likewise. (__arm_vrshlq_m_n_u8): Likewise. (__arm_vqshlq_m_r_u8): Likewise. (__arm_vqrshlq_m_n_u8): Likewise. (__arm_vminavq_p_s8): Likewise. (__arm_vminaq_m_s8): Likewise. (__arm_vmaxavq_p_s8): Likewise. (__arm_vmaxaq_m_s8): Likewise. (__arm_vcmpneq_m_s8): Likewise. (__arm_vcmpneq_m_n_s8): Likewise. (__arm_vcmpltq_m_s8): Likewise. (__arm_vcmpltq_m_n_s8): Likewise. (__arm_vcmpleq_m_s8): Likewise. (__arm_vcmpleq_m_n_s8): Likewise. (__arm_vcmpgtq_m_s8): Likewise. (__arm_vcmpgtq_m_n_s8): Likewise. (__arm_vcmpgeq_m_s8): Likewise. (__arm_vcmpgeq_m_n_s8): Likewise. (__arm_vcmpeqq_m_s8): Likewise. (__arm_vcmpeqq_m_n_s8): Likewise. (__arm_vshlq_m_r_s8): Likewise. (__arm_vrshlq_m_n_s8): Likewise. (__arm_vrev64q_m_s8): Likewise. (__arm_vqshlq_m_r_s8): Likewise. (__arm_vqrshlq_m_n_s8): Likewise. (__arm_vqnegq_m_s8): Likewise. (__arm_vqabsq_m_s8): Likewise. (__arm_vnegq_m_s8): Likewise. (__arm_vmvnq_m_s8): Likewise. (__arm_vmlsdavxq_p_s8): Likewise. (__arm_vmlsdavq_p_s8): Likewise. (__arm_vmladavxq_p_s8): Likewise. (__arm_vmladavq_p_s8): Likewise. (__arm_vminvq_p_s8): Likewise. (__arm_vmaxvq_p_s8): Likewise. (__arm_vdupq_m_n_s8): Likewise. (__arm_vclzq_m_s8): Likewise. (__arm_vclsq_m_s8): Likewise. (__arm_vaddvaq_p_s8): Likewise. (__arm_vabsq_m_s8): Likewise. (__arm_vqrdmlsdhxq_s8): Likewise. (__arm_vqrdmlsdhq_s8): Likewise. (__arm_vqrdmlashq_n_s8): Likewise. (__arm_vqrdmlahq_n_s8): Likewise. (__arm_vqrdmladhxq_s8): Likewise. (__arm_vqrdmladhq_s8): Likewise. (__arm_vqdmlsdhxq_s8): Likewise. (__arm_vqdmlsdhq_s8): Likewise. (__arm_vqdmlahq_n_s8): Likewise. (__arm_vqdmladhxq_s8): Likewise. (__arm_vqdmladhq_s8): Likewise. (__arm_vmlsdavaxq_s8): Likewise. (__arm_vmlsdavaq_s8): Likewise. (__arm_vmlasq_n_s8): Likewise. (__arm_vmlaq_n_s8): Likewise. (__arm_vmladavaxq_s8): Likewise. (__arm_vmladavaq_s8): Likewise. (__arm_vsriq_n_s8): Likewise. (__arm_vsliq_n_s8): Likewise. (__arm_vpselq_u16): Likewise. (__arm_vpselq_s16): Likewise. (__arm_vrev64q_m_u16): Likewise. (__arm_vqrdmlashq_n_u16): Likewise. (__arm_vqrdmlahq_n_u16): Likewise. (__arm_vqdmlahq_n_u16): Likewise. (__arm_vmvnq_m_u16): Likewise. (__arm_vmlasq_n_u16): Likewise. (__arm_vmlaq_n_u16): Likewise. (__arm_vmladavq_p_u16): Likewise. (__arm_vmladavaq_u16): Likewise. (__arm_vminvq_p_u16): Likewise. (__arm_vmaxvq_p_u16): Likewise. (__arm_vdupq_m_n_u16): Likewise. (__arm_vcmpneq_m_u16): Likewise. (__arm_vcmpneq_m_n_u16): Likewise. (__arm_vcmphiq_m_u16): Likewise. (__arm_vcmphiq_m_n_u16): Likewise. (__arm_vcmpeqq_m_u16): Likewise. (__arm_vcmpeqq_m_n_u16): Likewise. (__arm_vcmpcsq_m_u16): Likewise. (__arm_vcmpcsq_m_n_u16): Likewise. (__arm_vclzq_m_u16): Likewise. (__arm_vaddvaq_p_u16): Likewise. (__arm_vsriq_n_u16): Likewise. (__arm_vsliq_n_u16): Likewise. (__arm_vshlq_m_r_u16): Likewise. (__arm_vrshlq_m_n_u16): Likewise. (__arm_vqshlq_m_r_u16): Likewise. (__arm_vqrshlq_m_n_u16): Likewise. (__arm_vminavq_p_s16): Likewise. (__arm_vminaq_m_s16): Likewise. (__arm_vmaxavq_p_s16): Likewise. (__arm_vmaxaq_m_s16): Likewise. (__arm_vcmpneq_m_s16): Likewise. (__arm_vcmpneq_m_n_s16): Likewise. (__arm_vcmpltq_m_s16): Likewise. (__arm_vcmpltq_m_n_s16): Likewise. (__arm_vcmpleq_m_s16): Likewise. (__arm_vcmpleq_m_n_s16): Likewise. (__arm_vcmpgtq_m_s16): Likewise. (__arm_vcmpgtq_m_n_s16): Likewise. (__arm_vcmpgeq_m_s16): Likewise. (__arm_vcmpgeq_m_n_s16): Likewise. (__arm_vcmpeqq_m_s16): Likewise. (__arm_vcmpeqq_m_n_s16): Likewise. (__arm_vshlq_m_r_s16): Likewise. (__arm_vrshlq_m_n_s16): Likewise. (__arm_vrev64q_m_s16): Likewise. (__arm_vqshlq_m_r_s16): Likewise. (__arm_vqrshlq_m_n_s16): Likewise. (__arm_vqnegq_m_s16): Likewise. (__arm_vqabsq_m_s16): Likewise. (__arm_vnegq_m_s16): Likewise. (__arm_vmvnq_m_s16): Likewise. (__arm_vmlsdavxq_p_s16): Likewise. (__arm_vmlsdavq_p_s16): Likewise. (__arm_vmladavxq_p_s16): Likewise. (__arm_vmladavq_p_s16): Likewise. (__arm_vminvq_p_s16): Likewise. (__arm_vmaxvq_p_s16): Likewise. (__arm_vdupq_m_n_s16): Likewise. (__arm_vclzq_m_s16): Likewise. (__arm_vclsq_m_s16): Likewise. (__arm_vaddvaq_p_s16): Likewise. (__arm_vabsq_m_s16): Likewise. (__arm_vqrdmlsdhxq_s16): Likewise. (__arm_vqrdmlsdhq_s16): Likewise. (__arm_vqrdmlashq_n_s16): Likewise. (__arm_vqrdmlahq_n_s16): Likewise. (__arm_vqrdmladhxq_s16): Likewise. (__arm_vqrdmladhq_s16): Likewise. (__arm_vqdmlsdhxq_s16): Likewise. (__arm_vqdmlsdhq_s16): Likewise. (__arm_vqdmlahq_n_s16): Likewise. (__arm_vqdmladhxq_s16): Likewise. (__arm_vqdmladhq_s16): Likewise. (__arm_vmlsdavaxq_s16): Likewise. (__arm_vmlsdavaq_s16): Likewise. (__arm_vmlasq_n_s16): Likewise. (__arm_vmlaq_n_s16): Likewise. (__arm_vmladavaxq_s16): Likewise. (__arm_vmladavaq_s16): Likewise. (__arm_vsriq_n_s16): Likewise. (__arm_vsliq_n_s16): Likewise. (__arm_vpselq_u32): Likewise. (__arm_vpselq_s32): Likewise. (__arm_vrev64q_m_u32): Likewise. (__arm_vqrdmlashq_n_u32): Likewise. (__arm_vqrdmlahq_n_u32): Likewise. (__arm_vqdmlahq_n_u32): Likewise. (__arm_vmvnq_m_u32): Likewise. (__arm_vmlasq_n_u32): Likewise. (__arm_vmlaq_n_u32): Likewise. (__arm_vmladavq_p_u32): Likewise. (__arm_vmladavaq_u32): Likewise. (__arm_vminvq_p_u32): Likewise. (__arm_vmaxvq_p_u32): Likewise. (__arm_vdupq_m_n_u32): Likewise. (__arm_vcmpneq_m_u32): Likewise. (__arm_vcmpneq_m_n_u32): Likewise. (__arm_vcmphiq_m_u32): Likewise. (__arm_vcmphiq_m_n_u32): Likewise. (__arm_vcmpeqq_m_u32): Likewise. (__arm_vcmpeqq_m_n_u32): Likewise. (__arm_vcmpcsq_m_u32): Likewise. (__arm_vcmpcsq_m_n_u32): Likewise. (__arm_vclzq_m_u32): Likewise. (__arm_vaddvaq_p_u32): Likewise. (__arm_vsriq_n_u32): Likewise. (__arm_vsliq_n_u32): Likewise. (__arm_vshlq_m_r_u32): Likewise. (__arm_vrshlq_m_n_u32): Likewise. (__arm_vqshlq_m_r_u32): Likewise. (__arm_vqrshlq_m_n_u32): Likewise. (__arm_vminavq_p_s32): Likewise. (__arm_vminaq_m_s32): Likewise. (__arm_vmaxavq_p_s32): Likewise. (__arm_vmaxaq_m_s32): Likewise. (__arm_vcmpneq_m_s32): Likewise. (__arm_vcmpneq_m_n_s32): Likewise. (__arm_vcmpltq_m_s32): Likewise. (__arm_vcmpltq_m_n_s32): Likewise. (__arm_vcmpleq_m_s32): Likewise. (__arm_vcmpleq_m_n_s32): Likewise. (__arm_vcmpgtq_m_s32): Likewise. (__arm_vcmpgtq_m_n_s32): Likewise. (__arm_vcmpgeq_m_s32): Likewise. (__arm_vcmpgeq_m_n_s32): Likewise. (__arm_vcmpeqq_m_s32): Likewise. (__arm_vcmpeqq_m_n_s32): Likewise. (__arm_vshlq_m_r_s32): Likewise. (__arm_vrshlq_m_n_s32): Likewise. (__arm_vrev64q_m_s32): Likewise. (__arm_vqshlq_m_r_s32): Likewise. (__arm_vqrshlq_m_n_s32): Likewise. (__arm_vqnegq_m_s32): Likewise. (__arm_vqabsq_m_s32): Likewise. (__arm_vnegq_m_s32): Likewise. (__arm_vmvnq_m_s32): Likewise. (__arm_vmlsdavxq_p_s32): Likewise. (__arm_vmlsdavq_p_s32): Likewise. (__arm_vmladavxq_p_s32): Likewise. (__arm_vmladavq_p_s32): Likewise. (__arm_vminvq_p_s32): Likewise. (__arm_vmaxvq_p_s32): Likewise. (__arm_vdupq_m_n_s32): Likewise. (__arm_vclzq_m_s32): Likewise. (__arm_vclsq_m_s32): Likewise. (__arm_vaddvaq_p_s32): Likewise. (__arm_vabsq_m_s32): Likewise. (__arm_vqrdmlsdhxq_s32): Likewise. (__arm_vqrdmlsdhq_s32): Likewise. (__arm_vqrdmlashq_n_s32): Likewise. (__arm_vqrdmlahq_n_s32): Likewise. (__arm_vqrdmladhxq_s32): Likewise. (__arm_vqrdmladhq_s32): Likewise. (__arm_vqdmlsdhxq_s32): Likewise. (__arm_vqdmlsdhq_s32): Likewise. (__arm_vqdmlahq_n_s32): Likewise. (__arm_vqdmladhxq_s32): Likewise. (__arm_vqdmladhq_s32): Likewise. (__arm_vmlsdavaxq_s32): Likewise. (__arm_vmlsdavaq_s32): Likewise. (__arm_vmlasq_n_s32): Likewise. (__arm_vmlaq_n_s32): Likewise. (__arm_vmladavaxq_s32): Likewise. (__arm_vmladavaq_s32): Likewise. (__arm_vsriq_n_s32): Likewise. (__arm_vsliq_n_s32): Likewise. (__arm_vpselq_u64): Likewise. (__arm_vpselq_s64): Likewise. (vcmpneq_m_n): Define polymorphic variant. (vcmpneq_m): Likewise. (vqrdmlsdhq): Likewise. (vqrdmlsdhxq): Likewise. (vqrshlq_m_n): Likewise. (vqshlq_m_r): Likewise. (vrev64q_m): Likewise. (vrshlq_m_n): Likewise. (vshlq_m_r): Likewise. (vsliq_n): Likewise. (vsriq_n): Likewise. (vqrdmlashq_n): Likewise. (vqrdmlahq): Likewise. (vqrdmladhxq): Likewise. (vqrdmladhq): Likewise. (vqnegq_m): Likewise. (vqdmlsdhxq): Likewise. (vabsq_m): Likewise. (vclsq_m): Likewise. (vclzq_m): Likewise. (vcmpgeq_m): Likewise. (vcmpgeq_m_n): Likewise. (vdupq_m_n): Likewise. (vmaxaq_m): Likewise. (vmlaq_n): Likewise. (vmlasq_n): Likewise. (vmvnq_m): Likewise. (vnegq_m): Likewise. (vpselq): Likewise. (vqdmlahq_n): Likewise. (vqrdmlahq_n): Likewise. (vqdmlsdhq): Likewise. (vqdmladhq): Likewise. (vqabsq_m): Likewise. (vminaq_m): Likewise. (vrmlaldavhaq): Likewise. (vmlsdavxq_p): Likewise. (vmlsdavq_p): Likewise. (vmlsdavaxq): Likewise. (vmlsdavaq): Likewise. (vaddvaq_p): Likewise. (vcmpcsq_m_n): Likewise. (vcmpcsq_m): Likewise. (vcmpeqq_m_n): Likewise. (vcmpeqq_m): Likewise. (vmladavxq_p): Likewise. (vmladavq_p): Likewise. (vmladavaxq): Likewise. (vmladavaq): Likewise. (vminvq_p): Likewise. (vminavq_p): Likewise. (vmaxvq_p): Likewise. (vmaxavq_p): Likewise. (vcmpltq_m_n): Likewise. (vcmpltq_m): Likewise. (vcmpleq_m): Likewise. (vcmpleq_m_n): Likewise. (vcmphiq_m_n): Likewise. (vcmphiq_m): Likewise. (vcmpgtq_m_n): Likewise. (vcmpgtq_m): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use builtin qualifier. (TERNOP_NONE_NONE_NONE_NONE): Likewise. (TERNOP_NONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise. (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise. * config/arm/constraints.md (Rc): Define constraint to check constant is in the range of 0 to 15. (Re): Define constraint to check constant is in the range of 0 to 31. * config/arm/mve.md (VADDVAQ_P): Define iterator. (VCLZQ_M): Likewise. (VCMPEQQ_M_N): Likewise. (VCMPEQQ_M): Likewise. (VCMPNEQ_M_N): Likewise. (VCMPNEQ_M): Likewise. (VDUPQ_M_N): Likewise. (VMAXVQ_P): Likewise. (VMINVQ_P): Likewise. (VMLADAVAQ): Likewise. (VMLADAVQ_P): Likewise. (VMLAQ_N): Likewise. (VMLASQ_N): Likewise. (VMVNQ_M): Likewise. (VPSELQ): Likewise. (VQDMLAHQ_N): Likewise. (VQRDMLAHQ_N): Likewise. (VQRDMLASHQ_N): Likewise. (VQRSHLQ_M_N): Likewise. (VQSHLQ_M_R): Likewise. (VREV64Q_M): Likewise. (VRSHLQ_M_N): Likewise. (VSHLQ_M_R): Likewise. (VSLIQ_N): Likewise. (VSRIQ_N): Likewise. (mve_vabsq_m_s): Define RTL pattern. (mve_vaddvaq_p_): Likewise. (mve_vclsq_m_s): Likewise. (mve_vclzq_m_): Likewise. (mve_vcmpcsq_m_n_u): Likewise. (mve_vcmpcsq_m_u): Likewise. (mve_vcmpeqq_m_n_): Likewise. (mve_vcmpeqq_m_): Likewise. (mve_vcmpgeq_m_n_s): Likewise. (mve_vcmpgeq_m_s): Likewise. (mve_vcmpgtq_m_n_s): Likewise. (mve_vcmpgtq_m_s): Likewise. (mve_vcmphiq_m_n_u): Likewise. (mve_vcmphiq_m_u): Likewise. (mve_vcmpleq_m_n_s): Likewise. (mve_vcmpleq_m_s): Likewise. (mve_vcmpltq_m_n_s): Likewise. (mve_vcmpltq_m_s): Likewise. (mve_vcmpneq_m_n_): Likewise. (mve_vcmpneq_m_): Likewise. (mve_vdupq_m_n_): Likewise. (mve_vmaxaq_m_s): Likewise. (mve_vmaxavq_p_s): Likewise. (mve_vmaxvq_p_): Likewise. (mve_vminaq_m_s): Likewise. (mve_vminavq_p_s): Likewise. (mve_vminvq_p_): Likewise. (mve_vmladavaq_): Likewise. (mve_vmladavq_p_): Likewise. (mve_vmladavxq_p_s): Likewise. (mve_vmlaq_n_): Likewise. (mve_vmlasq_n_): Likewise. (mve_vmlsdavq_p_s): Likewise. (mve_vmlsdavxq_p_s): Likewise. (mve_vmvnq_m_): Likewise. (mve_vnegq_m_s): Likewise. (mve_vpselq_): Likewise. (mve_vqabsq_m_s): Likewise. (mve_vqdmlahq_n_): Likewise. (mve_vqnegq_m_s): Likewise. (mve_vqrdmladhq_s): Likewise. (mve_vqrdmladhxq_s): Likewise. (mve_vqrdmlahq_n_): Likewise. (mve_vqrdmlashq_n_): Likewise. (mve_vqrdmlsdhq_s): Likewise. (mve_vqrdmlsdhxq_s): Likewise. (mve_vqrshlq_m_n_): Likewise. (mve_vqshlq_m_r_): Likewise. (mve_vrev64q_m_): Likewise. (mve_vrshlq_m_n_): Likewise. (mve_vshlq_m_r_): Likewise. (mve_vsliq_n_): Likewise. (mve_vsriq_n_): Likewise. (mve_vqdmlsdhxq_s): Likewise. (mve_vqdmlsdhq_s): Likewise. (mve_vqdmladhxq_s): Likewise. (mve_vqdmladhq_s): Likewise. (mve_vmlsdavaxq_s): Likewise. (mve_vmlsdavaq_s): Likewise. (mve_vmladavaxq_s): Likewise. * config/arm/predicates.md (mve_imm_15):Define predicate to check the matching constraint Rc. (mve_imm_31): Define predicate to check the matching constraint Re. 2020-03-18 Andrew Stubbs * config/gcn/gcn-valu.md (vec_cmpdi): Set operand 1 to DImode. (vec_cmpdi_dup): Likewise. * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1. 2020-03-18 Andrew Stubbs * config/gcn/gcn-valu.md (COND_MODE): Delete. (COND_INT_MODE): Delete. (cond_op): Add "mult". (cond_): Use VEC_ALLREG_MODE. (cond_): Use VEC_ALLREG_INT_MODE. 2020-03-18 Richard Biener PR middle-end/94206 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using partial int modes or not mode-precision integer types for the store. 2020-03-18 Jakub Jelinek * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue in a comment. * config/arc/arc.c (frame_stack_add): Likewise. * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term): Likewise. * ipa-predicate.c (predicate::remap_after_inlining): Likewise. * tree-ssa-strlen.h (handle_printf_call): Likewise. * tree-ssa-strlen.c (is_strlen_related_p): Likewise. * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise. 2020-03-18 Duan bo PR target/94201 * config/aarch64/aarch64.md (ldr_got_tiny): Delete. (@ldr_got_tiny_): New pattern. (ldr_got_tiny_sidi): Likewise. * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use them to handle SYMBOL_TINY_GOT for ILP32. 2020-03-18 Richard Sandiford * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as call-preserved for SVE PCS functions. (aarch64_layout_frame): Cope with up to 12 predicate save slots. Optimize the case in which there are no following vector save slots. 2020-03-18 Richard Biener PR middle-end/94188 * fold-const.c (build_fold_addr_expr): Convert address to correct type. * asan.c (maybe_create_ssa_name): Strip useless type conversions. * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1 to build the ADDR_EXPR which we don't really want to simplify. * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise. * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise. * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise. (simplify_builtin_call): Strip useless type conversions. * tree-ssa-strlen.c (new_strinfo): Likewise. 2020-03-17 Alexey Neyman PR debug/93751 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if the debug level is terse and the declaration is public. Do not generate type info. (dwarf2out_decl): Same. (add_type_attribute): Return immediately if debug level is terse. 2020-03-17 Richard Sandiford * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Define qualifier for ternary operands. (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vabavq_s8): Define macro. (vabavq_s16): Likewise. (vabavq_s32): Likewise. (vbicq_m_n_s16): Likewise. (vbicq_m_n_s32): Likewise. (vbicq_m_n_u16): Likewise. (vbicq_m_n_u32): Likewise. (vcmpeqq_m_f16): Likewise. (vcmpeqq_m_f32): Likewise. (vcvtaq_m_s16_f16): Likewise. (vcvtaq_m_u16_f16): Likewise. (vcvtaq_m_s32_f32): Likewise. (vcvtaq_m_u32_f32): Likewise. (vcvtq_m_f16_s16): Likewise. (vcvtq_m_f16_u16): Likewise. (vcvtq_m_f32_s32): Likewise. (vcvtq_m_f32_u32): Likewise. (vqrshrnbq_n_s16): Likewise. (vqrshrnbq_n_u16): Likewise. (vqrshrnbq_n_s32): Likewise. (vqrshrnbq_n_u32): Likewise. (vqrshrunbq_n_s16): Likewise. (vqrshrunbq_n_s32): Likewise. (vrmlaldavhaq_s32): Likewise. (vrmlaldavhaq_u32): Likewise. (vshlcq_s8): Likewise. (vshlcq_u8): Likewise. (vshlcq_s16): Likewise. (vshlcq_u16): Likewise. (vshlcq_s32): Likewise. (vshlcq_u32): Likewise. (vabavq_u8): Likewise. (vabavq_u16): Likewise. (vabavq_u32): Likewise. (__arm_vabavq_s8): Define intrinsic. (__arm_vabavq_s16): Likewise. (__arm_vabavq_s32): Likewise. (__arm_vabavq_u8): Likewise. (__arm_vabavq_u16): Likewise. (__arm_vabavq_u32): Likewise. (__arm_vbicq_m_n_s16): Likewise. (__arm_vbicq_m_n_s32): Likewise. (__arm_vbicq_m_n_u16): Likewise. (__arm_vbicq_m_n_u32): Likewise. (__arm_vqrshrnbq_n_s16): Likewise. (__arm_vqrshrnbq_n_u16): Likewise. (__arm_vqrshrnbq_n_s32): Likewise. (__arm_vqrshrnbq_n_u32): Likewise. (__arm_vqrshrunbq_n_s16): Likewise. (__arm_vqrshrunbq_n_s32): Likewise. (__arm_vrmlaldavhaq_s32): Likewise. (__arm_vrmlaldavhaq_u32): Likewise. (__arm_vshlcq_s8): Likewise. (__arm_vshlcq_u8): Likewise. (__arm_vshlcq_s16): Likewise. (__arm_vshlcq_u16): Likewise. (__arm_vshlcq_s32): Likewise. (__arm_vshlcq_u32): Likewise. (__arm_vcmpeqq_m_f16): Likewise. (__arm_vcmpeqq_m_f32): Likewise. (__arm_vcvtaq_m_s16_f16): Likewise. (__arm_vcvtaq_m_u16_f16): Likewise. (__arm_vcvtaq_m_s32_f32): Likewise. (__arm_vcvtaq_m_u32_f32): Likewise. (__arm_vcvtq_m_f16_s16): Likewise. (__arm_vcvtq_m_f16_u16): Likewise. (__arm_vcvtq_m_f32_s32): Likewise. (__arm_vcvtq_m_f32_u32): Likewise. (vcvtaq_m): Define polymorphic variant. (vcvtq_m): Likewise. (vabavq): Likewise. (vshlcq): Likewise. (vbicq_m_n): Likewise. (vqrshrnbq_n): Likewise. (vqrshrunbq_n): Likewise. * config/arm/arm_mve_builtins.def (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer. (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. * config/arm/mve.md (VBICQ_M_N): Define iterator. (VCVTAQ_M): Likewise. (VCVTQ_M_TO_F): Likewise. (VQRSHRNBQ_N): Likewise. (VABAVQ): Likewise. (VSHLCQ): Likewise. (VRMLALDAVHAQ): Likewise. (mve_vbicq_m_n_): Define RTL pattern. (mve_vcmpeqq_m_f): Likewise. (mve_vcvtaq_m_): Likewise. (mve_vcvtq_m_to_f_): Likewise. (mve_vqrshrnbq_n_): Likewise. (mve_vqrshrunbq_n_s): Likewise. (mve_vrmlaldavhaq_v4si): Likewise. (mve_vabavq_): Likewise. (mve_vshlcq_): Likewise. (mve_vshlcq_): Likewise. (mve_vshlcq_vec_): Define RTL expand. (mve_vshlcq_carry_): Likewise. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vqmovntq_u16): Define macro. (vqmovnbq_u16): Likewise. (vmulltq_poly_p8): Likewise. (vmullbq_poly_p8): Likewise. (vmovntq_u16): Likewise. (vmovnbq_u16): Likewise. (vmlaldavxq_u16): Likewise. (vmlaldavq_u16): Likewise. (vqmovuntq_s16): Likewise. (vqmovunbq_s16): Likewise. (vshlltq_n_u8): Likewise. (vshllbq_n_u8): Likewise. (vorrq_n_u16): Likewise. (vbicq_n_u16): Likewise. (vcmpneq_n_f16): Likewise. (vcmpneq_f16): Likewise. (vcmpltq_n_f16): Likewise. (vcmpltq_f16): Likewise. (vcmpleq_n_f16): Likewise. (vcmpleq_f16): Likewise. (vcmpgtq_n_f16): Likewise. (vcmpgtq_f16): Likewise. (vcmpgeq_n_f16): Likewise. (vcmpgeq_f16): Likewise. (vcmpeqq_n_f16): Likewise. (vcmpeqq_f16): Likewise. (vsubq_f16): Likewise. (vqmovntq_s16): Likewise. (vqmovnbq_s16): Likewise. (vqdmulltq_s16): Likewise. (vqdmulltq_n_s16): Likewise. (vqdmullbq_s16): Likewise. (vqdmullbq_n_s16): Likewise. (vorrq_f16): Likewise. (vornq_f16): Likewise. (vmulq_n_f16): Likewise. (vmulq_f16): Likewise. (vmovntq_s16): Likewise. (vmovnbq_s16): Likewise. (vmlsldavxq_s16): Likewise. (vmlsldavq_s16): Likewise. (vmlaldavxq_s16): Likewise. (vmlaldavq_s16): Likewise. (vminnmvq_f16): Likewise. (vminnmq_f16): Likewise. (vminnmavq_f16): Likewise. (vminnmaq_f16): Likewise. (vmaxnmvq_f16): Likewise. (vmaxnmq_f16): Likewise. (vmaxnmavq_f16): Likewise. (vmaxnmaq_f16): Likewise. (veorq_f16): Likewise. (vcmulq_rot90_f16): Likewise. (vcmulq_rot270_f16): Likewise. (vcmulq_rot180_f16): Likewise. (vcmulq_f16): Likewise. (vcaddq_rot90_f16): Likewise. (vcaddq_rot270_f16): Likewise. (vbicq_f16): Likewise. (vandq_f16): Likewise. (vaddq_n_f16): Likewise. (vabdq_f16): Likewise. (vshlltq_n_s8): Likewise. (vshllbq_n_s8): Likewise. (vorrq_n_s16): Likewise. (vbicq_n_s16): Likewise. (vqmovntq_u32): Likewise. (vqmovnbq_u32): Likewise. (vmulltq_poly_p16): Likewise. (vmullbq_poly_p16): Likewise. (vmovntq_u32): Likewise. (vmovnbq_u32): Likewise. (vmlaldavxq_u32): Likewise. (vmlaldavq_u32): Likewise. (vqmovuntq_s32): Likewise. (vqmovunbq_s32): Likewise. (vshlltq_n_u16): Likewise. (vshllbq_n_u16): Likewise. (vorrq_n_u32): Likewise. (vbicq_n_u32): Likewise. (vcmpneq_n_f32): Likewise. (vcmpneq_f32): Likewise. (vcmpltq_n_f32): Likewise. (vcmpltq_f32): Likewise. (vcmpleq_n_f32): Likewise. (vcmpleq_f32): Likewise. (vcmpgtq_n_f32): Likewise. (vcmpgtq_f32): Likewise. (vcmpgeq_n_f32): Likewise. (vcmpgeq_f32): Likewise. (vcmpeqq_n_f32): Likewise. (vcmpeqq_f32): Likewise. (vsubq_f32): Likewise. (vqmovntq_s32): Likewise. (vqmovnbq_s32): Likewise. (vqdmulltq_s32): Likewise. (vqdmulltq_n_s32): Likewise. (vqdmullbq_s32): Likewise. (vqdmullbq_n_s32): Likewise. (vorrq_f32): Likewise. (vornq_f32): Likewise. (vmulq_n_f32): Likewise. (vmulq_f32): Likewise. (vmovntq_s32): Likewise. (vmovnbq_s32): Likewise. (vmlsldavxq_s32): Likewise. (vmlsldavq_s32): Likewise. (vmlaldavxq_s32): Likewise. (vmlaldavq_s32): Likewise. (vminnmvq_f32): Likewise. (vminnmq_f32): Likewise. (vminnmavq_f32): Likewise. (vminnmaq_f32): Likewise. (vmaxnmvq_f32): Likewise. (vmaxnmq_f32): Likewise. (vmaxnmavq_f32): Likewise. (vmaxnmaq_f32): Likewise. (veorq_f32): Likewise. (vcmulq_rot90_f32): Likewise. (vcmulq_rot270_f32): Likewise. (vcmulq_rot180_f32): Likewise. (vcmulq_f32): Likewise. (vcaddq_rot90_f32): Likewise. (vcaddq_rot270_f32): Likewise. (vbicq_f32): Likewise. (vandq_f32): Likewise. (vaddq_n_f32): Likewise. (vabdq_f32): Likewise. (vshlltq_n_s16): Likewise. (vshllbq_n_s16): Likewise. (vorrq_n_s32): Likewise. (vbicq_n_s32): Likewise. (vrmlaldavhq_u32): Likewise. (vctp8q_m): Likewise. (vctp64q_m): Likewise. (vctp32q_m): Likewise. (vctp16q_m): Likewise. (vaddlvaq_u32): Likewise. (vrmlsldavhxq_s32): Likewise. (vrmlsldavhq_s32): Likewise. (vrmlaldavhxq_s32): Likewise. (vrmlaldavhq_s32): Likewise. (vcvttq_f16_f32): Likewise. (vcvtbq_f16_f32): Likewise. (vaddlvaq_s32): Likewise. (__arm_vqmovntq_u16): Define intrinsic. (__arm_vqmovnbq_u16): Likewise. (__arm_vmulltq_poly_p8): Likewise. (__arm_vmullbq_poly_p8): Likewise. (__arm_vmovntq_u16): Likewise. (__arm_vmovnbq_u16): Likewise. (__arm_vmlaldavxq_u16): Likewise. (__arm_vmlaldavq_u16): Likewise. (__arm_vqmovuntq_s16): Likewise. (__arm_vqmovunbq_s16): Likewise. (__arm_vshlltq_n_u8): Likewise. (__arm_vshllbq_n_u8): Likewise. (__arm_vorrq_n_u16): Likewise. (__arm_vbicq_n_u16): Likewise. (__arm_vcmpneq_n_f16): Likewise. (__arm_vcmpneq_f16): Likewise. (__arm_vcmpltq_n_f16): Likewise. (__arm_vcmpltq_f16): Likewise. (__arm_vcmpleq_n_f16): Likewise. (__arm_vcmpleq_f16): Likewise. (__arm_vcmpgtq_n_f16): Likewise. (__arm_vcmpgtq_f16): Likewise. (__arm_vcmpgeq_n_f16): Likewise. (__arm_vcmpgeq_f16): Likewise. (__arm_vcmpeqq_n_f16): Likewise. (__arm_vcmpeqq_f16): Likewise. (__arm_vsubq_f16): Likewise. (__arm_vqmovntq_s16): Likewise. (__arm_vqmovnbq_s16): Likewise. (__arm_vqdmulltq_s16): Likewise. (__arm_vqdmulltq_n_s16): Likewise. (__arm_vqdmullbq_s16): Likewise. (__arm_vqdmullbq_n_s16): Likewise. (__arm_vorrq_f16): Likewise. (__arm_vornq_f16): Likewise. (__arm_vmulq_n_f16): Likewise. (__arm_vmulq_f16): Likewise. (__arm_vmovntq_s16): Likewise. (__arm_vmovnbq_s16): Likewise. (__arm_vmlsldavxq_s16): Likewise. (__arm_vmlsldavq_s16): Likewise. (__arm_vmlaldavxq_s16): Likewise. (__arm_vmlaldavq_s16): Likewise. (__arm_vminnmvq_f16): Likewise. (__arm_vminnmq_f16): Likewise. (__arm_vminnmavq_f16): Likewise. (__arm_vminnmaq_f16): Likewise. (__arm_vmaxnmvq_f16): Likewise. (__arm_vmaxnmq_f16): Likewise. (__arm_vmaxnmavq_f16): Likewise. (__arm_vmaxnmaq_f16): Likewise. (__arm_veorq_f16): Likewise. (__arm_vcmulq_rot90_f16): Likewise. (__arm_vcmulq_rot270_f16): Likewise. (__arm_vcmulq_rot180_f16): Likewise. (__arm_vcmulq_f16): Likewise. (__arm_vcaddq_rot90_f16): Likewise. (__arm_vcaddq_rot270_f16): Likewise. (__arm_vbicq_f16): Likewise. (__arm_vandq_f16): Likewise. (__arm_vaddq_n_f16): Likewise. (__arm_vabdq_f16): Likewise. (__arm_vshlltq_n_s8): Likewise. (__arm_vshllbq_n_s8): Likewise. (__arm_vorrq_n_s16): Likewise. (__arm_vbicq_n_s16): Likewise. (__arm_vqmovntq_u32): Likewise. (__arm_vqmovnbq_u32): Likewise. (__arm_vmulltq_poly_p16): Likewise. (__arm_vmullbq_poly_p16): Likewise. (__arm_vmovntq_u32): Likewise. (__arm_vmovnbq_u32): Likewise. (__arm_vmlaldavxq_u32): Likewise. (__arm_vmlaldavq_u32): Likewise. (__arm_vqmovuntq_s32): Likewise. (__arm_vqmovunbq_s32): Likewise. (__arm_vshlltq_n_u16): Likewise. (__arm_vshllbq_n_u16): Likewise. (__arm_vorrq_n_u32): Likewise. (__arm_vbicq_n_u32): Likewise. (__arm_vcmpneq_n_f32): Likewise. (__arm_vcmpneq_f32): Likewise. (__arm_vcmpltq_n_f32): Likewise. (__arm_vcmpltq_f32): Likewise. (__arm_vcmpleq_n_f32): Likewise. (__arm_vcmpleq_f32): Likewise. (__arm_vcmpgtq_n_f32): Likewise. (__arm_vcmpgtq_f32): Likewise. (__arm_vcmpgeq_n_f32): Likewise. (__arm_vcmpgeq_f32): Likewise. (__arm_vcmpeqq_n_f32): Likewise. (__arm_vcmpeqq_f32): Likewise. (__arm_vsubq_f32): Likewise. (__arm_vqmovntq_s32): Likewise. (__arm_vqmovnbq_s32): Likewise. (__arm_vqdmulltq_s32): Likewise. (__arm_vqdmulltq_n_s32): Likewise. (__arm_vqdmullbq_s32): Likewise. (__arm_vqdmullbq_n_s32): Likewise. (__arm_vorrq_f32): Likewise. (__arm_vornq_f32): Likewise. (__arm_vmulq_n_f32): Likewise. (__arm_vmulq_f32): Likewise. (__arm_vmovntq_s32): Likewise. (__arm_vmovnbq_s32): Likewise. (__arm_vmlsldavxq_s32): Likewise. (__arm_vmlsldavq_s32): Likewise. (__arm_vmlaldavxq_s32): Likewise. (__arm_vmlaldavq_s32): Likewise. (__arm_vminnmvq_f32): Likewise. (__arm_vminnmq_f32): Likewise. (__arm_vminnmavq_f32): Likewise. (__arm_vminnmaq_f32): Likewise. (__arm_vmaxnmvq_f32): Likewise. (__arm_vmaxnmq_f32): Likewise. (__arm_vmaxnmavq_f32): Likewise. (__arm_vmaxnmaq_f32): Likewise. (__arm_veorq_f32): Likewise. (__arm_vcmulq_rot90_f32): Likewise. (__arm_vcmulq_rot270_f32): Likewise. (__arm_vcmulq_rot180_f32): Likewise. (__arm_vcmulq_f32): Likewise. (__arm_vcaddq_rot90_f32): Likewise. (__arm_vcaddq_rot270_f32): Likewise. (__arm_vbicq_f32): Likewise. (__arm_vandq_f32): Likewise. (__arm_vaddq_n_f32): Likewise. (__arm_vabdq_f32): Likewise. (__arm_vshlltq_n_s16): Likewise. (__arm_vshllbq_n_s16): Likewise. (__arm_vorrq_n_s32): Likewise. (__arm_vbicq_n_s32): Likewise. (__arm_vrmlaldavhq_u32): Likewise. (__arm_vctp8q_m): Likewise. (__arm_vctp64q_m): Likewise. (__arm_vctp32q_m): Likewise. (__arm_vctp16q_m): Likewise. (__arm_vaddlvaq_u32): Likewise. (__arm_vrmlsldavhxq_s32): Likewise. (__arm_vrmlsldavhq_s32): Likewise. (__arm_vrmlaldavhxq_s32): Likewise. (__arm_vrmlaldavhq_s32): Likewise. (__arm_vcvttq_f16_f32): Likewise. (__arm_vcvtbq_f16_f32): Likewise. (__arm_vaddlvaq_s32): Likewise. (vst4q): Define polymorphic variant. (vrndxq): Likewise. (vrndq): Likewise. (vrndpq): Likewise. (vrndnq): Likewise. (vrndmq): Likewise. (vrndaq): Likewise. (vrev64q): Likewise. (vnegq): Likewise. (vdupq_n): Likewise. (vabsq): Likewise. (vrev32q): Likewise. (vcvtbq_f32): Likewise. (vcvttq_f32): Likewise. (vcvtq): Likewise. (vsubq_n): Likewise. (vbrsrq_n): Likewise. (vcvtq_n): Likewise. (vsubq): Likewise. (vorrq): Likewise. (vabdq): Likewise. (vaddq_n): Likewise. (vandq): Likewise. (vbicq): Likewise. (vornq): Likewise. (vmulq_n): Likewise. (vmulq): Likewise. (vcaddq_rot270): Likewise. (vcmpeqq_n): Likewise. (vcmpeqq): Likewise. (vcaddq_rot90): Likewise. (vcmpgeq_n): Likewise. (vcmpgeq): Likewise. (vcmpgtq_n): Likewise. (vcmpgtq): Likewise. (vcmpgtq): Likewise. (vcmpleq_n): Likewise. (vcmpleq_n): Likewise. (vcmpleq): Likewise. (vcmpleq): Likewise. (vcmpltq_n): Likewise. (vcmpltq_n): Likewise. (vcmpltq): Likewise. (vcmpltq): Likewise. (vcmpneq_n): Likewise. (vcmpneq_n): Likewise. (vcmpneq): Likewise. (vcmpneq): Likewise. (vcmulq): Likewise. (vcmulq): Likewise. (vcmulq_rot180): Likewise. (vcmulq_rot180): Likewise. (vcmulq_rot270): Likewise. (vcmulq_rot270): Likewise. (vcmulq_rot90): Likewise. (vcmulq_rot90): Likewise. (veorq): Likewise. (veorq): Likewise. (vmaxnmaq): Likewise. (vmaxnmaq): Likewise. (vmaxnmavq): Likewise. (vmaxnmavq): Likewise. (vmaxnmq): Likewise. (vmaxnmq): Likewise. (vmaxnmvq): Likewise. (vmaxnmvq): Likewise. (vminnmaq): Likewise. (vminnmaq): Likewise. (vminnmavq): Likewise. (vminnmavq): Likewise. (vminnmq): Likewise. (vminnmq): Likewise. (vminnmvq): Likewise. (vminnmvq): Likewise. (vbicq_n): Likewise. (vqmovntq): Likewise. (vqmovntq): Likewise. (vqmovnbq): Likewise. (vqmovnbq): Likewise. (vmulltq_poly): Likewise. (vmulltq_poly): Likewise. (vmullbq_poly): Likewise. (vmullbq_poly): Likewise. (vmovntq): Likewise. (vmovntq): Likewise. (vmovnbq): Likewise. (vmovnbq): Likewise. (vmlaldavxq): Likewise. (vmlaldavxq): Likewise. (vqmovuntq): Likewise. (vqmovuntq): Likewise. (vshlltq_n): Likewise. (vshlltq_n): Likewise. (vshllbq_n): Likewise. (vshllbq_n): Likewise. (vorrq_n): Likewise. (vorrq_n): Likewise. (vmlaldavq): Likewise. (vmlaldavq): Likewise. (vqmovunbq): Likewise. (vqmovunbq): Likewise. (vqdmulltq_n): Likewise. (vqdmulltq_n): Likewise. (vqdmulltq): Likewise. (vqdmulltq): Likewise. (vqdmullbq_n): Likewise. (vqdmullbq_n): Likewise. (vqdmullbq): Likewise. (vqdmullbq): Likewise. (vaddlvaq): Likewise. (vaddlvaq): Likewise. (vrmlaldavhq): Likewise. (vrmlaldavhq): Likewise. (vrmlaldavhxq): Likewise. (vrmlaldavhxq): Likewise. (vrmlsldavhq): Likewise. (vrmlsldavhq): Likewise. (vrmlsldavhxq): Likewise. (vrmlsldavhxq): Likewise. (vmlsldavxq): Likewise. (vmlsldavxq): Likewise. (vmlsldavq): Likewise. (vmlsldavq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. (BINOP_NONE_NONE_NONE): Likewise. (BINOP_UNONE_NONE_NONE): Likewise. (BINOP_UNONE_UNONE_IMM): Likewise. (BINOP_UNONE_UNONE_NONE): Likewise. (BINOP_UNONE_UNONE_UNONE): Likewise. * config/arm/mve.md (mve_vabdq_f): Define RTL pattern. (mve_vaddlvaq_v4si): Likewise. (mve_vaddq_n_f): Likewise. (mve_vandq_f): Likewise. (mve_vbicq_f): Likewise. (mve_vbicq_n_): Likewise. (mve_vcaddq_rot270_f): Likewise. (mve_vcaddq_rot90_f): Likewise. (mve_vcmpeqq_f): Likewise. (mve_vcmpeqq_n_f): Likewise. (mve_vcmpgeq_f): Likewise. (mve_vcmpgeq_n_f): Likewise. (mve_vcmpgtq_f): Likewise. (mve_vcmpgtq_n_f): Likewise. (mve_vcmpleq_f): Likewise. (mve_vcmpleq_n_f): Likewise. (mve_vcmpltq_f): Likewise. (mve_vcmpltq_n_f): Likewise. (mve_vcmpneq_f): Likewise. (mve_vcmpneq_n_f): Likewise. (mve_vcmulq_f): Likewise. (mve_vcmulq_rot180_f): Likewise. (mve_vcmulq_rot270_f): Likewise. (mve_vcmulq_rot90_f): Likewise. (mve_vctpq_mhi): Likewise. (mve_vcvtbq_f16_f32v8hf): Likewise. (mve_vcvttq_f16_f32v8hf): Likewise. (mve_veorq_f): Likewise. (mve_vmaxnmaq_f): Likewise. (mve_vmaxnmavq_f): Likewise. (mve_vmaxnmq_f): Likewise. (mve_vmaxnmvq_f): Likewise. (mve_vminnmaq_f): Likewise. (mve_vminnmavq_f): Likewise. (mve_vminnmq_f): Likewise. (mve_vminnmvq_f): Likewise. (mve_vmlaldavq_): Likewise. (mve_vmlaldavxq_): Likewise. (mve_vmlsldavq_s): Likewise. (mve_vmlsldavxq_s): Likewise. (mve_vmovnbq_): Likewise. (mve_vmovntq_): Likewise. (mve_vmulq_f): Likewise. (mve_vmulq_n_f): Likewise. (mve_vornq_f): Likewise. (mve_vorrq_f): Likewise. (mve_vorrq_n_): Likewise. (mve_vqdmullbq_n_s): Likewise. (mve_vqdmullbq_s): Likewise. (mve_vqdmulltq_n_s): Likewise. (mve_vqdmulltq_s): Likewise. (mve_vqmovnbq_): Likewise. (mve_vqmovntq_): Likewise. (mve_vqmovunbq_s): Likewise. (mve_vqmovuntq_s): Likewise. (mve_vrmlaldavhxq_sv4si): Likewise. (mve_vrmlsldavhq_sv4si): Likewise. (mve_vrmlsldavhxq_sv4si): Likewise. (mve_vshllbq_n_): Likewise. (mve_vshlltq_n_): Likewise. (mve_vsubq_f): Likewise. (mve_vmulltq_poly_p): Likewise. (mve_vmullbq_poly_p): Likewise. (mve_vrmlaldavhq_v4si): Likewise. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vsubq_u8): Define macro. (vsubq_n_u8): Likewise. (vrmulhq_u8): Likewise. (vrhaddq_u8): Likewise. (vqsubq_u8): Likewise. (vqsubq_n_u8): Likewise. (vqaddq_u8): Likewise. (vqaddq_n_u8): Likewise. (vorrq_u8): Likewise. (vornq_u8): Likewise. (vmulq_u8): Likewise. (vmulq_n_u8): Likewise. (vmulltq_int_u8): Likewise. (vmullbq_int_u8): Likewise. (vmulhq_u8): Likewise. (vmladavq_u8): Likewise. (vminvq_u8): Likewise. (vminq_u8): Likewise. (vmaxvq_u8): Likewise. (vmaxq_u8): Likewise. (vhsubq_u8): Likewise. (vhsubq_n_u8): Likewise. (vhaddq_u8): Likewise. (vhaddq_n_u8): Likewise. (veorq_u8): Likewise. (vcmpneq_n_u8): Likewise. (vcmphiq_u8): Likewise. (vcmphiq_n_u8): Likewise. (vcmpeqq_u8): Likewise. (vcmpeqq_n_u8): Likewise. (vcmpcsq_u8): Likewise. (vcmpcsq_n_u8): Likewise. (vcaddq_rot90_u8): Likewise. (vcaddq_rot270_u8): Likewise. (vbicq_u8): Likewise. (vandq_u8): Likewise. (vaddvq_p_u8): Likewise. (vaddvaq_u8): Likewise. (vaddq_n_u8): Likewise. (vabdq_u8): Likewise. (vshlq_r_u8): Likewise. (vrshlq_u8): Likewise. (vrshlq_n_u8): Likewise. (vqshlq_u8): Likewise. (vqshlq_r_u8): Likewise. (vqrshlq_u8): Likewise. (vqrshlq_n_u8): Likewise. (vminavq_s8): Likewise. (vminaq_s8): Likewise. (vmaxavq_s8): Likewise. (vmaxaq_s8): Likewise. (vbrsrq_n_u8): Likewise. (vshlq_n_u8): Likewise. (vrshrq_n_u8): Likewise. (vqshlq_n_u8): Likewise. (vcmpneq_n_s8): Likewise. (vcmpltq_s8): Likewise. (vcmpltq_n_s8): Likewise. (vcmpleq_s8): Likewise. (vcmpleq_n_s8): Likewise. (vcmpgtq_s8): Likewise. (vcmpgtq_n_s8): Likewise. (vcmpgeq_s8): Likewise. (vcmpgeq_n_s8): Likewise. (vcmpeqq_s8): Likewise. (vcmpeqq_n_s8): Likewise. (vqshluq_n_s8): Likewise. (vaddvq_p_s8): Likewise. (vsubq_s8): Likewise. (vsubq_n_s8): Likewise. (vshlq_r_s8): Likewise. (vrshlq_s8): Likewise. (vrshlq_n_s8): Likewise. (vrmulhq_s8): Likewise. (vrhaddq_s8): Likewise. (vqsubq_s8): Likewise. (vqsubq_n_s8): Likewise. (vqshlq_s8): Likewise. (vqshlq_r_s8): Likewise. (vqrshlq_s8): Likewise. (vqrshlq_n_s8): Likewise. (vqrdmulhq_s8): Likewise. (vqrdmulhq_n_s8): Likewise. (vqdmulhq_s8): Likewise. (vqdmulhq_n_s8): Likewise. (vqaddq_s8): Likewise. (vqaddq_n_s8): Likewise. (vorrq_s8): Likewise. (vornq_s8): Likewise. (vmulq_s8): Likewise. (vmulq_n_s8): Likewise. (vmulltq_int_s8): Likewise. (vmullbq_int_s8): Likewise. (vmulhq_s8): Likewise. (vmlsdavxq_s8): Likewise. (vmlsdavq_s8): Likewise. (vmladavxq_s8): Likewise. (vmladavq_s8): Likewise. (vminvq_s8): Likewise. (vminq_s8): Likewise. (vmaxvq_s8): Likewise. (vmaxq_s8): Likewise. (vhsubq_s8): Likewise. (vhsubq_n_s8): Likewise. (vhcaddq_rot90_s8): Likewise. (vhcaddq_rot270_s8): Likewise. (vhaddq_s8): Likewise. (vhaddq_n_s8): Likewise. (veorq_s8): Likewise. (vcaddq_rot90_s8): Likewise. (vcaddq_rot270_s8): Likewise. (vbrsrq_n_s8): Likewise. (vbicq_s8): Likewise. (vandq_s8): Likewise. (vaddvaq_s8): Likewise. (vaddq_n_s8): Likewise. (vabdq_s8): Likewise. (vshlq_n_s8): Likewise. (vrshrq_n_s8): Likewise. (vqshlq_n_s8): Likewise. (vsubq_u16): Likewise. (vsubq_n_u16): Likewise. (vrmulhq_u16): Likewise. (vrhaddq_u16): Likewise. (vqsubq_u16): Likewise. (vqsubq_n_u16): Likewise. (vqaddq_u16): Likewise. (vqaddq_n_u16): Likewise. (vorrq_u16): Likewise. (vornq_u16): Likewise. (vmulq_u16): Likewise. (vmulq_n_u16): Likewise. (vmulltq_int_u16): Likewise. (vmullbq_int_u16): Likewise. (vmulhq_u16): Likewise. (vmladavq_u16): Likewise. (vminvq_u16): Likewise. (vminq_u16): Likewise. (vmaxvq_u16): Likewise. (vmaxq_u16): Likewise. (vhsubq_u16): Likewise. (vhsubq_n_u16): Likewise. (vhaddq_u16): Likewise. (vhaddq_n_u16): Likewise. (veorq_u16): Likewise. (vcmpneq_n_u16): Likewise. (vcmphiq_u16): Likewise. (vcmphiq_n_u16): Likewise. (vcmpeqq_u16): Likewise. (vcmpeqq_n_u16): Likewise. (vcmpcsq_u16): Likewise. (vcmpcsq_n_u16): Likewise. (vcaddq_rot90_u16): Likewise. (vcaddq_rot270_u16): Likewise. (vbicq_u16): Likewise. (vandq_u16): Likewise. (vaddvq_p_u16): Likewise. (vaddvaq_u16): Likewise. (vaddq_n_u16): Likewise. (vabdq_u16): Likewise. (vshlq_r_u16): Likewise. (vrshlq_u16): Likewise. (vrshlq_n_u16): Likewise. (vqshlq_u16): Likewise. (vqshlq_r_u16): Likewise. (vqrshlq_u16): Likewise. (vqrshlq_n_u16): Likewise. (vminavq_s16): Likewise. (vminaq_s16): Likewise. (vmaxavq_s16): Likewise. (vmaxaq_s16): Likewise. (vbrsrq_n_u16): Likewise. (vshlq_n_u16): Likewise. (vrshrq_n_u16): Likewise. (vqshlq_n_u16): Likewise. (vcmpneq_n_s16): Likewise. (vcmpltq_s16): Likewise. (vcmpltq_n_s16): Likewise. (vcmpleq_s16): Likewise. (vcmpleq_n_s16): Likewise. (vcmpgtq_s16): Likewise. (vcmpgtq_n_s16): Likewise. (vcmpgeq_s16): Likewise. (vcmpgeq_n_s16): Likewise. (vcmpeqq_s16): Likewise. (vcmpeqq_n_s16): Likewise. (vqshluq_n_s16): Likewise. (vaddvq_p_s16): Likewise. (vsubq_s16): Likewise. (vsubq_n_s16): Likewise. (vshlq_r_s16): Likewise. (vrshlq_s16): Likewise. (vrshlq_n_s16): Likewise. (vrmulhq_s16): Likewise. (vrhaddq_s16): Likewise. (vqsubq_s16): Likewise. (vqsubq_n_s16): Likewise. (vqshlq_s16): Likewise. (vqshlq_r_s16): Likewise. (vqrshlq_s16): Likewise. (vqrshlq_n_s16): Likewise. (vqrdmulhq_s16): Likewise. (vqrdmulhq_n_s16): Likewise. (vqdmulhq_s16): Likewise. (vqdmulhq_n_s16): Likewise. (vqaddq_s16): Likewise. (vqaddq_n_s16): Likewise. (vorrq_s16): Likewise. (vornq_s16): Likewise. (vmulq_s16): Likewise. (vmulq_n_s16): Likewise. (vmulltq_int_s16): Likewise. (vmullbq_int_s16): Likewise. (vmulhq_s16): Likewise. (vmlsdavxq_s16): Likewise. (vmlsdavq_s16): Likewise. (vmladavxq_s16): Likewise. (vmladavq_s16): Likewise. (vminvq_s16): Likewise. (vminq_s16): Likewise. (vmaxvq_s16): Likewise. (vmaxq_s16): Likewise. (vhsubq_s16): Likewise. (vhsubq_n_s16): Likewise. (vhcaddq_rot90_s16): Likewise. (vhcaddq_rot270_s16): Likewise. (vhaddq_s16): Likewise. (vhaddq_n_s16): Likewise. (veorq_s16): Likewise. (vcaddq_rot90_s16): Likewise. (vcaddq_rot270_s16): Likewise. (vbrsrq_n_s16): Likewise. (vbicq_s16): Likewise. (vandq_s16): Likewise. (vaddvaq_s16): Likewise. (vaddq_n_s16): Likewise. (vabdq_s16): Likewise. (vshlq_n_s16): Likewise. (vrshrq_n_s16): Likewise. (vqshlq_n_s16): Likewise. (vsubq_u32): Likewise. (vsubq_n_u32): Likewise. (vrmulhq_u32): Likewise. (vrhaddq_u32): Likewise. (vqsubq_u32): Likewise. (vqsubq_n_u32): Likewise. (vqaddq_u32): Likewise. (vqaddq_n_u32): Likewise. (vorrq_u32): Likewise. (vornq_u32): Likewise. (vmulq_u32): Likewise. (vmulq_n_u32): Likewise. (vmulltq_int_u32): Likewise. (vmullbq_int_u32): Likewise. (vmulhq_u32): Likewise. (vmladavq_u32): Likewise. (vminvq_u32): Likewise. (vminq_u32): Likewise. (vmaxvq_u32): Likewise. (vmaxq_u32): Likewise. (vhsubq_u32): Likewise. (vhsubq_n_u32): Likewise. (vhaddq_u32): Likewise. (vhaddq_n_u32): Likewise. (veorq_u32): Likewise. (vcmpneq_n_u32): Likewise. (vcmphiq_u32): Likewise. (vcmphiq_n_u32): Likewise. (vcmpeqq_u32): Likewise. (vcmpeqq_n_u32): Likewise. (vcmpcsq_u32): Likewise. (vcmpcsq_n_u32): Likewise. (vcaddq_rot90_u32): Likewise. (vcaddq_rot270_u32): Likewise. (vbicq_u32): Likewise. (vandq_u32): Likewise. (vaddvq_p_u32): Likewise. (vaddvaq_u32): Likewise. (vaddq_n_u32): Likewise. (vabdq_u32): Likewise. (vshlq_r_u32): Likewise. (vrshlq_u32): Likewise. (vrshlq_n_u32): Likewise. (vqshlq_u32): Likewise. (vqshlq_r_u32): Likewise. (vqrshlq_u32): Likewise. (vqrshlq_n_u32): Likewise. (vminavq_s32): Likewise. (vminaq_s32): Likewise. (vmaxavq_s32): Likewise. (vmaxaq_s32): Likewise. (vbrsrq_n_u32): Likewise. (vshlq_n_u32): Likewise. (vrshrq_n_u32): Likewise. (vqshlq_n_u32): Likewise. (vcmpneq_n_s32): Likewise. (vcmpltq_s32): Likewise. (vcmpltq_n_s32): Likewise. (vcmpleq_s32): Likewise. (vcmpleq_n_s32): Likewise. (vcmpgtq_s32): Likewise. (vcmpgtq_n_s32): Likewise. (vcmpgeq_s32): Likewise. (vcmpgeq_n_s32): Likewise. (vcmpeqq_s32): Likewise. (vcmpeqq_n_s32): Likewise. (vqshluq_n_s32): Likewise. (vaddvq_p_s32): Likewise. (vsubq_s32): Likewise. (vsubq_n_s32): Likewise. (vshlq_r_s32): Likewise. (vrshlq_s32): Likewise. (vrshlq_n_s32): Likewise. (vrmulhq_s32): Likewise. (vrhaddq_s32): Likewise. (vqsubq_s32): Likewise. (vqsubq_n_s32): Likewise. (vqshlq_s32): Likewise. (vqshlq_r_s32): Likewise. (vqrshlq_s32): Likewise. (vqrshlq_n_s32): Likewise. (vqrdmulhq_s32): Likewise. (vqrdmulhq_n_s32): Likewise. (vqdmulhq_s32): Likewise. (vqdmulhq_n_s32): Likewise. (vqaddq_s32): Likewise. (vqaddq_n_s32): Likewise. (vorrq_s32): Likewise. (vornq_s32): Likewise. (vmulq_s32): Likewise. (vmulq_n_s32): Likewise. (vmulltq_int_s32): Likewise. (vmullbq_int_s32): Likewise. (vmulhq_s32): Likewise. (vmlsdavxq_s32): Likewise. (vmlsdavq_s32): Likewise. (vmladavxq_s32): Likewise. (vmladavq_s32): Likewise. (vminvq_s32): Likewise. (vminq_s32): Likewise. (vmaxvq_s32): Likewise. (vmaxq_s32): Likewise. (vhsubq_s32): Likewise. (vhsubq_n_s32): Likewise. (vhcaddq_rot90_s32): Likewise. (vhcaddq_rot270_s32): Likewise. (vhaddq_s32): Likewise. (vhaddq_n_s32): Likewise. (veorq_s32): Likewise. (vcaddq_rot90_s32): Likewise. (vcaddq_rot270_s32): Likewise. (vbrsrq_n_s32): Likewise. (vbicq_s32): Likewise. (vandq_s32): Likewise. (vaddvaq_s32): Likewise. (vaddq_n_s32): Likewise. (vabdq_s32): Likewise. (vshlq_n_s32): Likewise. (vrshrq_n_s32): Likewise. (vqshlq_n_s32): Likewise. (__arm_vsubq_u8): Define intrinsic. (__arm_vsubq_n_u8): Likewise. (__arm_vrmulhq_u8): Likewise. (__arm_vrhaddq_u8): Likewise. (__arm_vqsubq_u8): Likewise. (__arm_vqsubq_n_u8): Likewise. (__arm_vqaddq_u8): Likewise. (__arm_vqaddq_n_u8): Likewise. (__arm_vorrq_u8): Likewise. (__arm_vornq_u8): Likewise. (__arm_vmulq_u8): Likewise. (__arm_vmulq_n_u8): Likewise. (__arm_vmulltq_int_u8): Likewise. (__arm_vmullbq_int_u8): Likewise. (__arm_vmulhq_u8): Likewise. (__arm_vmladavq_u8): Likewise. (__arm_vminvq_u8): Likewise. (__arm_vminq_u8): Likewise. (__arm_vmaxvq_u8): Likewise. (__arm_vmaxq_u8): Likewise. (__arm_vhsubq_u8): Likewise. (__arm_vhsubq_n_u8): Likewise. (__arm_vhaddq_u8): Likewise. (__arm_vhaddq_n_u8): Likewise. (__arm_veorq_u8): Likewise. (__arm_vcmpneq_n_u8): Likewise. (__arm_vcmphiq_u8): Likewise. (__arm_vcmphiq_n_u8): Likewise. (__arm_vcmpeqq_u8): Likewise. (__arm_vcmpeqq_n_u8): Likewise. (__arm_vcmpcsq_u8): Likewise. (__arm_vcmpcsq_n_u8): Likewise. (__arm_vcaddq_rot90_u8): Likewise. (__arm_vcaddq_rot270_u8): Likewise. (__arm_vbicq_u8): Likewise. (__arm_vandq_u8): Likewise. (__arm_vaddvq_p_u8): Likewise. (__arm_vaddvaq_u8): Likewise. (__arm_vaddq_n_u8): Likewise. (__arm_vabdq_u8): Likewise. (__arm_vshlq_r_u8): Likewise. (__arm_vrshlq_u8): Likewise. (__arm_vrshlq_n_u8): Likewise. (__arm_vqshlq_u8): Likewise. (__arm_vqshlq_r_u8): Likewise. (__arm_vqrshlq_u8): Likewise. (__arm_vqrshlq_n_u8): Likewise. (__arm_vminavq_s8): Likewise. (__arm_vminaq_s8): Likewise. (__arm_vmaxavq_s8): Likewise. (__arm_vmaxaq_s8): Likewise. (__arm_vbrsrq_n_u8): Likewise. (__arm_vshlq_n_u8): Likewise. (__arm_vrshrq_n_u8): Likewise. (__arm_vqshlq_n_u8): Likewise. (__arm_vcmpneq_n_s8): Likewise. (__arm_vcmpltq_s8): Likewise. (__arm_vcmpltq_n_s8): Likewise. (__arm_vcmpleq_s8): Likewise. (__arm_vcmpleq_n_s8): Likewise. (__arm_vcmpgtq_s8): Likewise. (__arm_vcmpgtq_n_s8): Likewise. (__arm_vcmpgeq_s8): Likewise. (__arm_vcmpgeq_n_s8): Likewise. (__arm_vcmpeqq_s8): Likewise. (__arm_vcmpeqq_n_s8): Likewise. (__arm_vqshluq_n_s8): Likewise. (__arm_vaddvq_p_s8): Likewise. (__arm_vsubq_s8): Likewise. (__arm_vsubq_n_s8): Likewise. (__arm_vshlq_r_s8): Likewise. (__arm_vrshlq_s8): Likewise. (__arm_vrshlq_n_s8): Likewise. (__arm_vrmulhq_s8): Likewise. (__arm_vrhaddq_s8): Likewise. (__arm_vqsubq_s8): Likewise. (__arm_vqsubq_n_s8): Likewise. (__arm_vqshlq_s8): Likewise. (__arm_vqshlq_r_s8): Likewise. (__arm_vqrshlq_s8): Likewise. (__arm_vqrshlq_n_s8): Likewise. (__arm_vqrdmulhq_s8): Likewise. (__arm_vqrdmulhq_n_s8): Likewise. (__arm_vqdmulhq_s8): Likewise. (__arm_vqdmulhq_n_s8): Likewise. (__arm_vqaddq_s8): Likewise. (__arm_vqaddq_n_s8): Likewise. (__arm_vorrq_s8): Likewise. (__arm_vornq_s8): Likewise. (__arm_vmulq_s8): Likewise. (__arm_vmulq_n_s8): Likewise. (__arm_vmulltq_int_s8): Likewise. (__arm_vmullbq_int_s8): Likewise. (__arm_vmulhq_s8): Likewise. (__arm_vmlsdavxq_s8): Likewise. (__arm_vmlsdavq_s8): Likewise. (__arm_vmladavxq_s8): Likewise. (__arm_vmladavq_s8): Likewise. (__arm_vminvq_s8): Likewise. (__arm_vminq_s8): Likewise. (__arm_vmaxvq_s8): Likewise. (__arm_vmaxq_s8): Likewise. (__arm_vhsubq_s8): Likewise. (__arm_vhsubq_n_s8): Likewise. (__arm_vhcaddq_rot90_s8): Likewise. (__arm_vhcaddq_rot270_s8): Likewise. (__arm_vhaddq_s8): Likewise. (__arm_vhaddq_n_s8): Likewise. (__arm_veorq_s8): Likewise. (__arm_vcaddq_rot90_s8): Likewise. (__arm_vcaddq_rot270_s8): Likewise. (__arm_vbrsrq_n_s8): Likewise. (__arm_vbicq_s8): Likewise. (__arm_vandq_s8): Likewise. (__arm_vaddvaq_s8): Likewise. (__arm_vaddq_n_s8): Likewise. (__arm_vabdq_s8): Likewise. (__arm_vshlq_n_s8): Likewise. (__arm_vrshrq_n_s8): Likewise. (__arm_vqshlq_n_s8): Likewise. (__arm_vsubq_u16): Likewise. (__arm_vsubq_n_u16): Likewise. (__arm_vrmulhq_u16): Likewise. (__arm_vrhaddq_u16): Likewise. (__arm_vqsubq_u16): Likewise. (__arm_vqsubq_n_u16): Likewise. (__arm_vqaddq_u16): Likewise. (__arm_vqaddq_n_u16): Likewise. (__arm_vorrq_u16): Likewise. (__arm_vornq_u16): Likewise. (__arm_vmulq_u16): Likewise. (__arm_vmulq_n_u16): Likewise. (__arm_vmulltq_int_u16): Likewise. (__arm_vmullbq_int_u16): Likewise. (__arm_vmulhq_u16): Likewise. (__arm_vmladavq_u16): Likewise. (__arm_vminvq_u16): Likewise. (__arm_vminq_u16): Likewise. (__arm_vmaxvq_u16): Likewise. (__arm_vmaxq_u16): Likewise. (__arm_vhsubq_u16): Likewise. (__arm_vhsubq_n_u16): Likewise. (__arm_vhaddq_u16): Likewise. (__arm_vhaddq_n_u16): Likewise. (__arm_veorq_u16): Likewise. (__arm_vcmpneq_n_u16): Likewise. (__arm_vcmphiq_u16): Likewise. (__arm_vcmphiq_n_u16): Likewise. (__arm_vcmpeqq_u16): Likewise. (__arm_vcmpeqq_n_u16): Likewise. (__arm_vcmpcsq_u16): Likewise. (__arm_vcmpcsq_n_u16): Likewise. (__arm_vcaddq_rot90_u16): Likewise. (__arm_vcaddq_rot270_u16): Likewise. (__arm_vbicq_u16): Likewise. (__arm_vandq_u16): Likewise. (__arm_vaddvq_p_u16): Likewise. (__arm_vaddvaq_u16): Likewise. (__arm_vaddq_n_u16): Likewise. (__arm_vabdq_u16): Likewise. (__arm_vshlq_r_u16): Likewise. (__arm_vrshlq_u16): Likewise. (__arm_vrshlq_n_u16): Likewise. (__arm_vqshlq_u16): Likewise. (__arm_vqshlq_r_u16): Likewise. (__arm_vqrshlq_u16): Likewise. (__arm_vqrshlq_n_u16): Likewise. (__arm_vminavq_s16): Likewise. (__arm_vminaq_s16): Likewise. (__arm_vmaxavq_s16): Likewise. (__arm_vmaxaq_s16): Likewise. (__arm_vbrsrq_n_u16): Likewise. (__arm_vshlq_n_u16): Likewise. (__arm_vrshrq_n_u16): Likewise. (__arm_vqshlq_n_u16): Likewise. (__arm_vcmpneq_n_s16): Likewise. (__arm_vcmpltq_s16): Likewise. (__arm_vcmpltq_n_s16): Likewise. (__arm_vcmpleq_s16): Likewise. (__arm_vcmpleq_n_s16): Likewise. (__arm_vcmpgtq_s16): Likewise. (__arm_vcmpgtq_n_s16): Likewise. (__arm_vcmpgeq_s16): Likewise. (__arm_vcmpgeq_n_s16): Likewise. (__arm_vcmpeqq_s16): Likewise. (__arm_vcmpeqq_n_s16): Likewise. (__arm_vqshluq_n_s16): Likewise. (__arm_vaddvq_p_s16): Likewise. (__arm_vsubq_s16): Likewise. (__arm_vsubq_n_s16): Likewise. (__arm_vshlq_r_s16): Likewise. (__arm_vrshlq_s16): Likewise. (__arm_vrshlq_n_s16): Likewise. (__arm_vrmulhq_s16): Likewise. (__arm_vrhaddq_s16): Likewise. (__arm_vqsubq_s16): Likewise. (__arm_vqsubq_n_s16): Likewise. (__arm_vqshlq_s16): Likewise. (__arm_vqshlq_r_s16): Likewise. (__arm_vqrshlq_s16): Likewise. (__arm_vqrshlq_n_s16): Likewise. (__arm_vqrdmulhq_s16): Likewise. (__arm_vqrdmulhq_n_s16): Likewise. (__arm_vqdmulhq_s16): Likewise. (__arm_vqdmulhq_n_s16): Likewise. (__arm_vqaddq_s16): Likewise. (__arm_vqaddq_n_s16): Likewise. (__arm_vorrq_s16): Likewise. (__arm_vornq_s16): Likewise. (__arm_vmulq_s16): Likewise. (__arm_vmulq_n_s16): Likewise. (__arm_vmulltq_int_s16): Likewise. (__arm_vmullbq_int_s16): Likewise. (__arm_vmulhq_s16): Likewise. (__arm_vmlsdavxq_s16): Likewise. (__arm_vmlsdavq_s16): Likewise. (__arm_vmladavxq_s16): Likewise. (__arm_vmladavq_s16): Likewise. (__arm_vminvq_s16): Likewise. (__arm_vminq_s16): Likewise. (__arm_vmaxvq_s16): Likewise. (__arm_vmaxq_s16): Likewise. (__arm_vhsubq_s16): Likewise. (__arm_vhsubq_n_s16): Likewise. (__arm_vhcaddq_rot90_s16): Likewise. (__arm_vhcaddq_rot270_s16): Likewise. (__arm_vhaddq_s16): Likewise. (__arm_vhaddq_n_s16): Likewise. (__arm_veorq_s16): Likewise. (__arm_vcaddq_rot90_s16): Likewise. (__arm_vcaddq_rot270_s16): Likewise. (__arm_vbrsrq_n_s16): Likewise. (__arm_vbicq_s16): Likewise. (__arm_vandq_s16): Likewise. (__arm_vaddvaq_s16): Likewise. (__arm_vaddq_n_s16): Likewise. (__arm_vabdq_s16): Likewise. (__arm_vshlq_n_s16): Likewise. (__arm_vrshrq_n_s16): Likewise. (__arm_vqshlq_n_s16): Likewise. (__arm_vsubq_u32): Likewise. (__arm_vsubq_n_u32): Likewise. (__arm_vrmulhq_u32): Likewise. (__arm_vrhaddq_u32): Likewise. (__arm_vqsubq_u32): Likewise. (__arm_vqsubq_n_u32): Likewise. (__arm_vqaddq_u32): Likewise. (__arm_vqaddq_n_u32): Likewise. (__arm_vorrq_u32): Likewise. (__arm_vornq_u32): Likewise. (__arm_vmulq_u32): Likewise. (__arm_vmulq_n_u32): Likewise. (__arm_vmulltq_int_u32): Likewise. (__arm_vmullbq_int_u32): Likewise. (__arm_vmulhq_u32): Likewise. (__arm_vmladavq_u32): Likewise. (__arm_vminvq_u32): Likewise. (__arm_vminq_u32): Likewise. (__arm_vmaxvq_u32): Likewise. (__arm_vmaxq_u32): Likewise. (__arm_vhsubq_u32): Likewise. (__arm_vhsubq_n_u32): Likewise. (__arm_vhaddq_u32): Likewise. (__arm_vhaddq_n_u32): Likewise. (__arm_veorq_u32): Likewise. (__arm_vcmpneq_n_u32): Likewise. (__arm_vcmphiq_u32): Likewise. (__arm_vcmphiq_n_u32): Likewise. (__arm_vcmpeqq_u32): Likewise. (__arm_vcmpeqq_n_u32): Likewise. (__arm_vcmpcsq_u32): Likewise. (__arm_vcmpcsq_n_u32): Likewise. (__arm_vcaddq_rot90_u32): Likewise. (__arm_vcaddq_rot270_u32): Likewise. (__arm_vbicq_u32): Likewise. (__arm_vandq_u32): Likewise. (__arm_vaddvq_p_u32): Likewise. (__arm_vaddvaq_u32): Likewise. (__arm_vaddq_n_u32): Likewise. (__arm_vabdq_u32): Likewise. (__arm_vshlq_r_u32): Likewise. (__arm_vrshlq_u32): Likewise. (__arm_vrshlq_n_u32): Likewise. (__arm_vqshlq_u32): Likewise. (__arm_vqshlq_r_u32): Likewise. (__arm_vqrshlq_u32): Likewise. (__arm_vqrshlq_n_u32): Likewise. (__arm_vminavq_s32): Likewise. (__arm_vminaq_s32): Likewise. (__arm_vmaxavq_s32): Likewise. (__arm_vmaxaq_s32): Likewise. (__arm_vbrsrq_n_u32): Likewise. (__arm_vshlq_n_u32): Likewise. (__arm_vrshrq_n_u32): Likewise. (__arm_vqshlq_n_u32): Likewise. (__arm_vcmpneq_n_s32): Likewise. (__arm_vcmpltq_s32): Likewise. (__arm_vcmpltq_n_s32): Likewise. (__arm_vcmpleq_s32): Likewise. (__arm_vcmpleq_n_s32): Likewise. (__arm_vcmpgtq_s32): Likewise. (__arm_vcmpgtq_n_s32): Likewise. (__arm_vcmpgeq_s32): Likewise. (__arm_vcmpgeq_n_s32): Likewise. (__arm_vcmpeqq_s32): Likewise. (__arm_vcmpeqq_n_s32): Likewise. (__arm_vqshluq_n_s32): Likewise. (__arm_vaddvq_p_s32): Likewise. (__arm_vsubq_s32): Likewise. (__arm_vsubq_n_s32): Likewise. (__arm_vshlq_r_s32): Likewise. (__arm_vrshlq_s32): Likewise. (__arm_vrshlq_n_s32): Likewise. (__arm_vrmulhq_s32): Likewise. (__arm_vrhaddq_s32): Likewise. (__arm_vqsubq_s32): Likewise. (__arm_vqsubq_n_s32): Likewise. (__arm_vqshlq_s32): Likewise. (__arm_vqshlq_r_s32): Likewise. (__arm_vqrshlq_s32): Likewise. (__arm_vqrshlq_n_s32): Likewise. (__arm_vqrdmulhq_s32): Likewise. (__arm_vqrdmulhq_n_s32): Likewise. (__arm_vqdmulhq_s32): Likewise. (__arm_vqdmulhq_n_s32): Likewise. (__arm_vqaddq_s32): Likewise. (__arm_vqaddq_n_s32): Likewise. (__arm_vorrq_s32): Likewise. (__arm_vornq_s32): Likewise. (__arm_vmulq_s32): Likewise. (__arm_vmulq_n_s32): Likewise. (__arm_vmulltq_int_s32): Likewise. (__arm_vmullbq_int_s32): Likewise. (__arm_vmulhq_s32): Likewise. (__arm_vmlsdavxq_s32): Likewise. (__arm_vmlsdavq_s32): Likewise. (__arm_vmladavxq_s32): Likewise. (__arm_vmladavq_s32): Likewise. (__arm_vminvq_s32): Likewise. (__arm_vminq_s32): Likewise. (__arm_vmaxvq_s32): Likewise. (__arm_vmaxq_s32): Likewise. (__arm_vhsubq_s32): Likewise. (__arm_vhsubq_n_s32): Likewise. (__arm_vhcaddq_rot90_s32): Likewise. (__arm_vhcaddq_rot270_s32): Likewise. (__arm_vhaddq_s32): Likewise. (__arm_vhaddq_n_s32): Likewise. (__arm_veorq_s32): Likewise. (__arm_vcaddq_rot90_s32): Likewise. (__arm_vcaddq_rot270_s32): Likewise. (__arm_vbrsrq_n_s32): Likewise. (__arm_vbicq_s32): Likewise. (__arm_vandq_s32): Likewise. (__arm_vaddvaq_s32): Likewise. (__arm_vaddq_n_s32): Likewise. (__arm_vabdq_s32): Likewise. (__arm_vshlq_n_s32): Likewise. (__arm_vrshrq_n_s32): Likewise. (__arm_vqshlq_n_s32): Likewise. (vsubq): Define polymorphic variant. (vsubq_n): Likewise. (vshlq_r): Likewise. (vrshlq_n): Likewise. (vrshlq): Likewise. (vrmulhq): Likewise. (vrhaddq): Likewise. (vqsubq_n): Likewise. (vqsubq): Likewise. (vqshlq): Likewise. (vqshlq_r): Likewise. (vqshluq): Likewise. (vrshrq_n): Likewise. (vshlq_n): Likewise. (vqshluq_n): Likewise. (vqshlq_n): Likewise. (vqrshlq_n): Likewise. (vqrshlq): Likewise. (vqrdmulhq_n): Likewise. (vqrdmulhq): Likewise. (vqdmulhq_n): Likewise. (vqdmulhq): Likewise. (vqaddq_n): Likewise. (vqaddq): Likewise. (vorrq_n): Likewise. (vorrq): Likewise. (vornq): Likewise. (vmulq_n): Likewise. (vmulq): Likewise. (vmulltq_int): Likewise. (vmullbq_int): Likewise. (vmulhq): Likewise. (vminq): Likewise. (vminaq): Likewise. (vmaxq): Likewise. (vmaxaq): Likewise. (vhsubq_n): Likewise. (vhsubq): Likewise. (vhcaddq_rot90): Likewise. (vhcaddq_rot270): Likewise. (vhaddq_n): Likewise. (vhaddq): Likewise. (veorq): Likewise. (vcaddq_rot90): Likewise. (vcaddq_rot270): Likewise. (vbrsrq_n): Likewise. (vbicq_n): Likewise. (vbicq): Likewise. (vaddq): Likewise. (vaddq_n): Likewise. (vandq): Likewise. (vabdq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it. (BINOP_NONE_NONE_NONE): Likewise. (BINOP_NONE_NONE_UNONE): Likewise. (BINOP_UNONE_NONE_IMM): Likewise. (BINOP_UNONE_NONE_NONE): Likewise. (BINOP_UNONE_UNONE_IMM): Likewise. (BINOP_UNONE_UNONE_NONE): Likewise. (BINOP_UNONE_UNONE_UNONE): Likewise. * config/arm/constraints.md (Ra): Define constraint to check constant is in the range of 0 to 7. (Rg): Define constriant to check the constant is one among 1, 2, 4 and 8. * config/arm/mve.md (mve_vabdq_): Define RTL pattern. (mve_vaddq_n_): Likewise. (mve_vaddvaq_): Likewise. (mve_vaddvq_p_): Likewise. (mve_vandq_): Likewise. (mve_vbicq_): Likewise. (mve_vbrsrq_n_): Likewise. (mve_vcaddq_rot270_): Likewise. (mve_vcaddq_rot90_): Likewise. (mve_vcmpcsq_n_u): Likewise. (mve_vcmpcsq_u): Likewise. (mve_vcmpeqq_n_): Likewise. (mve_vcmpeqq_): Likewise. (mve_vcmpgeq_n_s): Likewise. (mve_vcmpgeq_s): Likewise. (mve_vcmpgtq_n_s): Likewise. (mve_vcmpgtq_s): Likewise. (mve_vcmphiq_n_u): Likewise. (mve_vcmphiq_u): Likewise. (mve_vcmpleq_n_s): Likewise. (mve_vcmpleq_s): Likewise. (mve_vcmpltq_n_s): Likewise. (mve_vcmpltq_s): Likewise. (mve_vcmpneq_n_): Likewise. (mve_vddupq_n_u): Likewise. (mve_veorq_): Likewise. (mve_vhaddq_n_): Likewise. (mve_vhaddq_): Likewise. (mve_vhcaddq_rot270_s): Likewise. (mve_vhcaddq_rot90_s): Likewise. (mve_vhsubq_n_): Likewise. (mve_vhsubq_): Likewise. (mve_vidupq_n_u): Likewise. (mve_vmaxaq_s): Likewise. (mve_vmaxavq_s): Likewise. (mve_vmaxq_): Likewise. (mve_vmaxvq_): Likewise. (mve_vminaq_s): Likewise. (mve_vminavq_s): Likewise. (mve_vminq_): Likewise. (mve_vminvq_): Likewise. (mve_vmladavq_): Likewise. (mve_vmladavxq_s): Likewise. (mve_vmlsdavq_s): Likewise. (mve_vmlsdavxq_s): Likewise. (mve_vmulhq_): Likewise. (mve_vmullbq_int_): Likewise. (mve_vmulltq_int_): Likewise. (mve_vmulq_n_): Likewise. (mve_vmulq_): Likewise. (mve_vornq_): Likewise. (mve_vorrq_): Likewise. (mve_vqaddq_n_): Likewise. (mve_vqaddq_): Likewise. (mve_vqdmulhq_n_s): Likewise. (mve_vqdmulhq_s): Likewise. (mve_vqrdmulhq_n_s): Likewise. (mve_vqrdmulhq_s): Likewise. (mve_vqrshlq_n_): Likewise. (mve_vqrshlq_): Likewise. (mve_vqshlq_n_): Likewise. (mve_vqshlq_r_): Likewise. (mve_vqshlq_): Likewise. (mve_vqshluq_n_s): Likewise. (mve_vqsubq_n_): Likewise. (mve_vqsubq_): Likewise. (mve_vrhaddq_): Likewise. (mve_vrmulhq_): Likewise. (mve_vrshlq_n_): Likewise. (mve_vrshlq_): Likewise. (mve_vrshrq_n_): Likewise. (mve_vshlq_n_): Likewise. (mve_vshlq_r_): Likewise. (mve_vsubq_n_): Likewise. (mve_vsubq_): Likewise. * config/arm/predicates.md (mve_imm_7): Define predicate to check the matching constraint Ra. (mve_imm_selective_upto_8): Define predicate to check the matching constraint Rg. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define qualifier for binary operands. (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro. (vaddlvq_p_u32): Likewise. (vcmpneq_s8): Likewise. (vcmpneq_s16): Likewise. (vcmpneq_s32): Likewise. (vcmpneq_u8): Likewise. (vcmpneq_u16): Likewise. (vcmpneq_u32): Likewise. (vshlq_s8): Likewise. (vshlq_s16): Likewise. (vshlq_s32): Likewise. (vshlq_u8): Likewise. (vshlq_u16): Likewise. (vshlq_u32): Likewise. (__arm_vaddlvq_p_s32): Define intrinsic. (__arm_vaddlvq_p_u32): Likewise. (__arm_vcmpneq_s8): Likewise. (__arm_vcmpneq_s16): Likewise. (__arm_vcmpneq_s32): Likewise. (__arm_vcmpneq_u8): Likewise. (__arm_vcmpneq_u16): Likewise. (__arm_vcmpneq_u32): Likewise. (__arm_vshlq_s8): Likewise. (__arm_vshlq_s16): Likewise. (__arm_vshlq_s32): Likewise. (__arm_vshlq_u8): Likewise. (__arm_vshlq_u16): Likewise. (__arm_vshlq_u32): Likewise. (vaddlvq_p): Define polymorphic variant. (vcmpneq): Likewise. (vshlq): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS): Use it. (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise. (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise. * config/arm/mve.md (mve_vaddlvq_p_v4si): Define RTL pattern. (mve_vcmpneq_): Likewise. (mve_vshlq_): Likewise. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define qualifier for binary operands. (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro. (vcvtq_n_s32_f32): Likewise. (vcvtq_n_u16_f16): Likewise. (vcvtq_n_u32_f32): Likewise. (vcreateq_u8): Likewise. (vcreateq_u16): Likewise. (vcreateq_u32): Likewise. (vcreateq_u64): Likewise. (vcreateq_s8): Likewise. (vcreateq_s16): Likewise. (vcreateq_s32): Likewise. (vcreateq_s64): Likewise. (vshrq_n_s8): Likewise. (vshrq_n_s16): Likewise. (vshrq_n_s32): Likewise. (vshrq_n_u8): Likewise. (vshrq_n_u16): Likewise. (vshrq_n_u32): Likewise. (__arm_vcreateq_u8): Define intrinsic. (__arm_vcreateq_u16): Likewise. (__arm_vcreateq_u32): Likewise. (__arm_vcreateq_u64): Likewise. (__arm_vcreateq_s8): Likewise. (__arm_vcreateq_s16): Likewise. (__arm_vcreateq_s32): Likewise. (__arm_vcreateq_s64): Likewise. (__arm_vshrq_n_s8): Likewise. (__arm_vshrq_n_s16): Likewise. (__arm_vshrq_n_s32): Likewise. (__arm_vshrq_n_u8): Likewise. (__arm_vshrq_n_u16): Likewise. (__arm_vshrq_n_u32): Likewise. (__arm_vcvtq_n_s16_f16): Likewise. (__arm_vcvtq_n_s32_f32): Likewise. (__arm_vcvtq_n_u16_f16): Likewise. (__arm_vcvtq_n_u32_f32): Likewise. (vshrq_n): Define polymorphic variant. * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Use it. (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise. * config/arm/constraints.md (Rb): Define constraint to check constant is in the range of 1 to 8. (Rf): Define constraint to check constant is in the range of 1 to 32. * config/arm/mve.md (mve_vcreateq_): Define RTL pattern. (mve_vshrq_n_): Likewise. (mve_vcvtq_n_from_f_): Likewise. * config/arm/predicates.md (mve_imm_8): Define predicate to check the matching constraint Rb. (mve_imm_32): Define predicate to check the matching constraint Rf. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define qualifier for binary operands. (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vsubq_n_f16): Define macro. (vsubq_n_f32): Likewise. (vbrsrq_n_f16): Likewise. (vbrsrq_n_f32): Likewise. (vcvtq_n_f16_s16): Likewise. (vcvtq_n_f32_s32): Likewise. (vcvtq_n_f16_u16): Likewise. (vcvtq_n_f32_u32): Likewise. (vcreateq_f16): Likewise. (vcreateq_f32): Likewise. (__arm_vsubq_n_f16): Define intrinsic. (__arm_vsubq_n_f32): Likewise. (__arm_vbrsrq_n_f16): Likewise. (__arm_vbrsrq_n_f32): Likewise. (__arm_vcvtq_n_f16_s16): Likewise. (__arm_vcvtq_n_f32_s32): Likewise. (__arm_vcvtq_n_f16_u16): Likewise. (__arm_vcvtq_n_f32_u32): Likewise. (__arm_vcreateq_f16): Likewise. (__arm_vcreateq_f32): Likewise. (vsubq): Define polymorphic variant. (vbrsrq): Likewise. (vcvtq_n): Likewise. * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use it. (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise. (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise. * config/arm/constraints.md (Rd): Define constraint to check constant is in the range of 1 to 16. * config/arm/mve.md (mve_vsubq_n_f): Define RTL pattern. mve_vbrsrq_n_f: Likewise. mve_vcvtq_n_to_f_: Likewise. mve_vcreateq_f: Likewise. * config/arm/predicates.md (mve_imm_16): Define predicate to check the matching constraint Rd. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (hi_UP): Define mode. * config/arm/arm.h (IS_VPR_REGNUM): Move. * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. (APSRQ_REGNUM): Modify. (APSRGE_REGNUM): Modify. * config/arm/arm_mve.h (vctp16q): Define macro. (vctp32q): Likewise. (vctp64q): Likewise. (vctp8q): Likewise. (vpnot): Likewise. (__arm_vctp16q): Define intrinsic. (__arm_vctp32q): Likewise. (__arm_vctp64q): Likewise. (__arm_vctp8q): Likewise. (__arm_vpnot): Likewise. * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin qualifier. * config/arm/mve.md (mve_vctpqhi): Define RTL pattern. (mve_vpnothi): Likewise. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. * config/arm/arm_mve.h (vdupq_n_s8): Define macro. (vdupq_n_s16): Likewise. (vdupq_n_s32): Likewise. (vabsq_s8): Likewise. (vabsq_s16): Likewise. (vabsq_s32): Likewise. (vclsq_s8): Likewise. (vclsq_s16): Likewise. (vclsq_s32): Likewise. (vclzq_s8): Likewise. (vclzq_s16): Likewise. (vclzq_s32): Likewise. (vnegq_s8): Likewise. (vnegq_s16): Likewise. (vnegq_s32): Likewise. (vaddlvq_s32): Likewise. (vaddvq_s8): Likewise. (vaddvq_s16): Likewise. (vaddvq_s32): Likewise. (vmovlbq_s8): Likewise. (vmovlbq_s16): Likewise. (vmovltq_s8): Likewise. (vmovltq_s16): Likewise. (vmvnq_s8): Likewise. (vmvnq_s16): Likewise. (vmvnq_s32): Likewise. (vrev16q_s8): Likewise. (vrev32q_s8): Likewise. (vrev32q_s16): Likewise. (vqabsq_s8): Likewise. (vqabsq_s16): Likewise. (vqabsq_s32): Likewise. (vqnegq_s8): Likewise. (vqnegq_s16): Likewise. (vqnegq_s32): Likewise. (vcvtaq_s16_f16): Likewise. (vcvtaq_s32_f32): Likewise. (vcvtnq_s16_f16): Likewise. (vcvtnq_s32_f32): Likewise. (vcvtpq_s16_f16): Likewise. (vcvtpq_s32_f32): Likewise. (vcvtmq_s16_f16): Likewise. (vcvtmq_s32_f32): Likewise. (vmvnq_u8): Likewise. (vmvnq_u16): Likewise. (vmvnq_u32): Likewise. (vdupq_n_u8): Likewise. (vdupq_n_u16): Likewise. (vdupq_n_u32): Likewise. (vclzq_u8): Likewise. (vclzq_u16): Likewise. (vclzq_u32): Likewise. (vaddvq_u8): Likewise. (vaddvq_u16): Likewise. (vaddvq_u32): Likewise. (vrev32q_u8): Likewise. (vrev32q_u16): Likewise. (vmovltq_u8): Likewise. (vmovltq_u16): Likewise. (vmovlbq_u8): Likewise. (vmovlbq_u16): Likewise. (vrev16q_u8): Likewise. (vaddlvq_u32): Likewise. (vcvtpq_u16_f16): Likewise. (vcvtpq_u32_f32): Likewise. (vcvtnq_u16_f16): Likewise. (vcvtmq_u16_f16): Likewise. (vcvtmq_u32_f32): Likewise. (vcvtaq_u16_f16): Likewise. (vcvtaq_u32_f32): Likewise. (__arm_vdupq_n_s8): Define intrinsic. (__arm_vdupq_n_s16): Likewise. (__arm_vdupq_n_s32): Likewise. (__arm_vabsq_s8): Likewise. (__arm_vabsq_s16): Likewise. (__arm_vabsq_s32): Likewise. (__arm_vclsq_s8): Likewise. (__arm_vclsq_s16): Likewise. (__arm_vclsq_s32): Likewise. (__arm_vclzq_s8): Likewise. (__arm_vclzq_s16): Likewise. (__arm_vclzq_s32): Likewise. (__arm_vnegq_s8): Likewise. (__arm_vnegq_s16): Likewise. (__arm_vnegq_s32): Likewise. (__arm_vaddlvq_s32): Likewise. (__arm_vaddvq_s8): Likewise. (__arm_vaddvq_s16): Likewise. (__arm_vaddvq_s32): Likewise. (__arm_vmovlbq_s8): Likewise. (__arm_vmovlbq_s16): Likewise. (__arm_vmovltq_s8): Likewise. (__arm_vmovltq_s16): Likewise. (__arm_vmvnq_s8): Likewise. (__arm_vmvnq_s16): Likewise. (__arm_vmvnq_s32): Likewise. (__arm_vrev16q_s8): Likewise. (__arm_vrev32q_s8): Likewise. (__arm_vrev32q_s16): Likewise. (__arm_vqabsq_s8): Likewise. (__arm_vqabsq_s16): Likewise. (__arm_vqabsq_s32): Likewise. (__arm_vqnegq_s8): Likewise. (__arm_vqnegq_s16): Likewise. (__arm_vqnegq_s32): Likewise. (__arm_vmvnq_u8): Likewise. (__arm_vmvnq_u16): Likewise. (__arm_vmvnq_u32): Likewise. (__arm_vdupq_n_u8): Likewise. (__arm_vdupq_n_u16): Likewise. (__arm_vdupq_n_u32): Likewise. (__arm_vclzq_u8): Likewise. (__arm_vclzq_u16): Likewise. (__arm_vclzq_u32): Likewise. (__arm_vaddvq_u8): Likewise. (__arm_vaddvq_u16): Likewise. (__arm_vaddvq_u32): Likewise. (__arm_vrev32q_u8): Likewise. (__arm_vrev32q_u16): Likewise. (__arm_vmovltq_u8): Likewise. (__arm_vmovltq_u16): Likewise. (__arm_vmovlbq_u8): Likewise. (__arm_vmovlbq_u16): Likewise. (__arm_vrev16q_u8): Likewise. (__arm_vaddlvq_u32): Likewise. (__arm_vcvtpq_u16_f16): Likewise. (__arm_vcvtpq_u32_f32): Likewise. (__arm_vcvtnq_u16_f16): Likewise. (__arm_vcvtmq_u16_f16): Likewise. (__arm_vcvtmq_u32_f32): Likewise. (__arm_vcvtaq_u16_f16): Likewise. (__arm_vcvtaq_u32_f32): Likewise. (__arm_vcvtaq_s16_f16): Likewise. (__arm_vcvtaq_s32_f32): Likewise. (__arm_vcvtnq_s16_f16): Likewise. (__arm_vcvtnq_s32_f32): Likewise. (__arm_vcvtpq_s16_f16): Likewise. (__arm_vcvtpq_s32_f32): Likewise. (__arm_vcvtmq_s16_f16): Likewise. (__arm_vcvtmq_s32_f32): Likewise. (vdupq_n): Define polymorphic variant. (vabsq): Likewise. (vclsq): Likewise. (vclzq): Likewise. (vnegq): Likewise. (vaddlvq): Likewise. (vaddvq): Likewise. (vmovlbq): Likewise. (vmovltq): Likewise. (vmvnq): Likewise. (vrev16q): Likewise. (vrev32q): Likewise. (vqabsq): Likewise. (vqnegq): Likewise. * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. (UNOP_SNONE_NONE): Likewise. (UNOP_UNONE_UNONE): Likewise. (UNOP_UNONE_NONE): Likewise. * config/arm/constraints.md (e): Define new constriant to allow only even registers. * config/arm/mve.md (mve_vqabsq_s): Define RTL pattern. (mve_vnegq_s): Likewise. (mve_vmvnq_): Likewise. (mve_vdupq_n_): Likewise. (mve_vclzq_): Likewise. (mve_vclsq_s): Likewise. (mve_vaddvq_): Likewise. (mve_vabsq_s): Likewise. (mve_vrev32q_): Likewise. (mve_vmovltq_): Likewise. (mve_vmovlbq_): Likewise. (mve_vcvtpq_): Likewise. (mve_vcvtnq_): Likewise. (mve_vcvtmq_): Likewise. (mve_vcvtaq_): Likewise. (mve_vrev16q_v16qi): Likewise. (mve_vaddlvq_v4si): Likewise. 2020-03-17 Jakub Jelinek * lra-spills.c (remove_pseudos): Fix up duplicated word issue in a dump message. * tree-sra.c (create_access_replacement): Fix up duplicated word issue in a comment. * read-rtl-function.c (find_param_by_name, function_reader::parse_enum_value, function_reader::get_insn_by_uid): Likewise. * spellcheck.c (get_edit_distance_cutoff): Likewise. * tree-data-ref.c (create_ifn_alias_checks): Likewise. * tree.def (SWITCH_EXPR): Likewise. * selftest.c (assert_str_contains): Likewise. * ipa-param-manipulation.h (class ipa_param_body_adjustments): Likewise. * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise. * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise. * langhooks.h (struct lang_hooks_for_decls): Likewise. * ipa-prop.h (struct ipa_param_descriptor): Likewise. * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store): Likewise. * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise. * tree-ssa-reassoc.c (reassociate_bb): Likewise. * tree.c (component_ref_size): Likewise. * hsa-common.c (hsa_init_compilation_unit_data): Likewise. * gimple-ssa-sprintf.c (get_string_length, format_string, format_directive): Likewise. * omp-grid.c (grid_process_kernel_body_copy): Likewise. * input.c (string_concat_db::get_string_concatenation, test_lexer_string_locations_ucn4): Likewise. * cfgexpand.c (pass_expand::execute): Likewise. * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds, maybe_diag_overlap): Likewise. * rtl.c (RTX_CODE_HWINT_P_1): Likewise. * shrink-wrap.c (spread_components): Likewise. * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse): Likewise. * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): Likewise. * dwarf2out.c (dwarf2out_early_finish): Likewise. * gimple-ssa-store-merging.c: Likewise. * ira-costs.c (record_operand_costs): Likewise. * tree-vect-loop.c (vectorizable_reduction): Likewise. * target.def (dispatch): Likewise. (validate_dims, gen_ccmp_first): Fix up duplicated word issue in documentation text. * doc/tm.texi: Regenerated. * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up duplicated word issue in a comment. * config/i386/i386.c (ix86_test_loading_unspec): Likewise. * config/i386/i386-features.c (remove_partial_avx_dependency): Likewise. * config/msp430/msp430.c (msp430_select_section): Likewise. * config/gcn/gcn-run.c (load_image): Likewise. * config/aarch64/aarch64-sve.md (sve_ld1r): Likewise. * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise. * config/aarch64/falkor-tag-collision-avoidance.c (single_dest_per_chain): Likewise. * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise. * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise. * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise. * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000-logue.c (rs6000_emit_probe_stack_range_stack_clash): Likewise. * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise. Fix various other issues in the comment. 2020-03-17 Mihail Ionescu * config/arm/t-rmprofile: create new multilib for armv8.1-m.main+mve hard float and reuse v8-m.main ones for v8.1-m.main+mve. 2020-03-17 Jakub Jelinek PR tree-optimization/94015 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the function where EXP is address of the bytes being stored rather than the bytes themselves into count_nonzero_bytes_addr. Punt on zero sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs. Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before calling native_encode_expr if host or target doesn't have 8-bit chars. Formatting fixes. (count_nonzero_bytes_addr): New function. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define. (UNOP_SNONE_NONE_QUALIFIERS): Likewise. (UNOP_SNONE_IMM_QUALIFIERS): Likewise. (UNOP_UNONE_NONE_QUALIFIERS): Likewise. (UNOP_UNONE_UNONE_QUALIFIERS): Likewise. (UNOP_UNONE_IMM_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vmvnq_n_s16): Define macro. (vmvnq_n_s32): Likewise. (vrev64q_s8): Likewise. (vrev64q_s16): Likewise. (vrev64q_s32): Likewise. (vcvtq_s16_f16): Likewise. (vcvtq_s32_f32): Likewise. (vrev64q_u8): Likewise. (vrev64q_u16): Likewise. (vrev64q_u32): Likewise. (vmvnq_n_u16): Likewise. (vmvnq_n_u32): Likewise. (vcvtq_u16_f16): Likewise. (vcvtq_u32_f32): Likewise. (__arm_vmvnq_n_s16): Define intrinsic. (__arm_vmvnq_n_s32): Likewise. (__arm_vrev64q_s8): Likewise. (__arm_vrev64q_s16): Likewise. (__arm_vrev64q_s32): Likewise. (__arm_vrev64q_u8): Likewise. (__arm_vrev64q_u16): Likewise. (__arm_vrev64q_u32): Likewise. (__arm_vmvnq_n_u16): Likewise. (__arm_vmvnq_n_u32): Likewise. (__arm_vcvtq_s16_f16): Likewise. (__arm_vcvtq_s32_f32): Likewise. (__arm_vcvtq_u16_f16): Likewise. (__arm_vcvtq_u32_f32): Likewise. (vrev64q): Define polymorphic variant. * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. (UNOP_SNONE_NONE): Likewise. (UNOP_SNONE_IMM): Likewise. (UNOP_UNONE_UNONE): Likewise. (UNOP_UNONE_NONE): Likewise. (UNOP_UNONE_IMM): Likewise. * config/arm/mve.md (mve_vrev64q_): Define RTL pattern. (mve_vcvtq_from_f_): Likewise. (mve_vmvnq_n_): Likewise. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. (UNOP_NONE_SNONE_QUALIFIERS): Likewise. (UNOP_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vrndxq_f16): Define macro. (vrndxq_f32): Likewise. (vrndq_f16) Likewise. (vrndq_f32): Likewise. (vrndpq_f16): Likewise. (vrndpq_f32): Likewise. (vrndnq_f16): Likewise. (vrndnq_f32): Likewise. (vrndmq_f16): Likewise. (vrndmq_f32): Likewise. (vrndaq_f16): Likewise. (vrndaq_f32): Likewise. (vrev64q_f16): Likewise. (vrev64q_f32): Likewise. (vnegq_f16): Likewise. (vnegq_f32): Likewise. (vdupq_n_f16): Likewise. (vdupq_n_f32): Likewise. (vabsq_f16): Likewise. (vabsq_f32): Likewise. (vrev32q_f16): Likewise. (vcvttq_f32_f16): Likewise. (vcvtbq_f32_f16): Likewise. (vcvtq_f16_s16): Likewise. (vcvtq_f32_s32): Likewise. (vcvtq_f16_u16): Likewise. (vcvtq_f32_u32): Likewise. (__arm_vrndxq_f16): Define intrinsic. (__arm_vrndxq_f32): Likewise. (__arm_vrndq_f16): Likewise. (__arm_vrndq_f32): Likewise. (__arm_vrndpq_f16): Likewise. (__arm_vrndpq_f32): Likewise. (__arm_vrndnq_f16): Likewise. (__arm_vrndnq_f32): Likewise. (__arm_vrndmq_f16): Likewise. (__arm_vrndmq_f32): Likewise. (__arm_vrndaq_f16): Likewise. (__arm_vrndaq_f32): Likewise. (__arm_vrev64q_f16): Likewise. (__arm_vrev64q_f32): Likewise. (__arm_vnegq_f16): Likewise. (__arm_vnegq_f32): Likewise. (__arm_vdupq_n_f16): Likewise. (__arm_vdupq_n_f32): Likewise. (__arm_vabsq_f16): Likewise. (__arm_vabsq_f32): Likewise. (__arm_vrev32q_f16): Likewise. (__arm_vcvttq_f32_f16): Likewise. (__arm_vcvtbq_f32_f16): Likewise. (__arm_vcvtq_f16_s16): Likewise. (__arm_vcvtq_f32_s32): Likewise. (__arm_vcvtq_f16_u16): Likewise. (__arm_vcvtq_f32_u32): Likewise. (vrndxq): Define polymorphic variants. (vrndq): Likewise. (vrndpq): Likewise. (vrndnq): Likewise. (vrndmq): Likewise. (vrndaq): Likewise. (vrev64q): Likewise. (vnegq): Likewise. (vabsq): Likewise. (vrev32q): Likewise. (vcvtbq_f32): Likewise. (vcvttq_f32): Likewise. (vcvtq): Likewise. * config/arm/arm_mve_builtins.def (VAR2): Define. (VAR1): Define. * config/arm/mve.md (mve_vrndxq_f): Add RTL pattern. (mve_vrndq_f): Likewise. (mve_vrndpq_f): Likewise. (mve_vrndnq_f): Likewise. (mve_vrndmq_f): Likewise. (mve_vrndaq_f): Likewise. (mve_vrev64q_f): Likewise. (mve_vnegq_f): Likewise. (mve_vdupq_n_f): Likewise. (mve_vabsq_f): Likewise. (mve_vrev32q_fv8hf): Likewise. (mve_vcvttq_f32_f16v4sf): Likewise. (mve_vcvtbq_f32_f16v4sf): Likewise. (mve_vcvtq_to_f_): Likewise. 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (CF): Define mve_builtin_data. (VAR1): Define. (ARM_BUILTIN_MVE_PATTERN_START): Define. (arm_init_mve_builtins): Define function. (arm_init_builtins): Add TARGET_HAVE_MVE check. (arm_expand_builtin_1): Check the range of fcode. (arm_expand_mve_builtin): Define function to expand MVE builtins. (arm_expand_builtin): Check the range of fcode. * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point types. (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace. (vst4q_s8): Define macro. (vst4q_s16): Likewise. (vst4q_s32): Likewise. (vst4q_u8): Likewise. (vst4q_u16): Likewise. (vst4q_u32): Likewise. (vst4q_f16): Likewise. (vst4q_f32): Likewise. (__arm_vst4q_s8): Define inline builtin. (__arm_vst4q_s16): Likewise. (__arm_vst4q_s32): Likewise. (__arm_vst4q_u8): Likewise. (__arm_vst4q_u16): Likewise. (__arm_vst4q_u32): Likewise. (__arm_vst4q_f16): Likewise. (__arm_vst4q_f32): Likewise. (__ARM_mve_typeid): Define macro with MVE types. (__ARM_mve_coerce): Define macro with _Generic feature. (vst4q): Define polymorphic variant for different vst4q builtins. * config/arm/arm_mve_builtins.def: New file. * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI modes in MVE. * config/arm/mve.md (MVE_VLD_ST): Define iterator. (unspec): Define unspec. (mve_vst4q): Define RTL pattern. * config/arm/neon.md (mov): Modify expand to allow XI and OI modes in MVE. (neon_mov): Modify RTL define_insn to allow XI and OI modes in MVE. (define_split): Allow OI mode split for MVE after reload. (define_split): Allow XI mode split for MVE after reload. * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def. (arm-builtins.o): Likewise. 2020-03-17 Christophe Lyon * c-typeck.c (process_init_element): Handle constructor_type with type size represented by POLY_INT_CST. 2020-03-17 Jakub Jelinek PR tree-optimization/94187 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if nchars - offset < nbytes. PR middle-end/94189 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would emit a warning if it was enabled and don't depend on TREE_NO_WARNING for code-generation. 2020-03-16 Vladimir Makarov PR target/94185 * lra-spills.c (remove_pseudos): Do not reuse insn alternative after changing memory subreg. 2020-03-16 Andre Vieira Srinath Parvathaneni * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add emulator calls for dobule precision arithmetic operations for MVE. 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base feature bit is on and -mfpu=auto is passed as compiler option, do not generate error on not finding any matching fpu. Because in this case fpu is not required. * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is enabled for MVE and also for all VFP extensions. (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2 is enabled. (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em. (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5 along with feature bits mve_float. (mve): Modify add options in armv8.1-m.main arch for MVE. (mve.fp): Modify add options in armv8.1-m.main arch for MVE with floating point. * config/arm/arm.c (use_return_insn): Replace the check with TARGET_VFP_BASE. (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with TARGET_VFP_BASE. (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as well. (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE as well. (arm_compute_frame_layout): Likewise. (arm_save_coproc_regs): Likewise. (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM in MVE as well. (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. (arm_expand_epilogue_apcs_frame): Likewise. (arm_expand_epilogue): Likewise. (arm_conditional_register_usage): Likewise. (arm_declare_function_name): Add check to skip printing .fpu directive in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is "softvfp". * config/arm/arm.h (TARGET_VFP_BASE): Define. * config/arm/arm.md (arch): Add "mve" to arch. (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true. (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE. * config/arm/constraints.md (Uf): Define to allow modification to FPCCR in MVE. * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard to not allow for MVE. * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs enum. (VUNSPEC_GET_FPSCR): Define. * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS instructions which move to general-purpose Register from Floating-point Special register and vice-versa. (thumb2_movhi_fp16): Likewise. (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along with MCR and MRC instructions which set and get Floating-point Status and Control Register (FPSCR). (movdi_vfp): Modify pattern to enable Single-precision scalar float move in MVE. (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar float move patterns in MVE. (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check. (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding TARGET_VFP_BASE check. (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR register. (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR register. 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config.gcc (arm_mve.h): Include mve intrinsics header file. * config/arm/aout.h (p0): Add new register name for MVE predicated cases. * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro common to Neon and MVE. (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK. (arm_init_simd_builtin_types): Disable poly types for MVE. (arm_init_neon_builtins): Move a check to arm_init_builtins function. (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of ARM_BUILTIN_NEON_LANE_CHECK. (mve_dereference_pointer): Add function. (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is enabled. (arm_expand_neon_builtin): Moved to arm_expand_builtin function. (arm_expand_builtin): Moved from arm_expand_neon_builtin function. * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE with floating point enabled. * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to simd_immediate_valid_for_move. (simd_immediate_valid_for_move): Renamed from neon_immediate_valid_for_move function. * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate error if vfpv2 feature bit is disabled and mve feature bit is also disabled for HARD_FLOAT_ABI. (use_return_insn): Check to not push VFP regs for MVE. (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard as Neon. (aapcs_vfp_allocate_return_reg): Likewise. (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2 address operand for MVE. (arm_rtx_costs_internal): MVE check to determine cost of rtx. (neon_valid_immediate): Rename to simd_valid_immediate. (simd_valid_immediate): Rename from neon_valid_immediate. (simd_valid_immediate): MVE check on size of vector is 128 bits. (neon_immediate_valid_for_move): Rename to simd_immediate_valid_for_move. (simd_immediate_valid_for_move): Rename from neon_immediate_valid_for_move. (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate function. (neon_make_constant): Modify call to neon_valid_immediate function. (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC for MVE. (output_move_neon): Add MVE check to generate vldm/vstm instrcutions. (arm_compute_frame_layout): Calculate space for saved VFP registers for MVE. (arm_save_coproc_regs): Save coproc registers for MVE. (arm_print_operand): Add case 'E' to print memory operands for MVE. (arm_print_operand_address): Check to print register number for MVE. (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE. (arm_modes_tieable_p): Check to allow structure mode for MVE. (arm_regno_class): Add VPR_REGNUM check. (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code for APCS frame. (arm_expand_epilogue): MVE check for enabling pop instructions in epilogue. (arm_print_asm_arch_directives): Modify function to disable print of .arch_extension "mve" and "fp" for cases where MVE is enabled with "SOFT FLOAT ABI". (arm_vector_mode_supported_p): Check for modes available in MVE interger and MVE floating point. (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode pointer support. (arm_conditional_register_usage): Enable usage of conditional regsiter for MVE. (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE. (arm_declare_function_name): Modify function to disable print of .arch_extension "mve" and "fp" for cases where MVE is enabled with "SOFT FLOAT ABI". * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and when target general registers are required. (TARGET_HAVE_MVE_FLOAT): Likewise. (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c for MVE. (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS which indicate this is not available for across function calls. (FIRST_PSEUDO_REGISTER): Modify. (VALID_MVE_MODE): Define valid MVE mode. (VALID_MVE_SI_MODE): Define valid MVE SI mode. (VALID_MVE_SF_MODE): Define valid MVE SF mode. (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode. (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence for MVE. (IS_VPR_REGNUM): Macro to check for VPR_REG register. (REG_ALLOC_ORDER): Add VPR_REGNUM entry. (enum reg_class): Add VPR_REG entry. (REG_CLASS_NAMES): Add VPR_REG entry. * config/arm/arm.md (VPR_REGNUM): Define. (conds): Check is_mve_type attrbiute to differentiate "conditional" and "unconditional" instructions. (arm_movsf_soft_insn): Modify RTL to not allow for MVE. (movdf_soft_insn): Modify RTL to not allow for MVE. (vfp_pop_multiple_with_writeback): Enable for MVE. (include "mve.md"): Include mve.md file. * config/arm/arm_mve.h: Add MVE intrinsics head file. * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE for vector predicated operands. * config/arm/iterators.md (VNIM1): Define. (VNINOTM1): Define. (VHFBF_split): Define * config/arm/mve.md: New file. (mve_mov): Define RTL for move, store and load in MVE. (mve_mov): Define move RTL pattern with vec_duplicate operator for second operand. * config/arm/neon.md (neon_immediate_valid_for_move): Rename with simd_immediate_valid_for_move. (neon_mov): Split pattern and move expand pattern "movv8hf" which is common to MVE and NEON to vec-common.md file. (vec_init): Add TARGET_HAVE_MVE check. * config/arm/predicates.md (vpr_register_operand): Define. * config/arm/t-arm: Add mve.md file. * config/arm/types.md (mve_move): Add MVE instructions mve_move to attribute "type". (mve_store): Add MVE instructions mve_store to attribute "type". (mve_load): Add MVE instructions mve_load to attribute "type". (is_mve_type): Define attribute. * config/arm/vec-common.md (mov): Modify RTL expand to support standard move patterns in MVE along with NEON and IWMMXT with mode iterator VNIM1. (mov): Modify RTL expand to support standard move patterns in NEON and IWMMXT with mode iterator V8HF. (movv8hf): Define RTL expand to support standard "movv8hf" pattern in NEON and MVE. * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to simd_immediate_valid_for_move. 2020-03-16 H.J. Lu PR target/89229 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL check. * config/i386/predicates.md (ext_sse_reg_operand): Removed. 2020-03-16 Jakub Jelinek PR debug/94167 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands DEBUG_STMTs. PR tree-optimization/94166 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION as secondary comparison key. 2020-03-16 Bin Cheng PR tree-optimization/94125 * tree-loop-distribution.c (loop_distribution::break_alias_scc_partitions): Update post order number for merged scc. 2020-03-15 H.J. Lu PR target/89229 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and MODE_SF. * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL and ext_sse_reg_operand check. 2020-03-15 Lewis Hyatt * common.opt: Avoid redundancy in the help text. * config/arc/arc.opt: Likewise. * config/cr16/cr16.opt: Likewise. 2020-03-14 Jakub Jelinek PR middle-end/93566 * tree-nested.c (convert_nonlocal_omp_clauses, convert_local_omp_clauses): Handle {,in_,task_}reduction clauses with C/C++ array sections. 2020-03-14 H.J. Lu PR target/89229 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL check. 2020-03-14 Jakub Jelinek * gimple-fold.c (gimple_fold_builtin_strncpy): Change "a an" to "an" in a comment. * hsa-common.h (is_a_helper): Likewise. * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise. * config/arc/arc.c (arc600_corereg_hazard): Likewise. * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise. 2020-03-13 Aaron Sawdey PR target/92379 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a 64-bit value by 64 bits (UB). 2020-03-13 Vladimir Makarov PR rtl-optimization/92303 * lra-spills.c (remove_pseudos): Try to simplify memory subreg. 2020-03-13 Segher Boessenkool PR rtl-optimization/94148 PR rtl-optimization/94042 * df-core.c (BB_LAST_CHANGE_AGE): Delete. (df_worklist_propagate_forward): New parameter last_change_age, use that instead of bb->aux. (df_worklist_propagate_backward): Ditto. (df_worklist_dataflow_doublequeue): Use a local array last_change_age. 2020-03-13 Richard Biener PR tree-optimization/94163 * tree-ssa-pre.c (create_expression_by_pieces): Check whether alignment would be zero. 2020-03-13 Martin Liska PR lto/94157 * lto-wrapper.c (run_gcc): Use concat for appending to collect_gcc_options. 2020-03-13 Jakub Jelinek PR target/94121 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode instead of GEN_INT. 2020-03-13 H.J. Lu PR target/89229 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF. * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256, TARGET_AVX512VL and ext_sse_reg_operand check. 2020-03-13 Bu Le PR target/94154 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=) (-param=aarch64-double-recp-precision=): New options. * doc/invoke.texi: Document them. * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them instead of hard-coding the choice of 1 for float and 2 for double. 2020-03-13 Eric Botcazou PR rtl-optimization/94119 * resource.h (clear_hashed_info_until_next_barrier): Declare. * resource.c (clear_hashed_info_until_next_barrier): New function. * reorg.c (add_to_delay_list): Fix formatting. (relax_delay_slots): Call clear_hashed_info_until_next_barrier on the next instruction after removing a BARRIER. 2020-03-13 Eric Botcazou PR middle-end/92071 * expmed.c (store_integral_bit_field): For fields larger than a word, call extract_bit_field on the value if the mode is BLKmode. Remove specific path for big-endian targets and tidy things up a little bit. 2020-03-12 Richard Sandiford PR rtl-optimization/90275 * cse.c (cse_insn): Delete no-op register moves too. 2020-03-12 Darius Galis * config/rx/rx.md (CTRLREG_CPEN): Remove. * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support. 2020-03-12 Richard Biener PR tree-optimization/94103 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type punning when the mode precision is not sufficient. 2020-03-12 H.J. Lu PR target/89229 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI, MODE_V1DF and MODE_V2SF. * config/i386/mmx.md (MMXMODE:*mov_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand check. 2020-03-12 Jakub Jelinek * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL. * doc/tm.texi: Regenerated. PR tree-optimization/94130 * tree-ssa-dse.c: Include gimplify.h. (increment_start_addr): If stmt has lhs, drop the lhs from call and set it after the call to the original value of the first argument. Formatting fixes. (decrement_count): Formatting fix. 2020-03-11 Delia Burduv * config/arm/arm-builtins.c (arm_init_simd_builtin_scalar_types): New. * config/arm/arm_neon.h (vld2_bf16): Used new builtin type. (vld2q_bf16): Used new builtin type. (vld3_bf16): Used new builtin type. (vld3q_bf16): Used new builtin type. (vld4_bf16): Used new builtin type. (vld4q_bf16): Used new builtin type. (vld2_dup_bf16): Used new builtin type. (vld2q_dup_bf16): Used new builtin type. (vld3_dup_bf16): Used new builtin type. (vld3q_dup_bf16): Used new builtin type. (vld4_dup_bf16): Used new builtin type. (vld4q_dup_bf16): Used new builtin type. 2020-03-11 Jakub Jelinek PR target/94134 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section at the start to switch to data section. Don't print extra newline if .globl directive has not been emitted. 2020-03-11 Richard Biener * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]): New pattern. 2020-03-11 Eric Botcazou PR middle-end/93961 * tree.c (variably_modified_type_p) : Recurse into fields whose type is a qualified union. 2020-03-11 Jakub Jelinek PR target/94121 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT. PR bootstrap/93962 * value-prof.c (dump_histogram_value): Use abs_hwi instead of std::abs. (get_nth_most_common_value): Use abs_hwi instead of abs. PR middle-end/94111 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl is rvc_normal, otherwise use real_to_decimal to print the number to string. PR tree-optimization/94114 * tree-loop-distribution.c (generate_memset_builtin): Call rewrite_to_non_trapping_overflow even on mem. (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even on dest and src. 2020-03-10 Jeff Law * config/bfin/bfin.md (movsi_insv): Add length attribute. 2020-03-10 Jiufu Guo PR target/93709 * gcc/config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check NAN and SIGNED_ZEROR for smax/smin. 2020-03-10 Will Schmidt PR target/90763 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add clause to handle P9V_BUILTIN_VEC_LXVL with const arguments. 2020-03-10 Roman Zhuykov * loop-iv.c (find_simple_exit): Make it static. * cfgloop.h: Remove the corresponding prototype. 2020-03-10 Roman Zhuykov * ddg.c (create_ddg): Fix intendation. (set_recurrence_length): Likewise. (create_ddg_all_sccs): Likewise. 2020-03-10 Jakub Jelinek PR target/94088 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with CCZmode instead of CCNOmode if operands[2] has DImode and pos + len is 32. 2020-03-09 Jason Merrill * gdbinit.in (pgs): Fix typo in documentation. 2020-03-09 Vladimir Makarov Revert: 2020-02-28 Vladimir Makarov PR rtl-optimization/93564 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we do not honor reg alloc order. 2020-03-09 Andrew Pinski PR inline-asm/94095 * doc/extend.texi (x86 Operand Modifiers): Fix column for 'A' modifier. 2020-03-09 Martin Liska PR target/93800 * config/rs6000/rs6000.c (rs6000_option_override_internal): Remove set of str_align_loops and str_align_jumps as these should be set in previous 2 conditions in the function. 2020-03-09 Jakub Jelinek PR rtl-optimization/94045 * params.opt (-param=max-find-base-term-values=): New option. * alias.c (find_base_term): Add cut-off for number of visited VALUEs in a single toplevel find_base_term call. 2020-03-06 Wilco Dijkstra PR target/91598 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define. * config/aarch64/aarch64-simd.md (aarch64_vec_mult_lane): Add new insn for widening lane mul. (aarch64_vec_mlal_lane): Likewise. * config/aarch64/aarch64-simd-builtins.def: Add intrinsics. * config/aarch64/arm_neon.h: (vmlal_lane_s16): Expand using intrinsics rather than inline asm. (vmlal_lane_u16): Likewise. (vmlal_lane_s32): Likewise. (vmlal_lane_u32): Likewise. (vmlal_laneq_s16): Likewise. (vmlal_laneq_u16): Likewise. (vmlal_laneq_s32): Likewise. (vmlal_laneq_u32): Likewise. (vmull_lane_s16): Likewise. (vmull_lane_u16): Likewise. (vmull_lane_s32): Likewise. (vmull_lane_u32): Likewise. (vmull_laneq_s16): Likewise. (vmull_laneq_u16): Likewise. (vmull_laneq_s32): Likewise. (vmull_laneq_u32): Likewise. * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul. (Qlane): Likewise. 2020-03-06 Wilco Dijkstra * aarch64/aarch64-simd.md (aarch64_mla_elt): Correct lane syntax. (aarch64_mla_elt_): Likewise. (aarch64_mls_elt): Likewise. (aarch64_mls_elt_): Likewise. (aarch64_fma4_elt): Likewise. (aarch64_fma4_elt_): Likewise. (aarch64_fma4_elt_to_64v2df): Likewise. (aarch64_fnma4_elt): Likewise. (aarch64_fnma4_elt_): Likewise. (aarch64_fnma4_elt_to_64v2df): Likewise. 2020-03-06 Kyrylo Tkachov * config/aarch64/aarch64-sve2.md (@aarch64_sve_: Specify movprfx attribute. (@aarch64_sve__lane_): Likewise. 2020-03-06 David Edelsohn PR target/94065 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for cmodel=large. (TARGET_NO_FP_IN_TOC): Same. * config/rs6000/aix71.h: Same. * config/rs6000/aix72.h: Same. 2020-03-06 Andrew Pinski Jeff Law PR rtl-optimization/93996 * haifa-sched.c (remove_notes): Be more careful when adding REG_SAVE_NOTE. 2020-03-06 Delia Burduv * config/arm/arm_neon.h (vld2_bf16): New. (vld2q_bf16): New. (vld3_bf16): New. (vld3q_bf16): New. (vld4_bf16): New. (vld4q_bf16): New. (vld2_dup_bf16): New. (vld2q_dup_bf16): New. (vld3_dup_bf16): New. (vld3q_dup_bf16): New. (vld4_dup_bf16): New. (vld4q_dup_bf16): New. * config/arm/arm_neon_builtins.def (vld2): Changed to VAR13 and added v4bf, v8bf (vld2_dup): Changed to VAR8 and added v4bf, v8bf (vld3): Changed to VAR13 and added v4bf, v8bf (vld3_dup): Changed to VAR8 and added v4bf, v8bf (vld4): Changed to VAR13 and added v4bf, v8bf (vld4_dup): Changed to VAR8 and added v4bf, v8bf * config/arm/iterators.md (VDXBF2): New iterator. *config/arm/neon.md (neon_vld2): Use new iterators. (neon_vld2_dup): Likewise. (neon_vld3qa): Likewise. (neon_vld3qb): Likewise. (neon_vld3_dup): Likewise. (neon_vld4): Likewise. (neon_vld4qa): Likewise. (neon_vld4qb): Likewise. (neon_vld4_dup): Likewise. (neon_vld2_dupv8bf): New. (neon_vld3_dupv8bf): Likewise. (neon_vld4_dupv8bf): Likewise. 2020-03-06 Delia Burduv * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef. (bfloat16x8x2_t): New typedef. (bfloat16x4x3_t): New typedef. (bfloat16x8x3_t): New typedef. (bfloat16x4x4_t): New typedef. (bfloat16x8x4_t): New typedef. (vst2_bf16): New. (vst2q_bf16): New. (vst3_bf16): New. (vst3q_bf16): New. (vst4_bf16): New. (vst4q_bf16): New. * config/arm/arm-builtins.c (v2bf_UP): Define. (VAR13): New. (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype. * config/arm/arm-modes.def (V2BF): New mode. * config/arm/arm-simd-builtin-types.def (Bfloat16x2_t): New entry. * config/arm/arm_neon_builtins.def (vst2): Changed to VAR13 and added v4bf, v8bf (vst3): Changed to VAR13 and added v4bf, v8bf (vst4): Changed to VAR13 and added v4bf, v8bf * config/arm/iterators.md (VDXBF): New iterator. (VQ2BF): New iterator. *config/arm/neon.md (neon_vst2): Used new iterators. (neon_vst2): Used new iterators. (neon_vst3): Used new iterators. (neon_vst3): Used new iterators. (neon_vst3qa): Used new iterators. (neon_vst3qb): Used new iterators. (neon_vst4): Used new iterators. (neon_vst4): Used new iterators. (neon_vst4qa): Used new iterators. (neon_vst4qb): Used new iterators. 2020-03-06 Delia Burduv * config/aarch64/aarch64-simd-builtins.def (bfcvtn): New built-in function. (bfcvtn_q): New built-in function. (bfcvtn2): New built-in function. (bfcvt): New built-in function. * config/aarch64/aarch64-simd.md (aarch64_bfcvtn): New pattern. (aarch64_bfcvtn2v8bf): New pattern. (aarch64_bfcvtbf): New pattern. * config/aarch64/arm_bf16.h (float32_t): New typedef. (vcvth_bf16_f32): New intrinsic. * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic. (vcvtq_low_bf16_f32): New intrinsic. (vcvtq_high_bf16_f32): New intrinsic. * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator. (UNSPEC_BFCVTN): New UNSPEC. (UNSPEC_BFCVTN2): New UNSPEC. (UNSPEC_BFCVT): New UNSPEC. * config/arm/types.md (bf_cvt): New type. 2020-03-06 Andreas Krebbel * config/s390/s390.md ("tabort"): Get rid of two consecutive blanks in format string. 2020-03-05 H.J. Lu PR target/89229 PR target/89346 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype. * config/i386/i386.c (ix86_get_ssemov): New function. (ix86_output_ssemov): Likewise. * config/i386/sse.md (VMOVE:mov_internal): Call ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL check. (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV. (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL check. (*movti_internal): Likewise. (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV. 2020-03-05 Jeff Law PR tree-optimization/91890 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument. Use gimple_or_expr_nonartificial_location. (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds. Use gimple_or_expr_nonartificial_location. * gimple.c (gimple_or_expr_nonartificial_location): New function. * gimple.h (gimple_or_expr_nonartificial_location): Declare it. * tree-ssa-strlen.c (maybe_warn_overflow): Use gimple_or_expr_nonartificial_location. (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise. (maybe_warn_pointless_strcmp): Likewise. 2020-03-05 Jakub Jelinek PR target/94046 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of SRC and MASK arguments to __m128 from __m128d. (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256 from __m256d. (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128 from __m128d. * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C argument to __m128i from __m128d. (_mm256_permute2_pd): Fix first cast of C argument to __m256i from __m256d. (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128. (_mm256_permute2_ps): Fix first cast of C argument to __m256i from __m256. 2020-03-05 Delia Burduv * config/arm/arm_neon.h (vbfmmlaq_f32): New. (vbfmlalbq_f32): New. (vbfmlaltq_f32): New. (vbfmlalbq_lane_f32): New. (vbfmlaltq_lane_f32): New. (vbfmlalbq_laneq_f32): New. (vbfmlaltq_laneq_f32): New. * config/arm/arm_neon_builtins.def (vmmla): New. (vfmab): New. (vfmat): New. (vfmab_lane): New. (vfmat_lane): New. (vfmab_laneq): New. (vfmat_laneq): New. * config/arm/iterators.md (BF_MA): New int iterator. (bt): New int attribute. (VQXBF): Copy of VQX with V8BF. * config/arm/neon.md (neon_vmmlav8bf): New insn. (neon_vfmav8bf): New insn. (neon_vfma_lanev8bf): New insn. (neon_vfma_laneqv8bf): New expand. (neon_vget_high): Changed iterator to VQXBF. * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC. (UNSPEC_BFMAB): New UNSPEC. (UNSPEC_BFMAT): New UNSPEC. 2020-03-05 Jakub Jelinek PR middle-end/93399 * tree-pretty-print.h (pretty_print_string): Declare. * tree-pretty-print.c (pretty_print_string): Remove forward declaration, no longer static. Change nbytes parameter type from unsigned to size_t. * print-rtl.c (print_value) : Use pretty_print_string and for shrink way too long strings. 2020-03-05 Richard Biener Jakub Jelinek PR tree-optimization/93582 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR last operand as signed when looking for memset offset. Formatting fix. 2020-03-04 Andrew Pinski PR bootstrap/93962 * value-prof.c (dump_histogram_value): Use std::abs. 2020-03-04 Martin Sebor PR tree-optimization/93986 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int operands to the same precision widest_int to avoid ICEs. 2020-03-04 Bill Schmidt PR target/87560 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define. * rs6000.c (rs6000_disable_incompatible_switches): Add table entry for OPTION_MASK_ALTIVEC. 2020-03-04 Andreas Krebbel * config.gcc: Include the glibc-stdint.h header for zTPF. 2020-03-04 Andreas Krebbel * config/s390/s390.c (s390_secondary_memory_needed): Disallow direct FPR-GPR copies. (s390_register_info_gprtofpr): Disallow GPR content to be saved in FPRs. 2020-03-04 Andreas Krebbel * config/s390/s390.c (s390_emit_prologue): Specify the 2 new operands to the prologue_tpf expander. (s390_emit_epilogue): Likewise. (s390_option_override_internal): Do error checking and setup for the new options. * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK) (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET) (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET) (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions. * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new operands for the check flag and the branch target. * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check") ("mtpf-trace-hook-prologue-target") ("mtpf-trace-hook-epilogue-check") ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New options. * doc/invoke.texi: Document -mtpf-trace-skip option. The other options are for debugging purposes and will not be documented here. 2020-03-04 Jakub Jelinek PR debug/93888 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag. * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti argument. Change pd argument so that it can be modified. Turn constant non-CONSTRUCTOR store into non-constant if it is too large. Adjust offset and size of CONSTRUCTOR or non-constant store to avoid overflows. (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust callers. 2020-02-04 Richard Biener PR tree-optimization/93964 * graphite-isl-ast-to-gimple.c (gcc_expression_from_isl_ast_expr_id): Add intermediate conversion for pointer to integer converts. * graphite-scop-detection.c (assign_parameter_index_in_region): Relax assert. 2020-03-04 Martin Liska PR c/93886 PR c/93887 * doc/invoke.texi: Clarify --help=language and --help=common interaction. 2020-03-04 Jakub Jelinek PR tree-optimization/94001 * tree-tailcall.c (process_assignment): Before comparing op1 to *ass_var, verify *ass_var is non-NULL. 2020-03-04 Kito Cheng PR target/93995 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare the result of IOR. 2020-03-03 Dennis Zhang * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New. * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New. (vcvtq_high_f32_bf16, vcvt_bf16_f32): New. (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New. * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries. (vbfcvtv4sf, vbfcvtv4sf_high): Likewise. * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators. (V_bf_low, V_bf_cvt_m): New mode attributes. * config/arm/neon.md (neon_vbfcvtv4sf): New. (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New. (neon_vbfcvt, neon_vbfcvt_highv8bf): New. (neon_vbfcvtbf_cvtmode, neon_vbfcvtbf): New * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New. 2020-03-03 Jakub Jelinek PR tree-optimization/93582 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument. * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result members, initialize them in the constructor and if mask is non-NULL, artificially push_partial_def {} for the portions of the mask that contain zeros. (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to val and return (void *)-1. Formatting fix. (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization. Formatting fix. (vn_reference_lookup): Add mask argument. If non-NULL, don't call fully_constant_vn_reference_p nor vn_reference_lookup_1 and return data.mask_result. (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST mask. (visit_stmt): Formatting fix. 2020-03-03 Richard Biener PR tree-optimization/93946 * alias.h (refs_same_for_tbaa_p): Declare. * alias.c (refs_same_for_tbaa_p): New function. * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return zero. * tree-ssa-scopedtables.h (avail_exprs_stack::lookup_avail_expr): Add output argument giving access to the hashtable entry. * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr): Likewise. * tree-ssa-dom.c: Include alias.h. (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before removing redundant store. * tree-ssa-sccvn.h (vn_reference_s::base_set): New member. (ao_ref_init_from_vn_reference): Adjust prototype. (vn_reference_lookup_pieces): Likewise. (vn_reference_insert_pieces): Likewise. * tree-ssa-sccvn.c: Track base alias set in addition to alias set everywhere. (eliminate_dom_walker::eliminate_stmt): Also check base alias set when removing redundant stores. (visit_reference_op_store): Likewise. * dse.c (record_store): Adjust valdity check for redundant store removal. 2020-03-03 Jakub Jelinek PR target/26877 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder. PR rtl-optimization/94002 * explow.c (plus_constant): Punt if cst has VOIDmode and get_pool_mode is different from mode. 2020-03-03 Claudiu Zissulescu * config/arc/arc.c (leigitimate_small_data_address_p): Check if an address has an offset which fits the scalling constraint for a load/store operation. (legitimate_scaled_address_p): Update use leigitimate_small_data_address_p. (arc_print_operand): Likewise. (arc_legitimate_address_p): Likewise. (legitimate_small_data_address_p): Likewise. 2020-03-03 Claudiu Zissulescu * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate. (fnmasf4_fpu): Likewise. 2020-03-03 Claudiu Zissulescu * config/arc/arc.md (adddi3): Early expand the 64bit operation into 32bit ops. (subdi3): Likewise. (adddi3_i): Remove pattern. (subdi3_i): Likewise. 2020-03-03 Claudiu Zissulescu * config/arc/arc.md (eh_return): Add length info. 2020-03-02 David Malcolm * doc/invoke.texi (-fanalyzer-show-duplicate-count): New. 2020-03-02 David Malcolm * doc/invoke.texi (Static Analyzer Options): Add -Wanalyzer-stale-setjmp-buffer to the list of options enabled by -fanalyzer. 2020-03-02 Uroš Bizjak PR target/93997 * config/i386/i386.md (movstrict): Allow only registers with VALID_INT_MODE_P modes. 2020-03-02 Andrew Stubbs * config/gcn/gcn-valu.md (dpp_move): New. (reduc_insn): Use 'U' and 'B' operand codes. (reduc__scal_): Allow all types. (reduc__scal_v64di): Delete. (*_dpp_shr_): Allow all 1reg types. (*plus_carry_dpp_shr_v64si): Change to ... (*plus_carry_dpp_shr_): ... this and allow all 1reg int types. (mov_from_lane63_v64di): Change to ... (mov_from_lane63_): ... this, and allow all 64-bit modes. * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size. Support UNSPEC_MOV_DPP_SHR output formats. (gcn_expand_reduc_scalar): Add "use_moves" reductions. Add "use_extends" reductions. (print_operand_address): Add 'I' and 'U' codes. * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR. 2020-03-02 Martin Liska * lto-wrapper.c: Fix typo in comment about C++ standard version. 2020-03-01 Martin Sebor PR c++/92721 * calls.c (init_attr_rdwr_indices): Correctly handle attribute. 2020-03-01 Martin Sebor PR middle-end/93829 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that of a pointer in the outermost ADDR_EXPRs. 2020-02-28 Jeff Law * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19. * config/v850/v850.c (v850_asm_trampoline_template): Update accordingly. 2020-02-28 Michael Meissner PR target/93937 * config/rs6000/vsx.md (vsx_extract__mode_var): Delete insn. 2020-02-28 Martin Liska PR other/93965 * configure.ac: Improve detection of ld_date by requiring either two dashes or none. * configure: Regenerate. 2020-02-28 Vladimir Makarov PR rtl-optimization/93564 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we do not honor reg alloc order. 2020-02-27 Joel Hutton PR target/87612 * config/aarch64/aarch64.c (aarch64_override_options): Fix misleading warning string. 2020-02-27 Martin Sebor * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo. 2020-02-27 Michael Meissner PR target/93932 * config/rs6000/vsx.md (vsx_extract__var, VSX_D iterator): Split the insn into two parts. This insn only does variable extract from a register. (vsx_extract__var_load, VSX_D iterator): New insn, do variable extract from memory. (vsx_extract_v4sf_var): Split the insn into two parts. This insn only does variable extract from a register. (vsx_extract_v4sf_var_load): New insn, do variable extract from memory. (vsx_extract__var, VSX_EXTRACT_I iterator): Split the insn into two parts. This insn only does variable extract from a register. (vsx_extract__var_load, VSX_EXTRACT_I iterator): New insn, do variable extract from memory. 2020-02-27 Martin Jambor Feng Xue PR ipa/93707 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with new function calls_same_node_or_its_all_contexts_clone_p. (cgraph_edge_brings_value_p): Use it. (cgraph_edge_brings_value_p): Likewise. (self_recursive_pass_through_p): Return false if caller is a clone. (self_recursive_agg_pass_through_p): Likewise. 2020-02-27 Jan Hubicka PR middle-end/92152 * alias.c (ends_tbaa_access_path_p): Break out from ... (component_uses_parent_alias_set_from): ... here. * alias.h (ends_tbaa_access_path_p): Declare. * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...; handle trailing arrays past end of tbaa access path. (aliasing_component_refs_p): ... here; likewise. (nonoverlapping_refs_since_match_p): Track TBAA segment of the access path; disambiguate also past end of it. (nonoverlapping_component_refs_p): Use only TBAA segment of the access path. 2020-02-27 Mihail Ionescu * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the beginning of the file. (vcreate_bf16, vcombine_bf16): New. (vdup_n_bf16, vdupq_n_bf16): New. (vdup_lane_bf16, vdup_laneq_bf16): New. (vdupq_lane_bf16, vdupq_laneq_bf16): New. (vduph_lane_bf16, vduph_laneq_bf16): New. (vset_lane_bf16, vsetq_lane_bf16): New. (vget_lane_bf16, vgetq_lane_bf16): New. (vget_high_bf16, vget_low_bf16): New. (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New. (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New. (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New. (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New. (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New. (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New. (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New. (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New. (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New. (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New. (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New. (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New. (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New. (vreinterpretq_bf16_p128): New. (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New. (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New. (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New. (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New. (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New. (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New. (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New. (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New. (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New. (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New. (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New. (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New. (vreinterpretq_p128_bf16): New. * config/arm/arm_neon_builtins.def (VDX): Add V4BF. (V_elem): Likewise. (V_elem_l): Likewise. (VD_LANE): Likewise. (VQX) Add V8BF. (V_DOUBLE): Likewise. (VDQX): Add V4BF and V8BF. (V_two_elem, V_three_elem, V_four_elem): Likewise. (V_reg): Likewise. (V_HALF): Likewise. (V_double_vector_mode): Likewise. (V_cmp_result): Likewise. (V_uf_sclr): Likewise. (V_sz_elem): Likewise. (Is_d_reg): Likewise. (V_mode_nunits): Likewise. * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16. 2020-02-27 Andrew Stubbs * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator. (2): Change modes to VEC_ALL1REG_INT_MODE. (3): Likewise. (3): New. (v3): New. (3): New. (3): Rename to ... (v64si3): ... this, and change modes to V64SI. * config/gcn/gcn.md (mnemonic): Use '%B' for not. 2020-02-27 Alexandre Oliva * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave them alone on vx7. 2020-02-27 Richard Biener PR tree-optimization/93508 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like non-_CHK variants. Valueize their length arguments. 2020-02-27 Richard Biener PR tree-optimization/93953 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference to the hash-map entry. 2020-02-27 Andrew Stubbs * config/gcn/gcn.md (mov): Add transformations for BI subregs. 2020-02-27 Mark Williams * dwarf2out.c (file_name_acquire): Call remap_debug_filename. * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map, -ffile-prefix-map and -fmacro-prefix-map. * lto-streamer-out.c: Include file-prefix-map.h. (lto_output_location): Remap the file part of locations. 2020-02-27 Jakub Jelinek PR c/93949 * gimplify.c (gimplify_init_constructor): Don't promote readonly DECL_REGISTER variables to TREE_STATIC. PR tree-optimization/93582 PR tree-optimization/93945 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with non-zero INTEGER_CST second argument and ref->offset or ref->size not a multiple of BITS_PER_UNIT. 2020-02-27 Jonathan Wakely * doc/install.texi (Binaries): Update description of BullFreeware. 2020-02-26 Sandra Loosemore PR c++/90467 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in C++ Language Options, Warning Options, and Static Analyzer Options lists. Document negative form of options enabled by default. Move some things around to more accurately sort warnings by category. (C++ Dialect Options, Warning Options, Static Analyzer Options): Document negative form of options when enabled by default. Move some things around to more accurately sort warnings by category. Add some missing index entries. Light copy-editing. 2020-02-26 Carl Love PR target/91276 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only for the vector unsigned short arguments. It is also listed as the name of the built-in for arguments vector unsigned short, vector unsigned int and vector unsigned long long built-ins. The name of the builtins for these arguments should be: __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and __builtin_crypto_vpmsumd respectively. 2020-02-26 Richard Biener * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count and load permutation. 2020-02-26 Richard Sandiford PR middle-end/93843 * optabs-tree.c (supportable_convert_operation): Reject types with scalar modes. 2020-02-26 David Malcolm * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o. 2020-02-26 Jakub Jelinek PR tree-optimization/93820 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE argument to ALL_INTEGER_CST_P boolean. (imm_store_chain_info::try_coalesce_bswap): Adjust caller. (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle adjacent INTEGER_CST store into merged_store->only_constants like overlapping one. 2020-02-25 Jakub Jelinek PR other/93912 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity -> probability. * cfghooks.c (verify_flow_info): Likewise. * predict.c (combine_predictions_for_bb): Likewise. * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo, sucessor -> successor. (find_traces_1_round): Fix comment typo, destinarion -> destination. * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors -> successors. * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump message typo, sucessors -> successors. 2020-02-25 Martin Sebor * doc/extend.texi (attribute access): Correct an example. 2020-02-25 Mihail Ionescu * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types): Add simd_bf. (aarch64_init_simd_builtin_scalar_types): Register simd_bf. (VAR15, VAR16): New. * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF. (VD): Enable for V4BF. (VDC): Likewise. (VQ): Enable for V8BF. (VQ2): Likewise. (VQ_NO2E): Likewise. (VDBL, Vdbl): Add V4BF. (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF. * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef. (bfloat16x8x2_t): Likewise. (bfloat16x4x3_t): Likewise. (bfloat16x8x3_t): Likewise. (bfloat16x4x4_t): Likewise. (bfloat16x8x4_t): Likewise. (vcombine_bf16): New. (vld1_bf16, vld1_bf16_x2): New. (vld1_bf16_x3, vld1_bf16_x4): New. (vld1q_bf16, vld1q_bf16_x2): New. (vld1q_bf16_x3, vld1q_bf16_x4): New. (vld1_lane_bf16): New. (vld1q_lane_bf16): New. (vld1_dup_bf16): New. (vld1q_dup_bf16): New. (vld2_bf16): New. (vld2q_bf16): New. (vld2_dup_bf16): New. (vld2q_dup_bf16): New. (vld3_bf16): New. (vld3q_bf16): New. (vld3_dup_bf16): New. (vld3q_dup_bf16): New. (vld4_bf16): New. (vld4q_bf16): New. (vld4_dup_bf16): New. (vld4q_dup_bf16): New. (vst1_bf16, vst1_bf16_x2): New. (vst1_bf16_x3, vst1_bf16_x4): New. (vst1q_bf16, vst1q_bf16_x2): New. (vst1q_bf16_x3, vst1q_bf16_x4): New. (vst1_lane_bf16): New. (vst1q_lane_bf16): New. (vst2_bf16): New. (vst2q_bf16): New. (vst3_bf16): New. (vst3q_bf16): New. (vst4_bf16): New. (vst4q_bf16): New. 2020-02-25 Mihail Ionescu * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF. (VALL_F16): Likewise. (VALLDI_F16): Likewise. (Vtype): Likewise. (Vetype): Likewise. (vswap_width_name): Likewise. (VSWAP_WIDTH): Likewise. (Vel): Likewise. (VEL): Likewise. (q): Likewise. * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New. (vget_lane_bf16, vgetq_lane_bf16): New. (vcreate_bf16): New. (vdup_n_bf16, vdupq_n_bf16): New. (vdup_lane_bf16, vdup_laneq_bf16): New. (vdupq_lane_bf16, vdupq_laneq_bf16): New. (vduph_lane_bf16, vduph_laneq_bf16): New. (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New. (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New. (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New. (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New. (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New. (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New. (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New. (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New. (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New. (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New. (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New. (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New. (vreinterpretq_bf16_p128): New. (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New. (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New. (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New. (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New. (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New. (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New. (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New. (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New. (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New. (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New. (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New. (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New. (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New. (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New. (vreinterpretq_p128_bf16): New. 2020-02-25 Dennis Zhang * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New (vbfdot_lane_f32, vbfdotq_laneq_f32): New. (vbfdot_laneq_f32, vbfdotq_lane_f32): New. * config/arm/arm_neon_builtins.def (vbfdot): New entry. (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise. * config/arm/iterators.md (VSF2BF): New attribute. * config/arm/neon.md (neon_vbfdot): New entry. (neon_vbfdot_lanev4bf): Likewise. (neon_vbfdot_lanev8bf): Likewise. 2020-02-25 Christophe Lyon * config/arm/arm.md (required_for_purecode): New attribute. (enabled): Handle required_for_purecode. * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to work with -mpure-code. 2020-02-25 Jakub Jelinek PR rtl-optimization/93908 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src with mask. 2019-02-25 Eric Botcazou * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode. 2020-02-25 Roman Zhuykov * doc/install.texi (--enable-checking): Adjust wording. 2020-02-25 Richard Biener PR tree-optimization/93868 * tree-vect-slp.c (slp_copy_subtree): New function. (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before re-arranging stmts in it. 2020-02-25 Jakub Jelinek PR middle-end/93874 * passes.c (pass_manager::dump_passes): Create a cgraph node for the dummy function and remove it at the end. PR translation/93864 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo paramter -> parameter. * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise. * ipa-prop.h (struct ipa_agg_replacement_value): Likewise. 2020-02-24 Roman Zhuykov * doc/install.texi (--enable-checking): Properly document current behavior. (--enable-stage1-checking): Minor clarification about bootstrap. 2020-02-24 David Malcolm PR analyzer/93032 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that -fanalyzer-checker=taint is also required. (-fanalyzer-checker=): Note that providing this option enables the given checker, and doing so may be required for checkers that are disabled by default. 2020-02-24 David Malcolm * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows significant control flow events; add a "3" which shows all control flow events; the old "3" becomes "4". 2020-02-24 Jakub Jelinek PR tree-optimization/93582 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider pd.offset and pd.size to be counted in bits rather than bytes, add support for maxsizei that is not a multiple of BITS_PER_UNIT and handle bitfield stores and loads. (vn_reference_lookup_3): Don't call ranges_known_overlap_p with uncomparable quantities - bytes vs. bits. Allow push_partial_def on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust pd.offset/pd.size to be counted in bits rather than bytes. Formatting fix. Rename shadowed len variable to buflen. 2020-02-24 Prathamesh Kulkarni Kugan Vivekandarajah PR driver/47785 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function. (driver::main): Call putenv_COLLECT_AS_OPTIONS. * opts-common.c (parse_options_from_collect_gcc_options): New function. (prepend_xassembler_to_collect_as_options): Likewise. * opts.h (parse_options_from_collect_gcc_options): Declare prototype. (prepend_xassembler_to_collect_as_options): Likewise. * lto-opts.c (lto_write_options): Stream assembler options in COLLECT_AS_OPTIONS. * lto-wrapper.c (xassembler_options_error): New static variable. (get_options_from_collect_gcc_options): Move parsing options code to parse_options_from_collect_gcc_options and call it. (merge_and_complain): Validate -Xassembler options. (append_compiler_options): Handle OPT_Xassembler. (run_gcc): Append command line -Xassembler options to collect_gcc_options. * doc/invoke.texi: Add documentation about using Xassembler options with LTO. 2020-02-24 Kito Cheng * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen for LTGT. (riscv_rtx_costs): Update cost model for LTGT. 2020-02-23 Vladimir Makarov PR rtl-optimization/93564 * ira-color.c (struct update_cost_queue_elem): New member start. (queue_update_cost, get_next_update_cost): Add new arg start. (allocnos_conflict_p): New function. (update_costs_from_allocno): Add new arg conflict_cost_update_p. Add checking conflicts with allocnos_conflict_p. (update_costs_from_prefs, restore_costs_from_copies): Adjust update_costs_from_allocno calls. (update_conflict_hard_regno_costs): Add checking conflicts with allocnos_conflict_p. Adjust calls of queue_update_cost and get_next_update_cost. (assign_hard_reg): Adjust calls of queue_update_cost. Add debugging print. (bucket_allocno_compare_func): Restore previous version. 2020-02-21 John David Anglin * gcc/config/pa/pa.c (pa_function_value): Fix check for word and double-word size when handling aggregate return values. * gcc/config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate that homogeneous SFmode and DFmode aggregates are passed and returned in general registers. 2020-02-21 Jakub Jelinek PR translation/93759 * opts.c (print_filtered_help): Translate help before appending messages to it rather than after that. 2020-02-19 Richard Sandiford PR rtl-optimization/PR92989 * lra-lives.c (process_bb_lives): Restore the original order of the bb liveness update. Call make_hard_regno_dead for each register clobbered at the start of an EH receiver. 2020-02-18 Feng Xue PR ipa/93763 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as self-recursively generated. 2020-02-21 Iain Sandoe PR target/93860 * config/darwin-c.c (pop_field_alignment): Adjust quoting of error string. 2020-02-21 Mihail Ionescu * doc/sourcebuild.texi (arm_v8_1m_mve_ok): Document new target supports option. 2020-02-21 Dennis Zhang * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New. * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New. * config/arm/iterators.md (MATMUL): New iterator. (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US. (mmla_sfx): New attribute. * config/arm/neon.md (neon_mmlav16qi): New. * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New. (UNSPEC_MATMUL_US): New. 2020-02-21 Mihail-Calin Ionescu * config/arm/arm.md: Prevent scalar shifts from being used when big endian is enabled. 2020-02-21 Jan Hubicka Richard Biener PR tree-optimization/93586 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk after mismatched array refs; do not sure type size information to recover from unmatched referneces with !flag_strict_aliasing_p. 2020-02-21 Andrew Stubbs * config/gcn/gcn-valu.md (gather_load): Rename to ... (gather_loadv64si): ... this and set operand 2 to V64SI. (scatter_store): Rename to ... (scatter_storev64si): ... this and set operand 1 to V64SI. (scatter_exec): Delete. Move contents ... (mask_scatter_store): ... here, and rename that to ... (mask_gather_loadv64si): ... this. Set operand 2 to V64SI. Remove mode conversion. (mask_gather_load): Rename to ... (mask_scatter_storev64si): ... this. Set operand 1 to V64SI. Remove mode conversion. * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion. 2020-02-21 Martin Jambor PR tree-optimization/93845 * tree-sra.c (verify_sra_access_forest): Only test access size of scalar types. 2020-02-21 Andrew Stubbs * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs. * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber. (addv64di3_exec): Likewise. (subv64di3): Likewise. (subv64di3_exec): Likewise. (addv64di3_zext): Likewise. (addv64di3_zext_exec): Likewise. (addv64di3_zext_dup): Likewise. (addv64di3_zext_dup_exec): Likewise. (addv64di3_zext_dup2): Likewise. (addv64di3_zext_dup2_exec): Likewise. (addv64di3_sext_dup2): Likewise. (addv64di3_sext_dup2_exec): Likewise. (v64di3): Likewise. (v64di3_exec): Likewise. (*_dpp_shr_v64di): Likewise. (*plus_carry_dpp_shr_v64di): Likewise. * config/gcn/gcn.md (adddi3): Likewise. (addptrdi3): Likewise. (di3): Likewise. 2020-02-21 Andrew Stubbs * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di. 2020-02-21 Richard Sandiford * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE support. Use aarch64_emit_mult instead of emitting multiplication instructions directly. * config/aarch64/aarch64-sve.md (sqrt2, rsqrt2) (@aarch64_rsqrte, @aarch64_rsqrts): New expanders. 2020-02-21 Richard Sandiford * config/aarch64/aarch64.c (aarch64_emit_mult): New function. (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult instead of emitting multiplication instructions directly. * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator. * config/aarch64/aarch64-sve.md (div3, @aarch64_frecpe) (@aarch64_frecps): New expanders. 2020-02-21 Richard Sandiford * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate on and produce uint64_ts rather than ints. (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts. (cpu_approx_modes): Change the fields from unsigned int to uint64_t. 2020-02-21 Richard Sandiford * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create an unused xmsk register when handling approximate rsqrt. 2020-02-21 Richard Sandiford * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted flag_finite_math_only condition. 2020-02-20 Uroš Bizjak PR target/93828 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand to destination operand for shufps alternative. (*vec_extractv2si_1): Ditto. 2020-02-20 Peter Bergner PR target/93658 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX vector modes. 2020-02-20 Martin Liska PR translation/93831 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode. 2020-02-20 Martin Liska PR translation/93830 * common/config/avr/avr-common.c: Remote trailing "|". 2020-02-19 Bernd Edlinger * collect2.c (maybe_run_lto_and_relink): Fix typo in comment. 2020-02-19 Richard Sandiford PR tree-optimization/93767 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the access-size bias from the offset calculations for negative strides. 2020-02-19 Bernd Edlinger * collect2.c (c_file, o_file): Make const again. (ldout,lderrout, dump_ld_file): Remove. (tool_cleanup): Avoid calling not signal-safe functions. (maybe_run_lto_and_relink): Avoid possible signal handler access to unintialzed memory (lto_o_files). (main): Avoid leaking temp files in $TMPDIR. Initialize c_file/o_file with concat, which avoids exposing uninitialized memory to signal handler, which calls unlink(!). Avoid calling maybe_unlink when the main function returns, since the atexit handler is already doing this. * collect2.h (dump_ld_file, ldout, lderrout): Remove. 2020-02-19 Martin Jambor PR tree-optimization/93776 * tree-sra.c (create_access): Do not create zero size accesses. (get_access_for_expr): Do not search for zero sized accesses. 2020-02-19 Martin Jambor PR tree-optimization/93667 * tree-sra.c (scalarizable_type_p): Return false if record fields do not follow wach other. 2020-01-21 Kito Cheng * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x. 2020-02-18 James Greenhalgh * config/aarch64/aarch64-simd-builtins.def (intrinsic_vec_smult_lo_): New. (intrinsic_vec_umult_lo_): Likewise. (vec_widen_smult_hi_): Likewise. (vec_widen_umult_hi_): Likewise. * config/aarch64/aarch64-simd.md (aarch64_intrinsic_vec_mult_lo_): New. * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics. (vmull_high_s16): Likewise. (vmull_high_s32): Likewise. (vmull_high_u8): Likewise. (vmull_high_u16): Likewise. (vmull_high_u32): Likewise. (vmull_s8): Likewise. (vmull_s16): Likewise. (vmull_s32): Likewise. (vmull_u8): Likewise. (vmull_u16): Likewise. (vmull_u32): Likewise. 2020-02-18 Martin Liska * value-prof.c (stream_out_histogram_value): Restore LTO PGO bootstrap by missing removal of invalid sanity check. 2020-02-18 Martin Liska PR ipa/92518 * ipa-icf-gimple.c (func_checker::compare_gimple_assign): Always compare LHS of gimple_assign. 2020-02-18 Martin Liska PR ipa/93583 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute and return type of functions. * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl): Drop MALLOC attribute for void functions. * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop malloc_state for a new VOID clone. 2020-02-18 Martin Liska PR ipa/92924 * common.opt: Add -fprofile-reproducibility. * doc/invoke.texi: Document it. * value-prof.c (dump_histogram_value): Document and support behavior for counters[0] being a negative value. (get_nth_most_common_value): Handle negative counters[0] in respect to flag_profile_reproducible. 2020-02-18 Jakub Jelinek PR ipa/93797 * cgraph.c (verify_speculative_call): Use speculative_id instead of speculative_uid in messages. Remove trailing whitespace from error message. Use num_speculative_call_targets instead of num_speculative_targets in a message. (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in edge messages and stmt instead of cal_stmt in reference message. PR tree-optimization/93780 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p before calling build_vector_type. (execute_update_addresses_taken): Likewise. PR driver/93796 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help typo, functoin -> function. * tree.c (free_lang_data_in_decl): Fix comment typo, functoin -> function. * ipa-visibility.c (cgraph_externally_visible_p): Likewise. 2020-02-17 David Malcolm * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs won't be printed. (print_option_information): Don't call get_option_url if URLs won't be printed. 2020-02-17 Alexandre Oliva * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete handling of register_common-less targets. 2020-02-17 Martin Liska PR ipa/93760 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar. 2020-02-17 Martin Liska PR translation/93755 * config/rs6000/rs6000.c (rs6000_option_override_internal): Fix double quotes. 2020-02-17 Martin Liska PR other/93756 * config/rx/elf.opt: Fix typo. 2020-02-17 Richard Biener PR c/86134 * opts-global.c (print_ignored_options): Use inform and amend message. 2020-02-17 Jiufu Guo PR target/93047 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber. 2020-02-16 Uroš Bizjak PR target/93743 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2. (atan23): Update operand order in the call to gen_atan2xf3. 2020-02-15 Jason Merrill * doc/invoke.texi (C Dialect Options): Add -std=c++20. 2020-02-15 Jakub Jelinek PR tree-optimization/93744 * match.pd (((m1 >/=/<= m2) * d -> (m1 >/=/<= m2) ? d : 0, A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A, A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make sure @2 in the first and @1 in the other patterns has no side-effects. 2020-02-15 David Malcolm Bernd Edlinger PR 87488 PR other/93168 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define. * configure.ac (--with-diagnostics-urls): New configuration option, based on --with-diagnostics-color. (DIAGNOSTICS_URLS_DEFAULT): New define. * config.h: Regenerate. * configure: Regenerate. * diagnostic.c (diagnostic_urls_init): Handle -1 for DIAGNOSTICS_URLS_DEFAULT from configure-time --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS and TERM_URLS environment variable. * diagnostic-url.h (diagnostic_url_format): New enum type. (diagnostic_urls_enabled_p): rename to... (determine_url_format): ... this, and change return type. * diagnostic-color.c (parse_env_vars_for_urls): New helper function. (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal, the linux console, and mingw. (diagnostic_urls_enabled_p): rename to... (determine_url_format): ... this, and adjust. * pretty-print.h (pretty_printer::show_urls): rename to... (pretty_printer::url_format): ... this, and change to enum. * pretty-print.c (pretty_printer::pretty_printer, pp_begin_url, pp_end_url, test_urls): Adjust. * doc/install.texi (--with-diagnostics-urls): Document the new configuration option. (--with-diagnostics-color): Document the existing interaction with GCC_COLORS better. * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS vindex reference. Update description of defaults based on the above. (-fdiagnostics-color): Update description of how -fdiagnostics-color interacts with GCC_COLORS. 2020-02-14 Eric Botcazou PR target/93704 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in conjunction with TARGET_GNU_TLS in early return. 2020-02-14 Alexander Monakov * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if the mode is not wider than UNITS_PER_WORD. 2020-02-14 Martin Jambor PR tree-optimization/93516 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create access of the same type as the parent. (propagate_subaccesses_from_lhs): Likewise. 2020-02-14 Hongtao Liu PR target/93724 * config/i386/avx512vbmi2intrin.h (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16, _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32, _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32, _m512_shrdi_epi64, _m512_mask_shrdi_epi64, _m512_maskz_shrdi_epi64, _mm512_shldi_epi16, _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16, _mm512_shldi_epi32, _mm512_mask_shldi_epi32, _mm512_maskz_shldi_epi32, _mm512_shldi_epi64, _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo of lacking a closing parenthesis. * config/i386/avx512vbmi2vlintrin.h (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16, _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32, _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32, _m256_shrdi_epi64, _m256_mask_shrdi_epi64, _m256_maskz_shrdi_epi64, _mm256_shldi_epi16, _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16, _mm256_shldi_epi32, _mm256_mask_shldi_epi32, _mm256_maskz_shldi_epi32, _mm256_shldi_epi64, _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64, _mm_shrdi_epi16, _mm_mask_shrdi_epi16, _mm_maskz_shrdi_epi16, _mm_shrdi_epi32, _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32, _mm_shrdi_epi64, _mm_mask_shrdi_epi64, _m_maskz_shrdi_epi64, _mm_shldi_epi16, _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16, _mm_shldi_epi32, _mm_mask_shldi_epi32, _mm_maskz_shldi_epi32, _mm_shldi_epi64, _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto. 2020-02-13 H.J. Lu PR target/93656 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at the target function entry. 2020-02-13 Claudiu Zissulescu * common/config/arc/arc-common.c (arc_option_optimization_table): Disable if-conversion step when optimized for size. 2020-02-13 Claudiu Zissulescu * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and R12-R15 are always in ARCOMPACT16_REGS register class. * config/arc/arc.opt (mq-class): Deprecate. * config/arc/constraint.md ("q"): Remove dependency on mq-class option. * doc/invoke.texi (mq-class): Update text. * common/config/arc/arc-common.c (arc_option_optimization_table): Update list. 2020-02-13 Claudiu Zissulescu * config/arc/arc.c (arc_insn_cost): New function. (TARGET_INSN_COST): Define. * config/arc/arc.md (cost): New attribute. (add_n): Use arc_nonmemory_operand. (ashlsi3_insn): Likewise, also update constraints. (ashrsi3_insn): Likewise. (rotrsi3): Likewise. (add_shift): Likewise. * config/arc/predicates.md (arc_nonmemory_operand): New predicate. 2020-02-13 Claudiu Zissulescu * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi registers. (umulsidi_600): Likewise. 2020-02-13 Jakub Jelinek PR target/93696 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8, _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8, _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8, _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W, pass __A to the builtin followed by __W instead of __A followed by __B. * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32, _mm512_mask_popcnt_epi64): Likewise. * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32, _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64, _mm256_mask_popcnt_epi64): Likewise. PR tree-optimization/93582 * fold-const.h (shift_bytes_in_array_left, shift_bytes_in_array_right): Declare. * fold-const.c (shift_bytes_in_array_left, shift_bytes_in_array_right): New function, moved from gimple-ssa-store-merging.c, no longer static. * gimple-ssa-store-merging.c (shift_bytes_in_array): Move to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left. (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c. (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of shift_bytes_in_array. (verify_shift_bytes_in_array): Rename to ... (verify_shift_bytes_in_array_left): ... this. Use shift_bytes_in_array_left instead of shift_bytes_in_array. (store_merging_c_tests): Call verify_shift_bytes_in_array_left instead of verify_shift_bytes_in_array. * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr / native_interpret_expr where the store covers all needed bits, punt on PDP-endian, otherwise allow all involved offsets and sizes not to be byte-aligned. PR target/93673 * config/i386/sse.md (k): Drop mode from last operand and use const_0_to_255_operand predicate instead of immediate_operand. (avx512dq_fpclass, avx512dq_vmfpclass, vgf2p8affineinvqb_, vgf2p8affineqb_): Drop mode from const_0_to_255_operand predicated operands. 2020-02-12 Jeff Law * config/h8300/h8300.md (comparison shortening peepholes): Use a mode iterator to merge the HImode and SImode peepholes. 2020-02-12 Jakub Jelinek PR middle-end/93663 * real.c (is_even): Make static. Function comment fix. (is_halfway_below): Make static, don't assert R is not inf/nan, instead return false for those. Small formatting fixes. 2020-02-12 Martin Sebor PR middle-end/93646 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename... (handle_builtin_stxncpy_strncat): ...to this. Change first argument. Issue only -Wstringop-overflow strncat, never -Wstringop-truncation. (strlen_check_and_optimize_call): Adjust callee name. 2020-02-12 Jeff Law * config/h8300/h8300.md (comparison shortening peepholes): Drop (and (xor)) variant. Combine other two into single peephole. 2020-02-12 Wilco Dijkstra PR rtl-optimization/93565 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs. 2020-02-12 Wilco Dijkstra * config/aarch64/aarch64-simd.md (aarch64_zero_extend_reduc_plus_): New pattern. * config/aarch64/aarch64.md (popcount2): Use it instead of generating separate ADDV and zero_extend patterns. * config/aarch64/iterators.md (VDQV_E): New iterator. 2020-02-12 Jeff Law * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns, expanders, splits, etc. (movmd_internal_, movmd splitter, movstr, movsd): Likewise. (stpcpy_internal_, stpcpy splitter): Likewise. (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise. * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function. (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused function prototype. (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise. 2020-02-12 Jakub Jelinek PR target/93670 * config/i386/sse.md (VI48F_256_DQ): New mode iterator. (avx512vl_vextractf128): Use it instead of VI48F_256. Remove TARGET_AVX512DQ from condition. (vec_extract_lo_): Use instead of in condition. If TARGET_AVX512DQ is false, emit vextract*64x4 instead of vextract*32x8. (vec_extract_lo_): Drop from condition. 2020-02-12 Kewen Lin PR target/91052 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn. 2020-02-12 Segher Boessenkool * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof where strlen is more legible. (rs6000_builtin_vectorized_libmass): Ditto. (rs6000_print_options_internal): Ditto. 2020-02-11 Martin Sebor PR tree-optimization/93683 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set. 2020-02-11 Michael Meissner * config/rs6000/predicates.md (cint34_operand): Rename the -mprefixed-addr option to be -mprefixed. * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename the -mprefixed-addr option to be -mprefixed. (OTHER_FUTURE_MASKS): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename the -mprefixed-addr option to be -mprefixed. Change error messages to refer to -mprefixed. (num_insns_constant_gpr): Rename the -mprefixed-addr option to be -mprefixed. (rs6000_legitimate_offset_address_p): Likewise. (rs6000_mode_dependent_address): Likewise. (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be "-mprefixed" for target attributes and pragmas. (address_to_insn_form): Rename the -mprefixed-addr option to be -mprefixed. (rs6000_adjust_insn_length): Likewise. * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the -mprefixed-addr option to be -mprefixed. (ASM_OUTPUT_OPCODE): Likewise. * config/rs6000/rs6000.md (prefixed insn attribute): Rename the -mprefixed-addr option to be -mprefixed. * config/rs6000/rs6000.opt (-mprefixed): Rename the -mprefixed-addr option to be prefixed. Change the option from being undocumented to being documented. * doc/invoke.texi (RS/6000 and PowerPC Options): Document the -mprefixed option. Update the -mpcrel documentation to mention -mprefixed. 2020-02-11 Hans-Peter Nilsson * ira-conflicts.c (print_hard_reg_set): Correct output for sets including FIRST_PSEUDO_REGISTER - 1. * ira-color.c (print_hard_reg_set): Ditto. 2020-02-11 Stam Markianos-Wright * config/arm/arm-builtins.c (enum arm_type_qualifiers): (USTERNOP_QUALIFIERS): New define. (USMAC_LANE_QUADTUP_QUALIFIERS): New define. (SUMAC_LANE_QUADTUP_QUALIFIERS): New define. (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX. (arm_expand_builtin_1): Add qualifier_lane_quadtup_index. * config/arm/arm_neon.h (vusdot_s32): New. (vusdot_lane_s32): New. (vusdotq_lane_s32): New. (vsudot_lane_s32): New. (vsudotq_lane_s32): New. * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New. * config/arm/iterators.md (DOTPROD_I8MM): New. (sup, opsuffix): Add . * config/arm/neon.md (neon_usdot, dot_lane: New. * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New. 2020-02-11 Richard Biener PR tree-optimization/93661 PR tree-optimization/93662 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard tree_to_poly_int64. * tree-sra.c (get_access_for_expr): Likewise. 2020-02-10 Jakub Jelinek PR target/93637 * config/i386/sse.md (VI_256_AVX2): New mode iterator. (vcond_mask_): Use it instead of VI_256. Change condition from TARGET_AVX2 to TARGET_AVX. 2020-02-10 Iain Sandoe PR other/93641 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last argument of strncmp. 2020-02-10 Hans-Peter Nilsson Try to generate zero-based comparisons. * config/cris/cris.c (cris_reduce_compare): New function. * config/cris/cris-protos.h (cris_reduce_compare): Add prototype. * config/cris/cris.md ("cbranch4", "cbranchdi4", "cstoredi4") (cstore4"): Apply cris_reduce_compare in expanders. 2020-02-10 Richard Earnshaw PR target/91913 * config/arm/arm.md (movsi_compare0): Allow SP as a source register in Thumb state and also as a destination in Arm state. Add T16 variants. 2020-02-10 Hans-Peter Nilsson * md.texi (Define Subst): Match closing paren in example. 2020-02-10 Jakub Jelinek PR target/58218 PR other/93641 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last arguments of strncmp. 2020-02-10 Feng Xue PR ipa/93203 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge but different source value. (adjust_callers_for_value_intersection): New function. (gather_edges_for_value): Adjust order of callers to let a non-self-recursive caller be the first element. (self_recursive_pass_through_p): Add a new parameter "simple", and check generalized self-recursive pass-through jump function. (self_recursive_agg_pass_through_p): Likewise. (find_more_scalar_values_for_callers_subset): Compute value from pass-through jump function for self-recursive. (intersect_with_plats): Cleanup previous implementation code for value itersection with self-recursive call edge. (intersect_with_agg_replacements): Likewise. (intersect_aggregates_with_edge): Deduce value from pass-through jump function for self-recursive call edge. Cleanup previous implementation code for value intersection with self-recursive call edge. (decide_whether_version_node): Remove dead callers and adjust order to let a non-self-recursive caller be the first element. 2020-02-09 Uroš Bizjak * recog.c: Move pass_split_before_sched2 code in front of pass_split_before_regstack. (pass_data_split_before_sched2): Rename pass to split3 from split4. (pass_data_split_before_regstack): Rename pass to split4 from split3. (rest_of_handle_split_before_sched2): Remove. (pass_split_before_sched2::execute): Unconditionally call split_all_insns. (enable_split_before_sched2): New function. (pass_split_before_sched2::gate): Use enable_split_before_sched2. (pass_split_before_regstack::gate): Ditto. * config/nds32/nds32.c (nds32_split_double_word_load_store_p): Update name check for renamed split4 pass. * config/sh/sh.c (register_sh_passes): Update pass insertion point for renamed split4 pass. 2020-02-09 Jakub Jelinek * gimplify.c (gimplify_adjust_omp_clauses_1): Promote DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid copying them around between host and target. 2020-02-08 Andrew Pinski PR target/91927 * config/aarch64/aarch64-simd.md (movmisalign): Check STRICT_ALIGNMENT also. 2020-02-08 Jim Wilson PR target/93532 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define. 2020-02-08 Uroš Bizjak Jakub Jelinek PR target/65782 * config/i386/i386.h (CALL_USED_REGISTERS): Make xmm16-xmm31 call-used even in 64-bit ms-abi. 2020-02-07 Dennis Zhang * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry. (simd_ummla, simd_usmmla): Likewise. * config/aarch64/aarch64-simd.md (aarch64_simd_mmlav16qi): New. * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New. (vusmmlaq_s32): New. 2020-02-07 Richard Biener PR middle-end/93519 * tree-inline.c (fold_marked_statements): Do a PRE walk, skipping unreachable regions. (optimize_inline_calls): Skip folding stmts when we didn't inline. 2020-02-07 H.J. Lu PR target/85667 * config/i386/i386.c (function_arg_ms_64): Add a type argument. Don't return aggregates with only SFmode and DFmode in SSE register. (ix86_function_arg): Pass arg.type to function_arg_ms_64. 2020-02-07 Jakub Jelinek PR target/93122 * config/rs6000/rs6000-logue.c (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn, if it fails, move rs into end_addr and retry. Add REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or the insn pattern doesn't describe well what exactly happens to dwarf2cfi.c. PR target/93594 * config/i386/predicates.md (avx_identity_operand): Remove. * config/i386/sse.md (*avx_vec_concat_1): Remove. (avx__, avx512f__256): Change patterns to a VEC_CONCAT of the operand and UNSPEC_CAST. (avx512f__): Change pattern to a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with UNSPEC_CAST. PR target/93611 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear recog_data.insn if distance_non_agu_define changed it. 2020-02-06 Michael Meissner PR target/93569 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0 we only had X-FORM (reg+reg) addressing for vectors. Also before ISA 3.0, we only had X-FORM addressing for scalars in the traditional Altivec registers. 2020-02-06 Vladimir Makarov PR rtl-optimization/93561 * lra-assigns.c (spill_for): Check that tested hard regno is not out of hard register range. 2020-02-06 Richard Sandiford * config/aarch64/aarch64.md (aarch64_movk): Add a type attribute. 2020-02-06 Segher Boessenkool * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case where the low and the high 32 bits are equal to each other specially, with an rldimi instruction. 2020-02-06 Mihail Ionescu * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main. 2020-02-06 Mihail Ionescu * config/arm/arm-tables.opt: Regenerate. 2020-02-06 Richard Sandiford PR target/87763 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare. * config/aarch64/aarch64.c (aarch64_movk_shift): New function. * config/aarch64/aarch64.md (aarch64_movk): New pattern. 2020-02-06 Richard Sandiford PR rtl-optimization/87763 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern. 2020-02-06 Delia Burduv * config/aarch64/aarch64-simd-builtins.def (bfmlaq): New built-in function. (bfmlalb): New built-in function. (bfmlalt): New built-in function. (bfmlalb_lane): New built-in function. (bfmlalt_lane): New built-in function. * config/aarch64/aarch64-simd.md (aarch64_bfmmlaqv4sf): New pattern. (aarch64_bfmlalv4sf): New pattern. (aarch64_bfmlal_lanev4sf): New pattern. * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic. (vbfmlalbq_f32): New intrinsic. (vbfmlaltq_f32): New intrinsic. (vbfmlalbq_lane_f32): New intrinsic. (vbfmlaltq_lane_f32): New intrinsic. (vbfmlalbq_laneq_f32): New intrinsic. (vbfmlaltq_laneq_f32): New intrinsic. * config/aarch64/iterators.md (BF_MLA): New int iterator. (bt): New int attribute. 2020-02-06 Uroš Bizjak * config/i386/i386.md (*pushtf): Emit "#" instead of calling gcc_unreachable in insn output. (*pushxf): Ditto. (*pushdf): Ditto. (*pushsf_rex64): Ditto for alternatives other than 1. (*pushsf): Ditto for alternatives other than 1. 2020-02-06 Martin Liska PR gcov-profile/91971 PR gcov-profile/93466 * coverage.c (coverage_init): Revert mangling of path into filename. It can lead to huge filename length. Creation of subfolders seem more natural. 2020-02-06 Stam Markianos-Wright PR target/93300 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New. (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs. Use arm_block_arith_comp_libfuncs_for_mode for HFmode. 2020-02-06 Jakub Jelinek PR target/93594 * config/i386/predicates.md (avx_identity_operand): New predicate. * config/i386/sse.md (*avx_vec_concat_1): New define_insn_and_split. PR libgomp/93515 * omp-low.c (use_pointer_for_field): For nested constructs, also look for map clauses on target construct. (scan_omp_1_stmt) : Bump temporarily taskreg_nesting_level. PR libgomp/93515 * gimplify.c (gimplify_scan_omp_clauses) : If adding shared clause, call omp_notice_variable on outer context if any. 2020-02-05 Jason Merrill PR c++/92003 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has non-zero address even if weak and not yet defined. 2020-02-05 Martin Sebor PR tree-optimization/92765 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL. * tree-ssa-strlen.c (compute_string_length): Remove. (determine_min_objsize): Remove. (get_len_or_size): Add an argument. Call get_range_strlen_dynamic. Avoid using type size as the upper bound on string length. (handle_builtin_string_cmp): Add an argument. Adjust. (strlen_check_and_optimize_call): Pass additional argument to handle_builtin_string_cmp. 2020-02-05 Uroš Bizjak * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove. (*pushdi2_rex64 peephole2): Unconditionally split after epilogue_completed. (*ashl3_doubleword): Ditto. (*3_doubleword): Ditto. 2020-02-05 Michael Meissner PR target/93568 * config/rs6000/rs6000.c (get_vector_offset): Fix 2020-02-05 Andrew Stubbs * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space. 2020-02-05 David Malcolm * doc/analyzer.texi (Special Functions for Debugging the Analyzer): Update description of __analyzer_dump_exploded_nodes. 2020-02-05 Jakub Jelinek PR target/92190 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only include sets and not clobbers in the vzeroupper pattern. * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that the parallel has 17 (64-bit) or 9 (32-bit) elts. (*avx_vzeroupper_1): New define_insn_and_split. PR target/92190 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets, don't run when !optimize. (pass_split_before_regstack::gate): For STACK_REGS targets, run even when !optimize. 2020-02-05 Richard Biener PR middle-end/90648 * genmatch.c (dt_node::gen_kids_1): Emit number of argument checks before matching calls. 2020-02-05 Jakub Jelinek * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up function comment typo. PR middle-end/93555 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or simd_clone_create failed when i == 0, adjust clone->nargs by clone->inbranch. 2020-02-05 Martin Liska PR c++/92717 * doc/invoke.texi: Document that one should not combine ASLR and -fpch. 2020-02-04 Richard Biener PR tree-optimization/93538 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr. 2020-02-04 Richard Biener PR tree-optimization/91123 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method. (vn_walk_cb_data::last_vuse): New member. (vn_walk_cb_data::saved_operands): Likewsie. (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands. (vn_walk_cb_data::push_partial_def): Use finish. (vn_reference_lookup_2): Update last_vuse and use finish if we've saved operands. (vn_reference_lookup_3): Use finish and update calls to push_partial_defs everywhere. When translating through memcpy or aggregate copies save off operands and alias-set. (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE operation for redundant store removal. 2020-02-04 Richard Biener PR tree-optimization/92819 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid generating more stmts than before. 2020-02-04 Martin Liska * config/arm/arm.c (arm_gen_far_branch): Move the function outside of selftests. 2020-02-03 Michael Meissner * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper function to adjust PC-relative vector addresses. (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to handle vectors with PC-relative addresses. 2020-02-03 Michael Meissner * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward reference. (hard_reg_and_mode_to_addr_mask): Delete. (rs6000_adjust_vec_address): If the original vector address was REG+REG or REG+OFFSET and the element is not zero, do the add of the elements in the original address before adding the offset for the vector element. Use address_to_insn_form to validate the address using the register being loaded, rather than guessing whether the address is a DS-FORM or DQ-FORM address. 2020-02-03 Michael Meissner * config/rs6000/rs6000.c (get_vector_offset): New helper function to calculate the offset in memory from the start of a vector of a particular element. Add code to keep the element number in bounds if the element number is variable. (rs6000_adjust_vec_address): Move calculation of offset of the vector element to get_vector_offset. (rs6000_split_vec_extract_var): Do not do the initial AND of element here, move the code to get_vector_offset. 2020-02-03 Michael Meissner * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some gcc_asserts. 2020-02-03 Segher Boessenkool * config/rs6000/constraints.md: Improve documentation. 2020-02-03 Richard Earnshaw PR target/93548 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md) ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change. 2020-02-03 Andrew Stubbs * config.gcc: Remove "carrizo" support. * config/gcn/gcn-opts.h (processor_type): Likewise. * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise. * config/gcn/gcn.opt (gpu_type): Likewise. * config/gcn/t-omp-device: Likewise. 2020-02-03 Stam Markianos-Wright PR target/91816 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype. * config/arm/arm.c (arm_gen_far_branch): New function arm_gen_far_branch. * config/arm/arm.md: Update b for Thumb2 range checks. 2020-02-03 Julian Brown Tobias Burnus * doc/invoke.texi: Update mention of OpenACC version to 2.6. 2020-02-03 Jakub Jelinek PR target/93533 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit valid RTL to sum up the lowest and second lowest bytes of the popcnt result. 2020-02-02 Vladimir Makarov PR rtl-optimization/91333 * ira-color.c (struct allocno_color_data): Add member hard_reg_prefs. (init_allocno_threads): Set the member up. (bucket_allocno_compare_func): Add compare hard reg prefs. 2020-01-31 Sandra Loosemore nios2: Support for GOT-relative DW_EH_PE_datarel encoding. * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION. * config.in: Regenerated. * configure: Regenerated. * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION. (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New. 2020-02-01 Andrew Burgess * configure: Regenerate. 2020-01-31 Vladimir Makarov PR rtl-optimization/91333 * ira-color.c (bucket_allocno_compare_func): Move conflict hard reg preferences comparison up. 2020-01-31 Richard Sandiford * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro. * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to aarch64-sve-builtins-base.h. * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to aarch64-sve-builtins-base.cc. * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane) (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) (svcvtnt): Declare. * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane) (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) (svcvtnt): New functions. * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane) (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla) (svcvtnt): New functions. (svcvt): Add a form that converts f32 to bf16. * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat) (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n): Declare. * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type): Treat B as bfloat16_t. (ternary_bfloat_lane_base): New class. (ternary_bfloat_def): Likewise. (ternary_bfloat): New shape. (ternary_bfloat_lane_def): New class. (ternary_bfloat_lane): New shape. (ternary_bfloat_lanex2_def): New class. (ternary_bfloat_lanex2): New shape. (ternary_bfloat_opt_n_def): New class. (ternary_bfloat_opt_n): New shape. * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro. * config/aarch64/aarch64-sve.md (@aarch64_sve_vnx4sf) (@aarch64_sve__lanevnx4sf): New patterns. (@aarch64_sve__trunc) (@cond__trunc): Likewise. (*cond__trunc): Likewise. (@aarch64_sve_cvtnt): Likewise. * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt): Key the pattern off the narrow mode instead of the wider one. * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator. (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs. (sve_fp_op): Handle them. (SVE_BFLOAT_TERNARY_LONG): New int itertor. (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise. 2020-01-31 Richard Sandiford * config/aarch64/arm_sve.h: Include arm_bf16.h. * config/aarch64/aarch64-modes.def (BF): Move definition before VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF. (SVE_MODES): Handle BF modes. * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle BF modes. (aarch64_full_sve_mode): Likewise. * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF and VNx32BF. (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF. (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore) (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count) (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the new SVE BF modes. * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New type_class_index. * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro. (TYPES_all_data): Add bf16. (TYPES_reinterpret1, TYPES_reinterpret): Likewise. (register_tuple_type): Increase buffer size. * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type. (bf16): New type suffix. * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv) (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax) (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr): Change type from all_data to all_arith. * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp) (svminp): Likewise. 2020-01-31 Dennis Zhang Matthew Malcomson Richard Sandiford * doc/invoke.texi (f32mm): Document new AArch64 -march= extension. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define __ARM_FEATURE_MATMUL_FP64. * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16) (sve): Add AARCH64_FL_F32MM to the list of extensions that should be disabled at the same time. (f32mm): New extension. * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro. (AARCH64_FL_F64MM): Bump to the next bit up. (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM) (TARGET_SVE_F64MM): New macros. * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator. (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL) (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q) (UNSPEC_ZIP2Q): New unspeccs. (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators. (optab, sur, perm_insn): Handle the new unspecs. (sve_fp_op): Handle UNSPEC_FMMLA. Resort. * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro): Use TARGET_SVE_F64MM instead of separate tests. (@aarch64_dot_prod): New pattern. (@aarch64_dot_prod_lane): Likewise. (@aarch64_sve_add_): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro. (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it. (TYPES_s_signed): New macro. (TYPES_s_integer): Use it. (TYPES_d_float): New macro. (TYPES_d_data): Use it. * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare. (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq) (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class. (svmmla): New shape. (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3 template parameters. (ternary_resize2_lane_base): Likewise. (ternary_resize2_base): New class. (ternary_qq_lane_base): Likewise. (ternary_intq_uintq_lane_def): Likewise. (ternary_intq_uintq_lane): New shape. (ternary_intq_uintq_opt_n_def): New class (ternary_intq_uintq_opt_n): New shape. (ternary_qq_lane_def): Inherit from ternary_qq_lane_base. (ternary_uintq_intq_def): New class. (ternary_uintq_intq): New shape. (ternary_uintq_intq_lane_def): New class. (ternary_uintq_intq_lane): New shape. (ternary_uintq_intq_opt_n_def): New class. (ternary_uintq_intq_opt_n): New shape. * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot) (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla) (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare. * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl): Generalize to... (svdotprod_lane_impl): ...this new class. (svmmla_impl, svusdot_impl): New classes. (svdot_lane): Update to use svdotprod_lane_impl. (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot) (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New functions. * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base function, with no types defined. (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New AARCH64_FL_I8MM functions. (svmmla): New AARCH64_FL_F32MM function. (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6. (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New AARCH64_FL_F64MM function. (REQUIRED_EXTENSIONS): 2020-01-31 Andrew Stubbs * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each alternative only. 2020-01-31 Uroš Bizjak * config/i386/i386.md (*movoi_internal_avx): Do not check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling. (*movti_internal): Do not check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. (*movtf_internal): Move check for TARGET_SSE2 and size optimization just after check for TARGET_AVX. (*movdf_internal): Ditto. * config/i386/mmx.md (*mov_internal): Do not check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. * config/i386/sse.md (mov_internal): Only check TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check for TARGET_SSE2 and size optimization just after check for TARGET_AVX. (_andnot3): Move check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX. (3): Ditto. (*andnot3): Ditto. (*andnottf3): Ditto. (*3): Ditto. (*tf3): Ditto. (*andnot3): Remove TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling. (3): Ditto. (*3): Ditto. (sse4_1_blendv): Ditto. * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Explain that tune applies to 128bit instructions only. 2020-01-31 Kwok Cheung Yeung * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count to definition of hsa_kernel_description. Parse assembly to find SGPR and VGPR count of kernel and store in hsa_kernel_description. 2020-01-31 Tamar Christina PR rtl-optimization/91838 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case to truncate if allowed or reject combination. 2020-01-31 Andrew Stubbs * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step. (find_inv_vars_cb): Likewise. 2020-01-31 David Malcolm * calls.c (special_function_p): Split out the check for DECL_NAME being non-NULL and fndecl being extern at file scope into a new maybe_special_function_p and call it. Drop check for fndecl being non-NULL that was after a usage of DECL_NAME (fndecl). * tree.h (maybe_special_function_p): New inline function. 2020-01-30 Andrew Stubbs * config/gcn/gcn-valu.md (gather_exec): Move contents ... (mask_gather_load): ... here, and zero-initialize the destination. (maskloaddi): Zero-initialize the destination. * config/gcn/gcn.c: 2020-01-30 David Malcolm PR analyzer/93356 * doc/analyzer.texi (Limitations): Note that constraints on floating-point values are currently ignored. 2020-01-30 Jakub Jelinek PR lto/93384 * symtab.c (symtab_node::noninterposable_alias): If localalias already exists, but is not usable, append numbers after it until a unique name is found. Formatting fix. PR middle-end/93505 * combine.c (simplify_comparison) : Punt on out of range rotate counts. 2020-01-30 Andrew Stubbs * config/gcn/gcn.c (print_operand): Handle LTGT. * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt. 2020-01-30 Richard Biener * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE. 2020-01-30 John David Anglin * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers without a DECL in .data.rel.ro.local. 2020-01-30 Jakub Jelinek PR target/93494 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4 returned. PR target/91824 * config/i386/sse.md (*_movmsk_zext): Renamed to ... (*_movmsk_ext): ... this. Use any_extend code iterator instead of always zero_extend. (*_movmsk_zext_lt): Renamed to ... (*_movmsk_ext_lt): ... this. Use any_extend code iterator instead of always zero_extend. (*_movmsk_zext_shift): Renamed to ... (*_movmsk_ext_shift): ... this. Use any_extend code iterator instead of always zero_extend. (*sse2_pmovmskb_ext): New define_insn. (*sse2_pmovmskb_ext_lt): New define_insn_and_split. PR target/91824 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split. (*popcountsi2_zext_falsedep): New define_insn. 2020-01-30 Dragan Mladjenovic * config.in: Regenerated. * configure: Regenerated. 2020-01-29 Tobias Burnus PR bootstrap/93409 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as LLVM's assembler changed the default in version 9. 2020-01-24 Jeff Law PR tree-optimization/89689 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure. 2020-01-29 Richard Sandiford Revert: 2020-01-28 Richard Sandiford PR rtl-optimization/87763 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract simplification to handle subregs as well as bare regs. * config/i386/i386.md (*testqi_ext_3): Match QI extracts too. 2020-01-29 Joel Hutton PR target/93221 * ira.c (ira): Revert use of simplified LRA algorithm. 2020-01-29 Martin Jambor PR tree-optimization/92706 * tree-sra.c (struct access): Fields first_link, last_link, next_queued and grp_queued renamed to first_rhs_link, last_rhs_link, next_rhs_queued and grp_rhs_queued respectively, new fields first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued. (struct assign_link): Field next renamed to next_rhs, new field next_lhs. Updated comment. (work_queue_head): Renamed to rhs_work_queue_head. (lhs_work_queue_head): New variable. (add_link_to_lhs): New function. (relink_to_new_repr): Also relink LHS lists. (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue. (add_access_to_lhs_work_queue): New function. (pop_access_from_work_queue): Renamed to pop_access_from_rhs_work_queue. (pop_access_from_lhs_work_queue): New function. (build_accesses_from_assign): Also add links to LHS lists and to LHS work_queue. (child_would_conflict_in_lacc): Renamed to child_would_conflict_in_acc. Adjusted parameter names. (create_artificial_child_access): New parameter set_grp_read, use it. (subtree_mark_written_and_enqueue): Renamed to subtree_mark_written_and_rhs_enqueue. (propagate_subaccesses_across_link): Renamed to propagate_subaccesses_from_rhs. (propagate_subaccesses_from_lhs): New function. (propagate_all_subaccesses): Also propagate subaccesses from LHSs to RHSs. 2020-01-29 Martin Jambor PR tree-optimization/92706 * tree-sra.c (struct access): Adjust comment of grp_total_scalarization. (find_access_in_subtree): Look for single children spanning an entire access. (scalarizable_type_p): Allow register accesses, adjust callers. (completely_scalarize): Remove function. (scalarize_elem): Likewise. (create_total_scalarization_access): Likewise. (sort_and_splice_var_accesses): Do not track total scalarization flags. (analyze_access_subtree): New parameter totally, adjust to new meaning of grp_total_scalarization. (analyze_access_trees): Pass new parameter to analyze_access_subtree. (can_totally_scalarize_forest_p): New function. (create_total_scalarization_access): Likewise. (create_total_access_and_reshape): Likewise. (total_should_skip_creating_access): Likewise. (totally_scalarize_subtree): Likewise. (analyze_all_variable_accesses): Perform total scalarization after subaccess propagation using the new functions above. (initialize_constant_pool_replacements): Output initializers by traversing the access tree. 2020-01-29 Martin Jambor * tree-sra.c (verify_sra_access_forest): New function. (verify_all_sra_access_forests): Likewise. (create_artificial_child_access): Set parent. (analyze_all_variable_accesses): Call the verifier. 2020-01-28 Jan Hubicka * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge if called on indirect edge. (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of speculative call if needed. 2020-01-29 Richard Biener PR tree-optimization/93428 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load permutation when the load node is created. (vect_analyze_slp_instance): Re-use it here. 2020-01-28 Jan Hubicka * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning. 2020-01-28 Vladimir Makarov PR rtl-optimization/93272 * ira-lives.c (process_out_of_region_eh_regs): New function. (process_bb_node_lives): Call it. 2020-01-28 Jan Hubicka * coverage.c (read_counts_file): Make error message lowercase. 2020-01-28 Jan Hubicka * profile-count.c (profile_quality_display_names): Fix ordering. 2020-01-28 Jan Hubicka PR lto/93318 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site hash only when edge is first within the sequence. (cgraph_edge::set_call_stmt): Update handling of speculative calls. (symbol_table::create_edge): Do not set target_prob. (cgraph_edge::remove_caller): Watch for speculative calls when updating the call site hash. (cgraph_edge::make_speculative): Drop target_prob parameter. (cgraph_edge::speculative_call_info): Remove. (cgraph_edge::first_speculative_call_target): New member function. (update_call_stmt_hash_for_removing_direct_edge): New function. (cgraph_edge::resolve_speculation): Rewrite to new API. (cgraph_edge::speculative_call_for_target): New member function. (cgraph_edge::make_direct): Rewrite to new API; fix handling of multiple speculation targets. (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating of profile. (verify_speculative_call): Verify that targets form an interval. * cgraph.h (cgraph_edge::speculative_call_info): Remove. (cgraph_edge::first_speculative_call_target): New member function. (cgraph_edge::next_speculative_call_target): New member function. (cgraph_edge::speculative_call_target_ref): New member function. (cgraph_edge;:speculative_call_indirect_edge): New member funtion. (cgraph_edge): Remove target_prob. * cgraphclones.c (cgraph_node::set_call_stmt_including_clones): Fix handling of speculative calls. * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals. * ipa-fnsummary.c (analyze_function_body): Likewise. * ipa-inline.c (speculation_useful_p): Use new speculative call API. * ipa-profile.c (dump_histogram): Fix formating. (ipa_profile_generate_summary): Watch for overflows. (ipa_profile): Do not require probablity to be 1/2; update to new API. * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API. (update_indirect_edges_after_inlining): Update to new API. * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call profiles. * profile-count.h: (profile_probability::adjusted): New. * tree-inline.c (copy_bb): Update to new speculative call API; fix updating of profile. * value-prof.c (gimple_ic_transform): Rename to ... (dump_ic_profile): ... this one; update dumping. (stream_in_histogram_value): Fix formating. (gimple_value_profile_transformations): Update. 2020-01-28 H.J. Lu PR target/91461 * config/i386/i386.md (*movoi_internal_avx): Remove TARGET_SSE_TYPELESS_STORES check. (*movti_internal): Prefer TARGET_AVX over TARGET_SSE_TYPELESS_STORES. (*movtf_internal): Likewise. * config/i386/sse.md (mov_internal): Prefer TARGET_AVX over TARGET_SSE_TYPELESS_STORES. Remove " == 16" check from TARGET_SSE_TYPELESS_STORES. 2020-01-28 David Malcolm * diagnostic-core.h (warning_at): Rename overload to... (warning_meta): ...this. (emit_diagnostic_valist): Delete decl of overload taking diagnostic_metadata. * diagnostic.c (emit_diagnostic_valist): Likewise for defn. (warning_at): Rename overload taking diagnostic_metadata to... (warning_meta): ...this. 2020-01-28 Richard Biener PR tree-optimization/93439 * tree-parloops.c (create_loop_fn): Move clique bookkeeping... * tree-cfg.c (move_sese_region_to_fn): ... here. (verify_types_in_gimple_reference): Verify used cliques are tracked. 2020-01-28 H.J. Lu PR target/91399 * config/i386/i386-options.c (set_ix86_tune_features): Add an argument of a pointer to struct gcc_options and pass it to parse_mtune_ctrl_str. (ix86_function_specific_restore): Pass opts to set_ix86_tune_features. (ix86_option_override_internal): Likewise. (parse_mtune_ctrl_str): Add an argument of a pointer to struct gcc_options and use it for x_ix86_tune_ctrl_string. 2020-01-28 Richard Sandiford PR rtl-optimization/87763 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract simplification to handle subregs as well as bare regs. * config/i386/i386.md (*testqi_ext_3): Match QI extracts too. 2020-01-28 Richard Sandiford * tree-vect-loop.c (vectorizable_reduction): Fail gracefully for reduction chains that (now) include a call. 2020-01-28 Richard Sandiford PR tree-optimization/92822 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling out the don't-care elements of a vector whose significant elements are duplicates, make the don't-care elements duplicates too. 2020-01-28 Richard Sandiford PR tree-optimization/93434 * tree-predcom.c (split_data_refs_to_components): Record which components have had aliasing loads removed. Prevent store-store commoning for all such components. 2020-01-28 Jakub Jelinek PR target/93418 * config/i386/i386.c (ix86_fold_builtin) : If mask is not -1 or is_vshift is true, use new_vector with number of elts npatterns rather than new_unary_operation. PR tree-optimization/93454 * gimple-fold.c (fold_array_ctor_reference): Perform elt_size.to_uhwi () just once, instead of calling it in every iteration. Punt if that value is above size of the temporary buffer. Decrease third native_encode_expr argument when bufoff + elt_sz is above size of buf. 2020-01-27 Joseph Myers * config/mips/mips.c (mips_declare_object_name) [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object. 2020-01-27 Martin Liska PR gcov-profile/93403 * tree-profile.c (gimple_init_gcov_profiler): Generate both __gcov_indirect_call_profiler_v4 and __gcov_indirect_call_profiler_v4_atomic. 2020-01-27 Richard Sandiford PR target/92822 * config/aarch64/aarch64-simd.md (aarch64_get_half): New expander. (@aarch64_split_simd_mov): Use it. (aarch64_simd_mov_from_low): Add a GPR alternative. Leave the vec_extract patterns to handle 2-element vectors. (aarch64_simd_mov_from_high): Likewise. (vec_extract): New expander. (vec_extractv2dfv1df): Likewise. 2020-01-27 Richard Sandiford * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match jump conditions for *compare_condjump. 2020-01-27 David Malcolm PR analyzer/93276 * digraph.cc (test_edge::test_edge): Specify template for base class initializer. 2020-01-27 Claudiu Zissulescu * config/arc/arc.c (arc_rtx_costs): Update mul64 cost. 2020-01-27 Claudiu Zissulescu * config/arc/arc-protos.h (gen_mlo): Remove. (gen_mhi): Likewise. * config/arc/arc.c (AUX_MULHI): Define. (arc_must_save_reister): Special handling for r58/59. (arc_compute_frame_size): Consider mlo/mhi registers. (arc_save_callee_saves): Emit fp/sp move only when emit_move paramter is true. (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from mlo/mhi name selection. (arc_restore_callee_saves): Don't early restore blink when ISR. (arc_expand_prologue): Add mlo/mhi saving. (arc_expand_epilogue): Add mlo/mhi restoring. (gen_mlo): Remove. (gen_mhi): Remove. * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register numbering when MUL64 option is used. (DWARF2_FRAME_REG_OUT): Define. * config/arc/arc.md (arc600_stall): New pattern. (VUNSPEC_ARC_ARC600_STALL): Define. (mulsi64): Use correct mlo/mhi registers. (mulsi_600): Clean it up. * config/arc/predicates.md (mlo_operand): Remove any dependency on TARGET_BIG_ENDIAN. (mhi_operand): Likewise. 2020-01-27 Claudiu Zissulescu Petro Karashchenko * config/arc/arc.c (arc_is_uncached_mem_p): Check struct attributes if needed. (prepare_move_operands): Generate special unspec instruction for direct access. (arc_isuncached_mem_p): Propagate uncached attribute to each structure member. * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define. (VUNSPEC_ARC_STDI): Likewise. (ALLI): New mode iterator. (mALLI): New mode attribute. (lddi): New instruction pattern. (stdi): Likewise. (stdidi_split): Split instruction for architectures which are not supporting ll64 option. (lddidi_split): Likewise. 2020-01-27 Richard Sandiford PR rtl-optimization/92989 * lra-lives.c (process_bb_lives): Update the live-in set before processing additional clobbers. 2020-01-27 Richard Sandiford PR rtl-optimization/93170 * cselib.c (cselib_invalidate_regno_val): New function, split out from... (cselib_invalidate_regno): ...here. (cselib_invalidated_by_call_p): New function. (cselib_process_insn): Iterate over all the hard-register entries in REG_VALUES and invalidate any that cross call-clobbered registers. 2020-01-27 Richard Sandiford * dojump.c (split_comparison): Use HONOR_NANS rather than HONOR_SNANS when splitting LTGT. 2020-01-27 Martin Liska PR driver/91220 * opts.c (print_filtered_help): Exclude language-specific options from --help=common unless enabled in all FEs. 2020-01-27 Martin Liska * opts.c (print_help): Exclude params from all except --help=param. 2020-01-27 Martin Liska PR target/93274 * config/i386/i386-features.c (make_resolver_func): Align the code with ppc64 target implementation. Do not generate a unique name for resolver function. 2020-01-27 Richard Biener PR tree-optimization/93397 * tree-vect-slp.c (vect_analyze_slp_instance): Delay converted reduction chain SLP graph adjustment. 2020-01-26 Marek Polacek PR sanitizer/93436 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on null DECL_NAME. 2020-01-26 Jason Merrill PR c++/92601 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING of complete types. 2020-01-26 Darius Galis * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint (rx_setmem): Likewise. 2020-01-26 Jakub Jelinek PR target/93412 * config/i386/i386.md (*addv4_doubleword, *subv4_doubleword): Use nonimmediate_operand instead of x86_64_hilo_general_operand and drop from constraint of last operand. PR target/93430 * config/i386/sse.md (*avx_vperm_broadcast_): Disallow for TARGET_AVX2 and V4DFmode not in the split condition, but in the pattern condition, though allow { 0, 0, 0, 0 } broadcast always. 2020-01-25 Feng Xue PR ipa/93166 * ipa-cp.c (get_info_about_necessary_edges): Remove value check assertion. 2020-01-24 Jeff Law PR tree-optimization/92788 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX not EDGE_ABNORMAL. 2020-01-24 Jakub Jelinek PR target/93395 * config/i386/sse.md (*avx_vperm_broadcast_v4sf, *avx_vperm_broadcast_, _vpermil, *_vpermilp): Move before avx2_perm/avx512f_perm. PR target/93376 * simplify-rtx.c (simplify_const_unary_operation, simplify_const_binary_operation): Punt for mode precision above MAX_BITSIZE_MODE_ANY_INT. 2020-01-24 Andrew Pinski * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change alu.shift_reg to 0. 2020-01-24 Jeff Law PR target/13721 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg for REGs. Call output_operand_lossage to get more reasonable diagnostics. 2020-01-24 Andrew Stubbs * config/gcn/gcn-valu.md (vec_cmpdi): Use gcn_fp_compare_operator. (vec_cmpudi): Use gcn_compare_operator. (vec_cmpv64qidi): Use gcn_compare_operator. (vec_cmpdi_exec): Use gcn_fp_compare_operator. (vec_cmpudi_exec): Use gcn_compare_operator. (vec_cmpv64qidi_exec): Use gcn_compare_operator. (vec_cmpdi_dup): Use gcn_fp_compare_operator. (vec_cmpdi_dup_exec): Use gcn_fp_compare_operator. (vcond): Use gcn_fp_compare_operator. (vcond_exec): Use gcn_fp_compare_operator. (vcondu): Use gcn_fp_compare_operator. (vcondu_exec): Use gcn_fp_compare_operator. 2020-01-24 Maciej W. Rozycki * doc/install.texi (Cross-Compiler-Specific Options): Document `--with-toolexeclibdir' option. 2020-01-24 Hans-Peter Nilsson * target.def (flags_regnum): Also mention effect on delay slot filling. * doc/tm.texi: Regenerate. 2020-01-23 Jeff Law PR translation/90162 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text. 2020-01-23 Mikael Tillenius PR target/92269 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of profiling label 2020-01-23 Jakub Jelinek PR rtl-optimization/93402 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust USE insns. 2020-01-23 Dragan Mladjenovic * config.in: Regenerated. * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1 for TARGET_LIBC_GNUSTACK. * configure: Regenerated. * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is found to be 2.31 or greater. 2020-01-23 Dragan Mladjenovic * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to TARGET_SOFT_FLOAT. * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ... (mips_asm_file_end): New function. Delegate to file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true. * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0. 2020-01-23 Jakub Jelinek PR target/93376 * config/i386/i386-modes.def (POImode): New mode. (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160. * config/i386/i386.md (DPWI): New mode attribute. (addv4, subv4): Use instead of . (QWI): Rename to... (QPWI): ... this. Use POI instead of OI for TImode. (*addv4_doubleword, *addv4_doubleword_1, *subv4_doubleword, *subv4_doubleword_1): Use instead of . 2020-01-23 Richard Sandiford PR target/93341 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New unspec. (speculation_tracker_rev): New pattern. * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation): Use speculation_tracker_rev to track the inverse condition. 2020-01-23 Richard Biener PR tree-optimization/93381 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take alias-set of the def as argument and record the first one. (vn_walk_cb_data::first_set): New member. (vn_reference_lookup_3): Pass the alias-set of the current def to push_partial_def. Fix alias-set used in the aggregate copy case. (vn_reference_lookup): Consistently set *last_vuse_ptr. * real.c (clear_significand_below): Fix out-of-bound access. 2020-01-23 Jakub Jelinek PR target/93346 * config/i386/i386.md (*bmi2_bzhi_3_2, *bmi2_bzhi_3_3): New define_insn patterns. 2020-01-23 Richard Sandiford * doc/sourcebuild.texi (check-function-bodies): Add an optional target/xfail selector. 2020-01-23 Richard Sandiford PR rtl-optimization/93124 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to bare USE and CLOBBER insns. 2020-01-22 Andrew Pinski * config/arc/arc.c (output_short_suffix): Check insn for nullness. 2020-01-22 David Malcolm PR analyzer/93307 * gdbinit.in (break-on-saved-diagnostic): Update for move of diagnostic_manager into "ana" namespace. * selftest-run-tests.c (selftest::run_tests): Update for move of selftest::run_analyzer_selftests to ana::selftest::run_analyzer_selftests. 2020-01-22 Richard Sandiford * cfgexpand.c (union_stack_vars): Update the size. 2020-01-22 Richard Biener PR tree-optimization/93381 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting throughout, handle all conversions the same. 2020-01-22 Jakub Jelinek PR target/93335 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate predicate, not whenever it is CONST_INT. Otherwise, force_reg it. Call force_reg on high_in2 unconditionally. 2020-01-22 Martin Liska PR tree-optimization/92924 * profile.c (compute_value_histograms): Divide all counter values. 2020-01-22 Jakub Jelinek PR target/91298 * output.h (assemble_name_resolve): Declare. * varasm.c (assemble_name_resolve): New function. (assemble_name): Use it. * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define. 2020-01-22 Joseph Myers * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to update_web_docs_git instead of update_web_docs_svn. 2020-01-21 Andrew Pinski PR target/9311 * config/aarch64/aarch64.md (tlsgd_small_): Have operand 0 as PTR mode. Have operand 1 as being modeless, it can be P mode. (*tlsgd_small_): Likewise. * config/aarch64/aarch64.c (aarch64_load_symref_appropriately) : Call gen_tlsgd_small_* with a ptr_mode register. Convert that register back to dest using convert_mode. 2020-01-21 Jim Wilson * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL instead of XINT. 2020-01-21 H.J. Lu Uros Bizjak PR target/93319 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode with ptr_mode. (legitimize_tls_address): Do GNU2 TLS address computation in ptr_mode and zero-extend result to Pmode. * config/i386/i386.md (@tls_dynamic_gnu2_64_): Replace :P with :PTR and Pmode with ptr_mode. (*tls_dynamic_gnu2_lea_64_): Likewise. (*tls_dynamic_gnu2_call_64_): Likewise. (*tls_dynamic_gnu2_combine_64_): Likewise. 2020-01-21 Jakub Jelinek PR target/93333 * config/riscv/riscv.c (riscv_rtx_costs) : Verify the last two operands are CONST_INT_P before using them as such. 2020-01-21 Richard Sandiford * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name to get the integer element types. 2020-01-21 Richard Sandiford * config/aarch64/aarch64-sve-builtins.h (function_expander::convert_to_pmode): Declare. * config/aarch64/aarch64-sve-builtins.cc (function_expander::convert_to_pmode): New function. (function_expander::get_contiguous_base): Use it. (function_expander::prepare_gather_address_operands): Likewise. * config/aarch64/aarch64-sve-builtins-sve2.cc (svwhilerw_svwhilewr_impl::expand): Likewise. 2020-01-21 Szabolcs Nagy PR target/92424 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set cfun->machine->label_is_assembled. (aarch64_print_patchable_function_entry): New. (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define. * config/aarch64/aarch64.h (struct machine_function): New field, label_is_assembled. 2020-01-21 David Malcolm PR ipa/93315 * ipa-profile.c (ipa_profile): Delete call_sums and set it to NULL on exit. 2020-01-18 Jan Hubicka PR lto/93318 * cgraph.c (cgraph_edge::resolve_speculation, cgraph_edge::redirect_call_stmt_to_callee): Fix update of call_stmt_site_hash. 2020-01-21 Martin Liska * config/rs6000/rs6000.c (common_mode_defined): Remove unused variable. 2020-01-21 Richard Biener PR tree-optimization/92328 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve type when value-numbering same-sized store by inserting a VIEW_CONVERT_EXPR. (eliminate_dom_walker::eliminate_stmt): When eliminating a redundant store handle bit-reinterpretation of the same value. 2020-01-21 Andrew Pinski PR tree-opt/93321 * tree-into-ssa.c (prepare_block_for_update_1): Split out from ... (prepare_block_for_update): This. Use a worklist instead of recursing. 2020-01-21 Mihail-Calin Ionescu * gcc/config/arm/arm.c (clear_operation_p): Initialise last_regno, skip first iteration based on the first_set value and use ints instead of the unnecessary HOST_WIDE_INTs. 2020-01-21 Jakub Jelinek PR target/93073 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for compare_mode other than SFmode or DFmode. 2020-01-21 Kito Cheng PR target/93304 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New. * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New. * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined. 2020-01-20 Wilco Dijkstra * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4. 2020-01-20 Andrew Pinski PR middle-end/93242 * targhooks.c (default_print_patchable_function_entry): Use output_asm_insn to emit the nop instruction. 2020-01-20 Fangrui Song PR middle-end/93194 * targhooks.c (default_print_patchable_function_entry): Align to POINTER_SIZE. 2020-01-20 H.J. Lu PR target/93319 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode. * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ... (@tls_dynamic_gnu2_64_): This. Replace DI with P. (*tls_dynamic_gnu2_lea_64): Renamed to ... (*tls_dynamic_gnu2_lea_64_): This. Replace DI with P. Remove the {q} suffix from lea. (*tls_dynamic_gnu2_call_64): Renamed to ... (*tls_dynamic_gnu2_call_64_): This. Replace DI with P. (*tls_dynamic_gnu2_combine_64): Renamed to ... (*tls_dynamic_gnu2_combine_64_): This. Replace DI with P. Pass Pmode to gen_tls_dynamic_gnu2_64. 2020-01-20 Wilco Dijkstra * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1. 2020-01-20 Richard Sandiford * config/aarch64/aarch64-sve-builtins-base.cc (svld1ro_impl::memory_vector_mode): Remove parameter name. 2020-01-20 Richard Biener PR debug/92763 * dwarf2out.c (prune_unused_types): Unconditionally mark called function DIEs. 2020-01-20 Martin Liska PR tree-optimization/93199 * tree-eh.c (struct leh_state): Add new field outer_non_cleanup. (cleanup_is_dead_in): Pass leh_state instead of eh_region. Add a checking that state->outer_non_cleanup points to outer non-clean up region. (lower_try_finally): Record outer_non_cleanup for this_state. (lower_catch): Likewise. (lower_eh_filter): Likewise. (lower_eh_must_not_throw): Likewise. (lower_cleanup): Likewise. 2020-01-20 Richard Biener PR tree-optimization/93094 * tree-vectorizer.h (vect_loop_versioning): Adjust. (vect_transform_loop): Likewise. * tree-vectorizer.c (try_vectorize_loop_1): Pass down loop_vectorized_call to vect_transform_loop. * tree-vect-loop.c (vect_transform_loop): Pass down loop_vectorized_call to vect_loop_versioning. * tree-vect-loop-manip.c (vect_loop_versioning): Use the earlier discovered loop_vectorized_call. 2020-01-19 Eric S. Raymond * doc/contribute.texi: Update for SVN -> Git transition. * doc/install.texi: Likewise. 2020-01-18 Jan Hubicka PR lto/93318 * cgraph.c (cgraph_edge::make_speculative): Increase number of speculative targets. (verify_speculative_call): New function (cgraph_node::verify_node): Use it. * ipa-profile.c (ipa_profile): Fix formating; do not set number of speculations. 2020-01-18 Jan Hubicka PR lto/93318 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting. (cgraph_edge::make_direct): Remove all indirect targets. (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct.. (cgraph_node::verify_node): Verify that only one call_stmt or lto_stmt_uid is set. * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or lto_stmt_uid. * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt. (lto_output_ref): Simplify streaming of stmt. * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid. 2020-01-18 Tamar Christina * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode): Mark parameter unused. 2020-01-18 Hans-Peter Nilsson * config.gcc : Add crisv32-*-* and cris-*-linux* 2019-01-18 Gerald Pfeifer * varpool.c (ctor_useable_for_folding_p): Fix grammar. 2020-01-18 Iain Sandoe * Makefile.in: Add coroutine-passes.o. * builtin-types.def (BT_CONST_SIZE): New. (BT_FN_BOOL_PTR): New. (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New. * builtins.def (DEF_COROUTINE_BUILTIN): New. * coroutine-builtins.def: New file. * coroutine-passes.cc: New file. * function.h (struct GTY function): Add a bit to indicate that the function is a coroutine component. * internal-fn.c (expand_CO_FRAME): New. (expand_CO_YIELD): New. (expand_CO_SUSPN): New. (expand_CO_ACTOR): New. * internal-fn.def (CO_ACTOR): New. (CO_YIELD): New. (CO_SUSPN): New. (CO_FRAME): New. * passes.def: Add pass_coroutine_lower_builtins, pass_coroutine_early_expand_ifns. * tree-pass.h (make_pass_coroutine_lower_builtins): New. (make_pass_coroutine_early_expand_ifns): New. * doc/invoke.texi: Document the fcoroutines command line switch. 2020-01-18 Jakub Jelinek * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable. PR target/93312 * config/arm/arm.c (clear_operation_p): Don't use REGNO until after checking the argument is a REG. Don't use REGNO (reg) again to set last_regno, reuse regno variable instead. 2020-01-17 David Malcolm * doc/analyzer.texi (Limitations): Add note about NaN. 2020-01-17 Mihail-Calin Ionescu Sudakshina Das * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg and valid immediate. (ashrdi3): Generate thumb2_asrl for both reg and valid immediate. (lshrdi3): Generate thumb2_lsrl for valid immediates. * config/arm/constraints.md (Pg): New. * config/arm/predicates.md (long_shift_imm): New. (arm_reg_or_long_shift_imm): Likewise. * config/arm/thumb2.md (thumb2_asrl): New immediate alternative. (thumb2_lsll): Likewise. (thumb2_lsrl): New. 2020-01-17 Mihail-Calin Ionescu Sudakshina Das * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE. (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE. * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd register pairs for doubleword quantities for ARMv8.1M-Mainline. * config/arm/thumb2.md (thumb2_asrl): New. (thumb2_lsll): Likewise. 2020-01-17 Jakub Jelinek * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove unused variable. 2020-01-17 Alexander Monakov * gdbinit.in (help-gcc-hooks): New command. (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc, pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update documentation. 2020-01-17 Matthew Malcomson * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro): Use the correct target macro. 2020-01-17 Matthew Malcomson * config/aarch64/aarch64-protos.h (aarch64_sve_ld1ro_operand_p): New. * config/aarch64/aarch64-sve-builtins-base.cc (class load_replicate): New. (class svld1ro_impl): New. (class svld1rq_impl): Change to inherit from load_replicate. (svld1ro): New sve intrinsic function base. * config/aarch64/aarch64-sve-builtins-base.def (svld1ro): New DEF_SVE_FUNCTION. * config/aarch64/aarch64-sve-builtins-base.h (svld1ro): New decl. * config/aarch64/aarch64-sve-builtins.cc (function_expander::add_mem_operand): Modify assert to allow OImode. * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro): New pattern. * config/aarch64/aarch64.c (aarch64_sve_ld1rq_operand_p): Implement in terms of ... (aarch64_sve_ld1rq_ld1ro_operand_p): This. (aarch64_sve_ld1ro_operand_p): New. * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec. * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New. * config/aarch64/predicates.md (aarch64_sve_ld1ro_operand_{b,h,w,d}): New. 2020-01-17 Matthew Malcomson * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64): Introduce this ACLE specified predefined macro. * config/aarch64/aarch64-option-extensions.def (f64mm): New. (fp): Disabling this disables f64mm. (simd): Disabling this disables f64mm. (fp16): Disabling this disables f64mm. (sve): Disabling this disables f64mm. * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New. (AARCH64_ISA_F64MM): New. (TARGET_F64MM): New. * doc/invoke.texi (f64mm): Document new option. 2020-01-17 Wilco Dijkstra * config/aarch64/aarch64.c (generic_tunings): Add branch fusion. (neoversen1_tunings): Likewise. 2020-01-17 Wilco Dijkstra PR target/92692 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap) Add assert to ensure prolog has been emitted. (aarch64_split_atomic_op): Likewise. * config/aarch64/atomics.md (aarch64_compare_and_swap) Use epilogue_completed rather than reload_completed. (aarch64_atomic_exchange): Likewise. (aarch64_atomic_): Likewise. (atomic_nand): Likewise. (aarch64_atomic_fetch_): Likewise. (atomic_fetch_nand): Likewise. (aarch64_atomic__fetch): Likewise. (atomic_nand_fetch): Likewise. 2020-01-17 Richard Sandiford PR target/93133 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false for FP modes. (REVERSE_CONDITION): Delete. * config/aarch64/iterators.md (CC_ONLY): New mode iterator. (CCFP_CCFPE): Likewise. (e): New mode attribute. * config/aarch64/aarch64.md (ccmp): Rename to... (@ccmp): ...this, using CC_ONLY instead of CC. (fccmp, fccmpe): Merge into... (@ccmp): ...this combined pattern. (@ccmp_rev): New pattern. (@ccmp_rev): Likewise. * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update name of generator from gen_ccmpdi to gen_ccmpccdi. (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse the previous comparison but aren't able to, use the new ccmp_rev patterns instead. 2020-01-17 Richard Sandiford * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather than testing directly for INTEGER_CST. (gimplify_target_expr, gimplify_omp_depend): Likewise. 2020-01-17 Jakub Jelinek PR tree-optimization/93292 * tree-vect-stmts.c (vectorizable_comparison): Punt also if get_vectype_for_scalar_type returns NULL. 2020-01-16 Jan Hubicka * params.opt (-param=max-predicted-iterations): Increase range from 0. * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations. 2020-01-16 Jan Hubicka * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of dump. * params.opt: (max-predicted-iterations): Set bounds. * predict.c (real_almost_one, real_br_prob_base, real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove. (propagate_freq): Add max_cyclic_prob parameter; cap cyclic probabilities; do not truncate to reg_br_prob_bases. (estimate_loops_at_level): Pass max_cyclic_prob. (estimate_loops): Compute max_cyclic_prob. (estimate_bb_frequencies): Do not initialize real_*; update calculation of back edge prob. * profile-count.c (profile_probability::to_sreal): New. * profile-count.h (class sreal): Move up in file. (profile_probability::to_sreal): Declare. 2020-01-16 Stam Markianos-Wright * config/arm/arm.c (arm_invalid_conversion): New function for target hook. (arm_invalid_unary_op): New function for target hook. (arm_invalid_binary_op): New function for target hook. 2020-01-16 Stam Markianos-Wright * config.gcc: Add arm_bf16.h. * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment. (arm_simd_builtin_std_type): Add BFmode. (arm_init_simd_builtin_types): Define element types for vector types. (arm_init_bf16_types): New function. (arm_init_builtins): Add arm_init_bf16_types function call. * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes. * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF. * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode. (arm_hard_regno_mode_ok): Add BFmode and tidy up statements. (arm_vector_mode_supported_p): Add V4BF, V8BF. (arm_mangle_type): Add __bf16. * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node, arm_bf16_ptr_type_node. * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and define_split between ARM registers. * config/arm/arm_bf16.h: New file. * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types. * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New. (VQXMOV): Add V8BF. * config/arm/neon.md: Add BF vector types to movhf NEON move patterns. * config/arm/vfp.md: Add BFmode to movhf patterns. 2020-01-16 Mihail Ionescu Andre Vieira * config/arm/arm-cpus.in (mve, mve_float): New features. (dsp, mve, mve.fp): New options. * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define. * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M. * doc/invoke.texi: Document the armv8.1-m mve and dps options. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to Armv8-M Mainline. * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove error for using -mcmse when targeting Armv8.1-M Mainline. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm.md (nonsecure_call_internal): Do not force memory address in r4 when targeting Armv8.1-M Mainline. (nonsecure_call_value_internal): Likewise. * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address a register match_operand again. Emit BLXNS when targeting Armv8.1-M Mainline. (nonsecure_call_value_reg_thumb2): Likewise. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early. (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear variable as true when floating-point ABI is not hard. Replace check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear. Generate VLSTM and VLLDM instruction respectively before and after a function call to cmse_nonsecure_call function. * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec. (VUNSPEC_VLLDM): Likewise. * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn. (lazy_load_multiple_insn): Likewise. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm.c (vfp_emit_fstmd): Declare early. (arm_emit_vfp_multi_reg_pop): Likewise. (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and restore callee-saved VFP registers. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early. (cmse_nonsecure_call_clear_caller_saved): Rename into ... (cmse_nonsecure_call_inline_register_clear): This. Save and clear callee-saved GPRs as well as clear ip register before doing a nonsecure call then restore callee-saved GPRs after it when targeting Armv8.1-M Mainline. (arm_reorg): Adapt to function rename. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm-protos.h (clear_operation_p): Adapt prototype. * config/arm/arm.c (clear_operation_p): Extend to be able to check a clear_vfp_multiple pattern based on a new vfp parameter. (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when targeting Armv8.1-M Mainline. (cmse_nonsecure_entry_clear_before_return): Clear VFP registers unconditionally when targeting Armv8.1-M Mainline architecture. Check whether VFP registers are available before looking call_used_regs for a VFP register. * config/arm/predicates.md (clear_multiple_operation): Adapt to change of prototype of clear_operation_p. (clear_vfp_multiple_operation): New predicate. * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec. * config/arm/vfp.md (clear_vfp_multiple): New define_insn. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm-protos.h (clear_operation_p): Declare. * config/arm/arm.c (clear_operation_p): New function. (cmse_clear_registers): Generate clear_multiple instruction pattern if targeting Armv8.1-M Mainline or successor. (output_return_instruction): Only output APSR register clearing if Armv8.1-M Mainline instructions not available. (thumb_exit): Likewise. * config/arm/predicates.md (clear_multiple_operation): New predicate. * config/arm/thumb2.md (clear_apsr): New define_insn. (clear_multiple): Likewise. * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm.c (fp_sysreg_names): Declare and define. (use_return_insn): Also return false for Armv8.1-M Mainline. (output_return_instruction): Skip FPSCR clearing if Armv8.1-M Mainline instructions are available. (arm_compute_frame_layout): Allocate space in frame for FPCXTNS when targeting Armv8.1-M Mainline Security Extensions. (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M Mainline entry function. (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if targeting Armv8.1-M Mainline or successor. (arm_expand_epilogue): Fix indentation of caller-saved register clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline entry function. * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro. (FP_SYSREGS): Likewise. (enum vfp_sysregs_encoding): Define enum. (fp_sysreg_names): Declare. * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec. * config/arm/vfp.md (push_fpsysreg_insn): New define_insn. (pop_fpsysreg_insn): Likewise. 2020-01-16 Mihail-Calin Ionescu Thomas Preud'homme * config/arm/arm-cpus.in (armv8_1m_main): New feature. (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k, ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve, ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a, ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent. (ARMv8_1m_main): New feature group. (armv8.1-m.main): New architecture. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize. (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main. (arm_options_perform_arch_sanity_checks): Error out when targeting Armv8.1-M Mainline Security Extensions. * config/arm/arm.h (arm_arch8_1m_main): Declare. 2020-01-16 Stam Markianos-Wright * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot, aarch64_bfdot_lane, aarch64_bfdot_laneq): New. * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane, aarch64_bfdot_laneq): New. * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32, vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32, vbfdotq_laneq_f32): New. * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype, VBFMLA_W, VBF): New. (isquadop): Add V4BF, V8BF. 2020-01-16 Stam Markianos-Wright * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers): New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS, TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP. (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX. (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index. * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane, usdot_laneq, sudot_lane,sudot_laneq): New. * config/aarch64/aarch64-simd.md (aarch64_usdot): New. (aarch64_dot_lane): New. * config/aarch64/arm_neon.h (vusdot_s32): New. (vusdotq_s32): New. (vusdot_lane_s32): New. (vsudot_lane_s32): New. * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator. (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs. 2020-01-16 Martin Liska * value-prof.c (dump_histogram_value): Fix obvious spacing issue. 2020-01-16 Andrew Pinski * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for !storage_order_barrier_p. 2020-01-16 Andrew Pinski * sched-int.h (_dep): Add unused bit-field field for the padding. * sched-deps.c (init_dep_1): Init unused field. 2020-01-16 Andrew Pinski * optabs.h (create_expand_operand): Initialize target field also. 2020-01-16 Andre Vieira PR tree-optimization/92429 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter. * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to control folding. * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing tree. 2020-01-16 Richard Sandiford * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply aarch64_sve_int_mode to each mode. 2020-01-15 David Malcolm * doc/analyzer.texi (Overview): Add note about -fdump-ipa-analyzer. 2020-01-15 Wilco Dijkstra PR tree-optimization/93231 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check input_type is unsigned. Use tree_to_shwi for shift constant. Check CST_STRING element size is CHAR_TYPE_SIZE bits. (simplify_count_trailing_zeroes): Add test to handle known non-zero inputs more efficiently. 2020-01-15 Uroš Bizjak * config/i386/i386.md (*movsf_internal): Do not require SSE2 ISA for alternatives 14 and 15. 2020-01-15 Richard Biener PR middle-end/93273 * tree-eh.c (sink_clobbers): If we already visited the destination block do not defer insertion. (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for the purpose of defered insertion. 2020-01-15 Jakub Jelinek * BASE-VER: Bump to 10.0.1. 2020-01-15 Richard Sandiford PR tree-optimization/93247 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access type of the stmt that we're going to vectorize. 2020-01-15 Richard Sandiford * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent type from the lhs. 2020-01-15 Martin Liska * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow 2 calls of streamer_read_hwi in a function call. 2020-01-15 Richard Biener * alias.c (record_alias_subset): Avoid redundant work when subset is already recorded. 2020-01-14 David Malcolm * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of the analyzer options provide CWE identifiers. 2020-01-14 David Malcolm * tree-diagnostic-path.cc (path_summary::event_range::print): When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers using get_pure_location. 2020-01-15 Jakub Jelinek PR tree-optimization/93262 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins, perform head trimming only if the last argument is constant, either all ones, or larger or equal to head trim, in the latter case decrease the last argument by head_trim. PR tree-optimization/93249 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h. (maybe_trim_memstar_call): Move head_trim and tail_trim vars to function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't perform head trim unless we can prove there are no '\0' chars from the source among the first head_trim chars. 2020-01-14 David Malcolm * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o. 2020-01-15 Jakub Jelinek PR target/93009 * config/i386/sse.md (*fma_fmadd__bcst_1, *fma_fmsub__bcst_1, *fma_fnmadd__bcst_1, *fma_fnmsub__bcst_1): Use just a single alternative instead of two, make operands 1 and 2 commutative. 2020-01-14 Jan Hubicka PR lto/91576 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and TYPE_MODE. 2020-01-14 David Malcolm * Makefile.in (lang_opt_files): Add analyzer.opt. (ANALYZER_OBJS): New. (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o, tristate.o and ANALYZER_OBJS. (TEXI_GCCINT_FILES): Add analyzer.texi. * common.opt (-fanalyzer): New driver option. * config.in: Regenerate. * configure: Regenerate. * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option. (gccdepdir): Also create depdir for "analyzer" subdir. * digraph.cc: New file. * digraph.h: New file. * doc/analyzer.texi: New file. * doc/gccint.texi ("Static Analyzer") New menu item. (analyzer.texi): Include it. * doc/invoke.texi ("Static Analyzer Options"): New list and new section. ("Warning Options"): Add static analysis warnings to the list. (-Wno-analyzer-double-fclose): New option. (-Wno-analyzer-double-free): New option. (-Wno-analyzer-exposure-through-output-file): New option. (-Wno-analyzer-file-leak): New option. (-Wno-analyzer-free-of-non-heap): New option. (-Wno-analyzer-malloc-leak): New option. (-Wno-analyzer-possible-null-argument): New option. (-Wno-analyzer-possible-null-dereference): New option. (-Wno-analyzer-null-argument): New option. (-Wno-analyzer-null-dereference): New option. (-Wno-analyzer-stale-setjmp-buffer): New option. (-Wno-analyzer-tainted-array-index): New option. (-Wno-analyzer-use-after-free): New option. (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option. (-Wno-analyzer-use-of-uninitialized-value): New option. (-Wanalyzer-too-complex): New option. (-fanalyzer-call-summaries): New warning. (-fanalyzer-checker=): New warning. (-fanalyzer-fine-grained): New warning. (-fno-analyzer-state-merge): New warning. (-fno-analyzer-state-purge): New warning. (-fanalyzer-transitivity): New warning. (-fanalyzer-verbose-edges): New warning. (-fanalyzer-verbose-state-changes): New warning. (-fanalyzer-verbosity=): New warning. (-fdump-analyzer): New warning. (-fdump-analyzer-callgraph): New warning. (-fdump-analyzer-exploded-graph): New warning. (-fdump-analyzer-exploded-nodes): New warning. (-fdump-analyzer-exploded-nodes-2): New warning. (-fdump-analyzer-exploded-nodes-3): New warning. (-fdump-analyzer-supergraph): New warning. * doc/sourcebuild.texi (dg-require-dot): New. (dg-check-dot): New. * gdbinit.in (break-on-saved-diagnostic): New command. * graphviz.cc: New file. * graphviz.h: New file. * ordered-hash-map-tests.cc: New file. * ordered-hash-map.h: New file. * passes.def (pass_analyzer): Add before pass_ipa_whole_program_visibility. * selftest-run-tests.c (selftest::run_tests): Call selftest::ordered_hash_map_tests_cc_tests. * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New decl. * shortest-paths.h: New file. * timevar.def (TV_ANALYZER): New timevar. (TV_ANALYZER_SUPERGRAPH): Likewise. (TV_ANALYZER_STATE_PURGE): Likewise. (TV_ANALYZER_PLAN): Likewise. (TV_ANALYZER_SCC): Likewise. (TV_ANALYZER_WORKLIST): Likewise. (TV_ANALYZER_DUMP): Likewise. (TV_ANALYZER_DIAGNOSTICS): Likewise. (TV_ANALYZER_SHORTEST_PATHS): Likewise. * tree-pass.h (make_pass_analyzer): New decl. * tristate.cc: New file. * tristate.h: New file. 2020-01-14 Uroš Bizjak PR target/93254 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for alternatives 9 and 10. 2020-01-14 David Malcolm * attribs.c (excl_hash_traits::empty_zero_p): New static constant. * gcov.c (function_start_pair_hash::empty_zero_p): Likewise. * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise. * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest. (selftest::hash_map_tests_c_tests): Call it. * hash-map-traits.h (simple_hashmap_traits::empty_zero_p): New static constant, using the value of = H::empty_zero_p. (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value from default_hash_traits . * hash-map.h (hash_map::empty_zero_p): Likewise, using the value from Traits. * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise. * hash-table.h (hash_table::alloc_entries): Guard the loop of calls to mark_empty with !Descriptor::empty_zero_p. (hash_table::empty_slow): Conditionalize the memset call with a check that Descriptor::empty_zero_p; otherwise, loop through the entries calling mark_empty on them. * hash-traits.h (int_hash::empty_zero_p): New static constant. (pointer_hash::empty_zero_p): Likewise. (pair_hash::empty_zero_p): Likewise. * ipa-devirt.c (default_hash_traits ::empty_zero_p): Likewise. * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise. (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise. * profile.c (location_triplet_hash::empty_zero_p): Likewise. * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise. (sanopt_tree_couple_hash::empty_zero_p): Likewise. * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise. * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise. * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise. * tree-vectorizer.h (default_hash_traits::empty_zero_p): Likewise. 2020-01-14 Kewen Lin * cfgloopanal.c (average_num_loop_insns): Free bbs when early return, fix typo on return value. 2020-01-14 Xiong Hu Luo PR ipa/69678 * cgraph.c (symbol_table::create_edge): Init speculative_id and target_prob. (cgraph_edge::make_speculative): Add param for setting speculative_id and target_prob. (cgraph_edge::speculative_call_info): Update comments and find reference by speculative_id for multiple indirect targets. (cgraph_edge::resolve_speculation): Decrease the speculations for indirect edge, drop it's speculative if not direct target left. Update comments. (cgraph_edge::redirect_call_stmt_to_callee): Likewise. (cgraph_node::dump): Print num_speculative_call_targets. (cgraph_node::verify_node): Don't report error if speculative edge not include statement. (cgraph_edge::num_speculative_call_targets_p): New function. * cgraph.h (int common_target_id): Remove. (int common_target_probability): Remove. (num_speculative_call_targets): New variable. (make_speculative): Add param for setting speculative_id. (cgraph_edge::num_speculative_call_targets_p): New declare. (target_prob): New variable. (speculative_id): New variable. * ipa-fnsummary.c (analyze_function_body): Create and duplicate call summaries for multiple speculative call targets. * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id. * ipa-profile.c (struct speculative_call_target): New struct. (class speculative_call_summary): New class. (class speculative_call_summaries): New class. (call_sums): New variable. (ipa_profile_generate_summary): Generate indirect multiple targets summaries. (ipa_profile_write_edge_summary): New function. (ipa_profile_write_summary): Stream out indirect multiple targets summaries. (ipa_profile_dump_all_summaries): New function. (ipa_profile_read_edge_summary): New function. (ipa_profile_read_summary_section): New function. (ipa_profile_read_summary): Stream in indirect multiple targets summaries. (ipa_profile): Generate num_speculative_call_targets from profile summaries. * ipa-ref.h (speculative_id): New variable. * ipa-utils.c (ipa_merge_profiles): Update with target_prob. * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and common_target_probability. Stream out speculative_id and num_speculative_call_targets. (input_edge): Likewise. * predict.c (dump_prediction): Remove edges count assert to be precise. * symtab.c (symtab_node::create_reference): Init speculative_id. (symtab_node::clone_references): Clone speculative_id. (symtab_node::clone_referring): Clone speculative_id. (symtab_node::clone_reference): Clone speculative_id. (symtab_node::clear_stmts_in_references): Clear speculative_id. * tree-inline.c (copy_bb): Duplicate all the speculative edges if indirect call contains multiple speculative targets. * value-prof.h (check_ic_target): Remove. * value-prof.c (gimple_value_profile_transformations): Use void function gimple_ic_transform. * value-prof.c (gimple_ic_transform): Handle topn case. Fix comment typos. Change it to a void function. 2020-01-13 Andrew Pinski * config/aarch64/aarch64-cores.def (octeontx2): New define. (octeontx2t98): New define. (octeontx2t96): New define. (octeontx2t93): New define. (octeontx2f95): New define. (octeontx2f95n): New define. (octeontx2f95mm): New define. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (-mcpu=): Document the new cpu types. 2020-01-13 Jason Merrill PR c++/33799 - destroy return value if local cleanup throws. * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR. 2020-01-13 Martin Liska * ipa-cp.c (get_max_overall_size): Use newly renamed param param_ipa_cp_unit_growth. * params.opt: Remove legacy param name. 2020-01-13 Martin Sebor PR tree-optimization/93213 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul stores to be eliminated. 2020-01-13 Martin Liska * opts.c (print_help): Do not print CL_PARAM and CL_WARNING for CL_OPTIMIZATION. 2020-01-13 Jonathan Wakely PR driver/92757 * doc/invoke.texi (Warning Options): Add caveat about some warnings depending on optimization settings. 2020-01-13 Jakub Jelinek PR tree-optimization/90838 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro argument rather than to initialize temporary for targets that don't use the mode argument at all. Initialize ctzval to avoid warning at -O0. 2020-01-10 Thomas Schwinge * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition. * tree-core.h: Document it. * gimplify.c (gimplify_omp_workshare): Set it. * omp-low.c (lower_omp_target): Use it. * tree-pretty-print.c (dump_omp_clause): Print it. * omp-low.c (lower_omp_target) : Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'. 2020-01-10 David Malcolm * Makefile.in (OBJS): Add tree-diagnostic-path.o. * common.opt (fdiagnostics-path-format=): New option. (diagnostic_path_format): New enum. (fdiagnostics-show-path-depths): New option. * coretypes.h (diagnostic_event_id_t): New forward decl. * diagnostic-color.c (color_dict): Add "path". * diagnostic-event-id.h: New file. * diagnostic-format-json.cc (json_from_expanded_location): Make non-static. (json_end_diagnostic): Call context->make_json_for_path if it exists and the diagnostic has a path. (diagnostic_output_format_init): Clear context->print_path. * diagnostic-path.h: New file. * diagnostic-show-locus.c (colorizer::set_range): Special-case when printing a run of events in a diagnostic_path so that they all get the same color. (layout::m_diagnostic_path_p): New field. (layout::layout): Initialize it. (layout::print_any_labels): Don't colorize the label text for an event in a diagnostic_path. (gcc_rich_location::add_location_if_nearby): Add "restrict_to_current_line_spans" and "label" params. Pass the former to layout.maybe_add_location_range; pass the latter when calling add_range. * diagnostic.c: Include "diagnostic-path.h". (diagnostic_initialize): Initialize context->path_format and context->show_path_depths. (diagnostic_show_any_path): New function. (diagnostic_path::interprocedural_p): New function. (diagnostic_report_diagnostic): Call diagnostic_show_any_path. (simple_diagnostic_path::num_events): New function. (simple_diagnostic_path::get_event): New function. (simple_diagnostic_path::add_event): New function. (simple_diagnostic_event::simple_diagnostic_event): New ctor. (simple_diagnostic_event::~simple_diagnostic_event): New dtor. (debug): New overload taking a diagnostic_path *. * diagnostic.def (DK_DIAGNOSTIC_PATH): New. * diagnostic.h (enum diagnostic_path_format): New enum. (json::value): New forward decl. (diagnostic_context::path_format): New field. (diagnostic_context::show_path_depths): New field. (diagnostic_context::print_path): New callback field. (diagnostic_context::make_json_for_path): New callback field. (diagnostic_show_any_path): New decl. (json_from_expanded_location): New decl. * doc/invoke.texi (-fdiagnostics-path-format=): New option. (-fdiagnostics-show-path-depths): New option. (-fdiagnostics-color): Add "path" to description of default GCC_COLORS; describe it. (-fdiagnostics-format=json): Document how diagnostic paths are represented in the JSON output format. * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby): Add optional params "restrict_to_current_line_spans" and "label". * opts.c (common_handle_option): Handle OPT_fdiagnostics_path_format_ and OPT_fdiagnostics_show_path_depths. * pretty-print.c: Include "diagnostic-event-id.h". (pp_format): Implement "%@" format code for printing diagnostic_event_id_t *. (selftest::test_pp_format): Add tests for "%@". * selftest-run-tests.c (selftest::run_tests): Call selftest::tree_diagnostic_path_cc_tests. * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl. * toplev.c (general_init): Initialize global_dc->path_format and global_dc->show_path_depths. * tree-diagnostic-path.cc: New file. * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make non-static. Drop "diagnostic" param in favor of storing the original value of "where" and re-using it. (virt_loc_aware_diagnostic_finalizer): Update for dropped param of maybe_unwind_expanded_macro_loc. (tree_diagnostics_defaults): Initialize context->print_path and context->make_json_for_path. * tree-diagnostic.h (default_tree_diagnostic_path_printer): New decl. (default_tree_make_json_for_path): New decl. (maybe_unwind_expanded_macro_loc): New decl. 2020-01-10 Jakub Jelinek PR tree-optimization/93210 * fold-const.h (native_encode_initializer, can_native_interpret_type_p): Declare. * fold-const.c (native_encode_string): Fix up handling with off != -1, simplify. (native_encode_initializer): New function, moved from dwarf2out.c. Adjust to native_encode_expr compatible arguments, including dry-run and partial extraction modes. Don't handle STRING_CST. (can_native_interpret_type_p): No longer static. * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify offset / BITS_PER_UNIT fits into int and don't call it if can_native_interpret_type_p fails. If suboff is NULL and for CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with native_encode_initializer. (fold_const_aggregate_ref_1): Formatting fix. * dwarf2out.c (native_encode_initializer): Moved to fold-const.c. (tree_add_const_value_attribute): Adjust caller. PR tree-optimization/90838 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of CTZ_DEFINED_VALUE_AT_ZERO. 2020-01-10 Vladimir Makarov PR inline-asm/93027 * lra-constraints.c (match_reload): Permit input operands have the same mode as output while other input operands have a different mode. 2020-01-10 Wilco Dijkstra PR tree-optimization/90838 * tree-ssa-forwprop.c (check_ctz_array): Add new function. (check_ctz_string): Likewise. (optimize_count_trailing_zeroes): Likewise. (simplify_count_trailing_zeroes): Likewise. (pass_forwprop::execute): Try ctz simplification. * match.pd: Add matching for ctz idioms. 2020-01-10 Stam Markianos-Wright * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function for target hook. (aarch64_invalid_unary_op): New function for target hook. (aarch64_invalid_binary_op): New function for target hook. 2020-01-10 Stam Markianos-Wright * config.gcc: Add arm_bf16.h. * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type): Add BFmode. (aarch64_init_simd_builtin_types): Define element types for vector types. (aarch64_init_bf16_types): New function. (aarch64_general_init_builtins): Add arm_init_bf16_types function call. * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector modes. * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types. * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move patterns. * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF. (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF. * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Add support for BF types. (aarch64_gimplify_va_arg_expr): Add support for BF types. (aarch64_vq_mode): Add support for BF types. (aarch64_simd_container_mode): Add support for BF types. (aarch64_mangle_type): Add support for BF scalar type. * config/aarch64/aarch64.md: Add BFmode to movhf pattern. * config/aarch64/arm_bf16.h: New file. * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types. * config/aarch64/iterators.md: Add BF types to mode attributes. (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New. 2020-01-10 Jason Merrill PR c++/93173 - incorrect tree sharing. * gimplify.c (copy_if_shared): No longer static. * gimplify.h: Declare it. 2020-01-10 Richard Sandiford * doc/invoke.texi (-msve-vector-bits=): Document that -msve-vector-bits=128 now generates VL-specific code for little-endian targets. * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use build_vector_type_for_mode to construct the data vector types. * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate VL-specific code for -msve-vector-bits=128 on little-endian targets. (aarch64_simd_container_mode): Always prefer Advanced SIMD modes for 128-bit vectors. 2020-01-10 Richard Sandiford * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask invocation. 2020-01-10 Richard Sandiford * config/aarch64/aarch64-builtins.c (aarch64_builtin_vectorized_function): Check for specific vector modes, rather than checking the number of elements and the element mode. 2020-01-10 Richard Sandiford * tree-vect-loop.c (vect_create_epilog_for_reduction): Use get_related_vectype_for_scalar_type rather than build_vector_type to create the index type for a conditional reduction. 2020-01-10 Richard Sandiford * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF for any type of gather or scatter, including strided accesses. 2020-01-10 Andre Vieira * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function comment. 2020-01-10 Andre Vieira * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use get_dr_vinfo_offset * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init parameter and its use to reset DR_OFFSET's. (vect_transform_loop): Remove orig_drs_init argument. * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset member of dr_vec_info rather than the offset of the associated data_reference's innermost_loop_behavior. (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference. (vect_do_peeling): Remove orig_drs_init parameter and its construction. * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with get_dr_vinfo_offset. (vectorizable_store): Likewise. (vectorizable_load): Likewise. 2020-01-10 Richard Biener * gimple-ssa-store-merging (pass_store_merging::terminate_all_aliasing_chains): Cache alias info. 2020-01-10 Martin Liska PR ipa/93217 * ipa-inline-analysis.c (offline_size): Make proper parenthesis encapsulation that was there before r280040. 2020-01-10 Richard Biener PR middle-end/93199 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL sequences to avoid walking them again for secondary opportunities. (pass_lower_eh_dispatch::execute): Instead actually insert them here. 2020-01-10 Richard Biener PR middle-end/93199 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible. (cleanup_all_empty_eh): Walk landing pads in reverse order to avoid quadraticness. 2020-01-10 Martin Jambor * params.opt (param_ipa_sra_max_replacements): Mark as Optimization. * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it to get param_ipa_sra_max_replacements. (param_splitting_across_edge): Pass the caller to pull_accesses_from_callee. 2020-01-10 Martin Jambor * params.opt (param_ipcp_unit_growth): Mark as Optimization. * ipa-cp.c (max_new_size): Removed. (orig_overall_size): New variable. (get_max_overall_size): New function. (estimate_local_effects): Use it. Adjust dump. (decide_about_value): Likewise. (ipcp_propagate_stage): Do not calculate max_new_size, just store orig_overall_size. Adjust dump. (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size. 2020-01-10 Martin Jambor * params.opt (param_ipa_max_agg_items): Mark as Optimization * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use instead of param_ipa_max_agg_items. (merge_aggregate_lattices): Extract param_ipa_max_agg_items from optimization info for the callee. 2020-01-09 Kwok Cheung Yeung * lto-streamer-in.c (input_function): Remove streamed-in inline debug markers if debug_inline_points is false. 2020-01-09 Richard Sandiford * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to extra_objs. * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and aarch64-sve-builtins-sve2.h. (aarch64-sve-builtins-sve2.o): New rule. * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro. (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise. (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise. (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and TARGET_SVE2_SM4. * config/aarch64/aarch64-sve.md: Update comments with SVE2 instructions that are handled here. (@cond_asrd): Generalize to... (@cond_): ...this. (*cond_asrd_2): Generalize to... (*cond__2): ...this. (*cond_asrd_z): Generalize to... (*cond__z): ...this. * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec. (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise. (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise. * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt): New pattern. (@aarch64_gather_ldnt_) (@aarch64_scatter_stnt): Likewise. (@aarch64_scatter_stnt_) (@aarch64_mul_lane_): Likewise. (@aarch64_sve_suqadd_const): Likewise. (*h): Generalize to... (@aarch64_pred_): ...this new pattern. (@cond_): New expander. (*cond__2): New pattern. (*cond__3): Likewise. (*cond__any): Likewise. (*cond__z): Likewise. (@aarch64_sve_):: Likewise. (@aarch64_sve__lane_): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond__2): New pattern. (*cond__3): Likewise. (*cond__any): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve__lane_) (@aarch64_sve_add_mul_lane_): Likewise. (@aarch64_sve_sub_mul_lane_): Likewise. (@aarch64_sve2_xar): Likewise. (@aarch64_sve2_bcax): Likewise. (*aarch64_sve2_eor3): Rename to... (@aarch64_sve2_eor3): ...this. (@aarch64_sve2_bsl): New expander. (@aarch64_sve2_nbsl): Likewise. (@aarch64_sve2_bsl1n): Likewise. (@aarch64_sve2_bsl2n): Likewise. (@aarch64_sve_add_): Likewise. (*aarch64_sve2_sra): Add MOVPRFX support. (@aarch64_sve_add_): New pattern. (@aarch64_sve_): Likewise. (@aarch64_sve2_aba): New expander. (*aarch64_sve2_aba): New pattern. (@aarch64_sve_): Likewise. (mull): Generalize to... (@aarch64_sve_): ...this new pattern. (@aarch64_sve__lane_) (@aarch64_sve_) (@aarch64_sve_add_) (@aarch64_sve_add__lane_) (@aarch64_sve_qadd_) (@aarch64_sve_qadd__lane_) (@aarch64_sve_sub_) (@aarch64_sve_sub__lane_) (@aarch64_sve_qsub_) (@aarch64_sve_qsub__lane_) (@aarch64_sve_): New patterns. (@aarch64__lane_) (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (shrnb): Generalize to... (@aarch64_sve_): ...this new pattern. (shrnt): Generalize to... (@aarch64_sve_): ...this new pattern. (@aarch64_pred_): New pattern. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond__2): New pattern. (*cond__z): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64__lane_): Likewise. (@aarch64_sve_): Likewise. (@aarch64__lane_): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond_): New pattern. (@aarch64_sve2_cvtnt): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond__any): New pattern. (@aarch64_sve2_cvtxnt): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond_): New pattern. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond_): New pattern. (@aarch64_sve2_pmul): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve2_tbl2): Likewise. (@aarch64_sve2_tbx): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve2_histcnt): Likewise. (@aarch64_sve2_histseg): Likewise. (@aarch64_pred_): Likewise. (*aarch64_pred__cc): Likewise. (*aarch64_pred__ptest): Likewise. (aarch64_sve2_aes): Likewise. (aarch64_sve2_aes): Likewise. (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise. (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise. (mulhs3): Update after above pattern name changes. * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY) (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI) (SVE2_PMULL_PAIR_I): New mode iterators. (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP) (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT) (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA) (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT) (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT) (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP) (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT) (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP) (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH) (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR) (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT) (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB) (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT) (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP) (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT) (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90) (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB) (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB) (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB) (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB) (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT) (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB) (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT) (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT) (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT) (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT) (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT) (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs. (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT) (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS) (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move further down file. (VNARROW, Ventype): New mode attributes. (Vewtype): Handle VNx2DI. Fix typo in comment. (VDOUBLE): New mode attribute. (sve_lane_con): Handle VNx8HI. (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2. (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus. (sve_int_op, sve_int_op_rev): Handle the above codes. (sve_pred_int_rhs2_operand): Likewise. (MULLBT, SHRNB, SHRNT): Delete. (SVE_INT_SHIFT_IMM): New int iterator. (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI and UNSPEC_WHILEHS for TARGET_SVE2. (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT) (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG) (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB) (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR) (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators. (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise. (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD) (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise. (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA) (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG) (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise. (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE) (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE) (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise. (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise. (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise. (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise. (optab): Handle the new unspecs. (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB and UNSPEC_RSHRNT. (lr): Handle the new unspecs. (bt): Delete. (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs. (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op) (sve_int_qsub_op): New int attributes. (sve_fp_op, rot): Handle the new unspecs. * config/aarch64/aarch64-sve-builtins.h (function_resolver::require_matching_pointer_type): Declare. (function_resolver::resolve_unary): Add an optional boolean argument. (function_resolver::finish_opt_n_resolution): Add an optional type_suffix_index argument. (gimple_folder::redirect_call): Declare. (gimple_expander::prepare_gather_address_operands): Add an optional bool parameter. * config/aarch64/aarch64-sve-builtins.cc: Include aarch64-sve-builtins-sve2.h. (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros. (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise. (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise. (TYPES_hsd_integer): Use TYPES_hsd_signed. (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros. (TYPES_s_unsigned): Likewise. (TYPES_s_integer): Use TYPES_s_unsigned. (TYPES_sd_signed, TYPES_sd_unsigned): New macros. (TYPES_sd_integer): Use them. (TYPES_d_unsigned): New macro. (TYPES_d_integer): Use it. (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros. (TYPES_cvt_narrow): Likewise. (DEF_SVE_TYPES_ARRAY): Include the new types macros above. (preds_mx): New variable. (function_builder::add_overloaded_function): Allow the new feature set to be more restrictive than the original one. (function_resolver::infer_pointer_type): Remove qualifiers from the pointer type before printing it. (function_resolver::require_matching_pointer_type): New function. (function_resolver::resolve_sv_displacement): Handle functions that don't support 32-bit vector indices or svint32_t vector offsets. (function_resolver::finish_opt_n_resolution): Take the inferred type as a separate argument. (function_resolver::resolve_unary): Optionally treat all forms in the same way as normal merging functions. (gimple_folder::redirect_call): New function. (function_expander::prepare_gather_address_operands): Add an argument that says whether scaled forms are available. If they aren't, handle scaling of vector indices and don't add the extension and scaling operands. (function_expander::map_to_unspecs): If aarch64_sve isn't available, fall back to using cond_* instead. * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function): Split out the member variables into... (rtx_code_function_base): ...this new base class. (rtx_code_function_rotated): Inherit rtx_code_function_base. (unspec_based_function): Split out the member variables into... (unspec_based_function_base): ...this new base class. (unspec_based_function_rotated): Inherit unspec_based_function_base. (unspec_based_function_exact_insn): New class. (unspec_based_add_function, unspec_based_add_lane_function) (unspec_based_lane_function, unspec_based_pred_function) (unspec_based_qadd_function, unspec_based_qadd_lane_function) (unspec_based_qsub_function, unspec_based_qsub_lane_function) (unspec_based_sub_function, unspec_based_sub_lane_function): New typedefs. (unspec_based_fused_function): New class. (unspec_based_mla_function, unspec_based_mls_function): New typedefs. (unspec_based_fused_lane_function): New class. (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New typedefs. (CODE_FOR_MODE1): New macro. (fixed_insn_function): New class. (while_comparison): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane) (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n) (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr) (load_ext_gather_index_restricted, load_ext_gather_offset_restricted) (load_gather_sv_restricted, shift_left_imm_long): Declare. (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise. (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise. (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted) (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane) (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate) (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint) (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt) (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication): Also add an initial argument for unary_convert_narrowt, regardless of the predication type. (build_32_64): Allow loads and stores to specify MODE_none. (build_sv_index64, build_sv_uint_offset): New functions. (long_type_suffix): New function. (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes. (binary_imm_long_base, load_gather_sv_base): Likewise. (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise. (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise. (unary_narrowb_base, unary_narrowt_base): Likewise. (binary_long_lane_def, binary_long_lane): New shape. (binary_long_opt_n_def, binary_long_opt_n): Likewise. (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise. (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise. (binary_to_uint_def, binary_to_uint): Likewise. (binary_wide_def, binary_wide): Likewise. (binary_wide_opt_n_def, binary_wide_opt_n): Likewise. (compare_def, compare): Likewise. (compare_ptr_def, compare_ptr): Likewise. (load_ext_gather_index_restricted_def, load_ext_gather_index_restricted): Likewise. (load_ext_gather_offset_restricted_def, load_ext_gather_offset_restricted): Likewise. (load_gather_sv_def): Inherit from load_gather_sv_base. (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape. (shift_left_imm_def, shift_left_imm): Likewise. (shift_left_imm_long_def, shift_left_imm_long): Likewise. (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise. (store_scatter_index_restricted_def, store_scatter_index_restricted): Likewise. (store_scatter_offset_restricted_def, store_scatter_offset_restricted): Likewise. (tbl_tuple_def, tbl_tuple): Likewise. (ternary_long_lane_def, ternary_long_lane): Likewise. (ternary_long_opt_n_def, ternary_long_opt_n): Likewise. (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base. (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base. (ternary_qq_rotate_def, ternary_qq_rotate): New shape. (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise. (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise. (ternary_uint_def, ternary_uint): Likewise. (unary_convert): Fix typo in comment. (unary_convert_narrowt_def, unary_convert_narrowt): New shape. (unary_long_def, unary_long): Likewise. (unary_narrowb_def, unary_narrowb): Likewise. (unary_narrowt_def, unary_narrowt): Likewise. (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise. (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise. (unary_to_int_def, unary_to_int): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla) (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions. (svasrd_impl): Delete. (svcadd_impl::expand): Handle integer operations too. (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the new functions to derive the unspec numbers. (svmla_svmls_lane_impl): Replace with... (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle integer operations too. (svwhile_impl): Rename to... (svwhilelx_impl): ...this and inherit from while_comparison. (svasrd): Use unspec_based_function. (svmla_lane): Use svmla_lane_impl. (svmls_lane): Use svmls_lane_impl. (svrecpe, svrsqrte): Handle unsigned integer operations too. (svwhilele, svwhilelt): Use svwhilelx_impl. * config/aarch64/aarch64-sve-builtins-sve2.h: New file. * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. * config/aarch64/aarch64-sve-builtins.def: Include aarch64-sve-builtins-sve2.def. 2020-01-09 Richard Sandiford * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p) (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument. * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p) (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar immediates as well as vector ones. * config/aarch64/predicates.md (aarch64_sve_arith_immediate) (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate) (aarch64_sve_qsub_immediate): Update calls accordingly. 2020-01-09 Richard Sandiford * config/aarch64/aarch64-sve2.md: Add banner comments. (mulhs3): Move further up file. (mull, shrnb, shrnt) (*aarch64_sve2_sra): Move further down file. * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too. 2020-01-09 Richard Sandiford * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW and UNSPEC_WHILEWR. (while_optab_cmp): Handle them. * config/aarch64/aarch64-sve.md (*while__ptest): Make public and add a "@" marker. * config/aarch64/aarch64-sve2.md (check__ptrs): Use it instead of gen_aarch64_sve2_while_ptest. (@aarch64_sve2_while_ptest): Delete. 2020-01-09 Richard Sandiford * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to... (UNSPEC_WHILELE): ...this. (UNSPEC_WHILE_LO): Rename to... (UNSPEC_WHILELO): ...this. (UNSPEC_WHILE_LS): Rename to... (UNSPEC_WHILELS): ...this. (UNSPEC_WHILE_LT): Rename to... (UNSPEC_WHILELT): ...this. * config/aarch64/iterators.md (SVE_WHILE): Update accordingly. (cmp_op, while_optab_cmp): Likewise. * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise. (svwhilelt): Likewise. 2020-01-09 Richard Sandiford * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete. (unary_to_uint): Define. * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def) (unary_count): Rename to... (unary_to_uint_def, unary_to_uint): ...this. * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly. 2020-01-09 Richard Sandiford * config/aarch64/aarch64-sve-builtins-functions.h (code_for_mode_function): New class. (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros. * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl) (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete. (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0. (svmul_lane, svtmad): Use CODE_FOR_MODE0. 2020-01-09 Richard Sandiford * config/aarch64/iterators.md (addsub): New code attribute. * config/aarch64/aarch64-simd.md (aarch64_): Re-express as... (aarch64_q): ...this, making the same change in the asm string and attributes. Fix indentation. * config/aarch64/aarch64-sve.md (@aarch64_): Re-express as... (@aarch64_sve_): ...this. * config/aarch64/aarch64-sve-builtins.h (function_expander::expand_signed_unpred_op): Delete. * config/aarch64/aarch64-sve-builtins.cc (function_expander::expand_signed_unpred_op): Likewise. (function_expander::map_to_rtx_codes): If the optab isn't defined, try using code_for_aarch64_sve instead. * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete. (svqsub_impl): Likewise. (svqadd, svqsub): Use rtx_code_function instead. 2020-01-09 Richard Sandiford * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete. (HADDSUB, sur, addsub): Remove them. 2020-01-09 Richard Sandiford * tree-nrv.c (pass_return_slot::execute): Handle all internal functions the same way, rather than singling out those that aren't mapped directly to optabs. 2020-01-09 Richard Sandiford * target.def (compatible_vector_types_p): New target hook. * hooks.h (hook_bool_const_tree_const_tree_true): Declare. * hooks.c (hook_bool_const_tree_const_tree_true): New function. * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook. * doc/tm.texi: Regenerate. * gimple-expr.c: Include target.h. (useless_type_conversion_p): Use targetm.compatible_vector_types_p. * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New function. (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define. * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred): Use the original predicate if it already has a suitable type. 2020-01-09 Martin Jambor * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct, resolve_speculation and redirect_call_stmt_to_callee static. Change return type of set_call_stmt to cgraph_edge *. * auto-profile.c (afdo_indirect_call): Adjust call to redirect_call_stmt_to_callee. * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *, make the this pointer explicit, adjust self-recursive calls and the call top make_direct. Return the resulting edge. (cgraph_edge::remove): Make this pointer explicit. (cgraph_edge::resolve_speculation): Likewise, adjust call to remove. (cgraph_edge::make_direct): Likewise, adjust call to resolve_speculation. (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust call to set_call_stmt. (cgraph_update_edges_for_call_stmt_node): Update call to set_call_stmt and remove. * cgraphclones.c (cgraph_node::set_call_stmt_including_clones): Renamed edge to master_edge. Adjusted calls to set_call_stmt. (cgraph_node::create_edge_including_clones): Moved "first" definition of edge to the block where it was used. Adjusted calls to set_call_stmt. (cgraph_node::remove_symbol_and_inline_clones): Adjust call to cgraph_edge::remove. * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to make_direct and redirect_call_stmt_to_callee. * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to resolve_speculation and make_direct. * ipa-inline-transform.c (inline_transform): Adjust call to redirect_call_stmt_to_callee. (check_speculations_1):: Adjust call to resolve_speculation. * ipa-inline.c (resolve_noninline_speculation): Adjust call to resolve-speculation. (inline_small_functions): Adjust call to resolve_speculation. (ipa_inline): Likewise. * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to make_direct. * ipa-visibility.c (function_and_variable_visibility): Make iteration safe with regards to edge removal, adjust calls to redirect_call_stmt_to_callee. * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct and redirect_call_stmt_to_callee. * multiple_target.c (create_dispatcher_calls): Adjust call to redirect_call_stmt_to_callee (redirect_to_specific_clone): Likewise. * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph): Adjust calls to cgraph_edge::remove. * tree-inline.c (copy_bb): Adjust call to set_call_stmt. (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee. (expand_call_inline): Adjust call to cgraph_edge::remove. 2020-01-09 Martin Liska * params.opt: Set Optimization for param_max_speculative_devirt_maydefs. 2020-01-09 Martin Sebor PR middle-end/93200 PR fortran/92956 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type. 2020-01-09 Martin Liska * auto-profile.c (auto_profile): Use opt_for_fn for a parameter. * ipa-cp.c (ipcp_lattice::add_value): Likewise. (propagate_vals_across_arith_jfunc): Likewise. (hint_time_bonus): Likewise. (incorporate_penalties): Likewise. (good_cloning_opportunity_p): Likewise. (perform_estimation_of_a_value): Likewise. (estimate_local_effects): Likewise. (ipcp_propagate_stage): Likewise. * ipa-fnsummary.c (decompose_param_expr): Likewise. (set_switch_stmt_execution_predicate): Likewise. (analyze_function_body): Likewise. * ipa-inline-analysis.c (offline_size): Likewise. * ipa-inline.c (early_inliner): Likewise. * ipa-prop.c (ipa_analyze_node): Likewise. (ipcp_transform_function): Likewise. * ipa-sra.c (process_scan_results): Likewise. (ipa_sra_summarize_function): Likewise. * params.opt: Rename ipcp-unit-growth to ipa-cp-unit-growth. Add Optimization for various IPA-related parameters. 2020-01-09 Richard Biener PR middle-end/93054 * gimplify.c (gimplify_expr): Deal with NOP definitions. 2020-01-09 Richard Biener PR tree-optimization/93040 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit. 2020-01-09 Georg-Johann Lay * common/config/avr/avr-common.c (avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early. 2020-01-09 Martin Liska * cgraphclones.c (symbol_table::materialize_all_clones): Use cgraph_node::dump_name. 2020-01-09 Jakub Jelinek PR inline-asm/93202 * config/riscv/riscv.c (riscv_print_operand_reloc): Use output_operand_lossage instead of gcc_unreachable. * doc/md.texi (riscv f constraint): Fix typo. PR target/93141 * config/i386/i386.md (subv4): Use SWIDWI iterator instead of SWI. Use instead of . Use CONST_SCALAR_INT_P instead of CONST_INT_P. (*subv4_1): Rename to ... (subv4_1): ... this. (*subv4_doubleword, *addv4_doubleword_1): New define_insn_and_split patterns. (*subv4_overflow_1, *addv4_overflow_2): New define_insn patterns. 2020-01-08 David Malcolm * vec.c (class selftest::count_dtor): New class. (selftest::test_auto_delete_vec): New test. (selftest::vec_c_tests): Call it. * vec.h (class auto_delete_vec): New class template. (auto_delete_vec::~auto_delete_vec): New dtor. 2020-01-08 David Malcolm * sbitmap.h (auto_sbitmap): Add operator const_sbitmap. 2020-01-08 Jim Wilson * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out use of TLS_MODEL_LOCAL_EXEC when not pic. 2020-01-08 David Malcolm * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix memory leak. 2020-01-08 Jakub Jelinek PR target/93187 * config/i386/i386.md (*stack_protect_set_2_ peephole2, *stack_protect_set_3 peephole2): Also check that the second insns source is general_operand. PR target/93174 * config/i386/i386.md (addcarry_0): Use nonimmediate_operand predicate for output operand instead of register_operand. (addcarry, addcarry_1): Likewise. Add alternative with memory destination and non-memory operands[2]. 2020-01-08 Martin Liska * cgraph.c (cgraph_node::dump): Use ::dump_name or ::dump_asm_name instead of (::name or ::asm_name). * cgraphclones.c (symbol_table::materialize_all_clones): Likewise. * cgraphunit.c (walk_polymorphic_call_targets): Likewise. (analyze_functions): Likewise. (expand_all_functions): Likewise. * ipa-cp.c (ipcp_cloning_candidate_p): Likewise. (propagate_bits_across_jump_function): Likewise. (dump_profile_updates): Likewise. (ipcp_store_bits_results): Likewise. (ipcp_store_vr_results): Likewise. * ipa-devirt.c (dump_targets): Likewise. * ipa-fnsummary.c (analyze_function_body): Likewise. * ipa-hsa.c (check_warn_node_versionable): Likewise. (process_hsa_functions): Likewise. * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise. (set_alias_uids): Likewise. * ipa-inline-transform.c (save_inline_function_body): Likewise. * ipa-inline.c (recursive_inlining): Likewise. (inline_to_all_callers_1): Likewise. (ipa_inline): Likewise. * ipa-profile.c (ipa_propagate_frequency_1): Likewise. (ipa_propagate_frequency): Likewise. * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise. (remove_described_reference): Likewise. * ipa-pure-const.c (worse_state): Likewise. (check_retval_uses): Likewise. (analyze_function): Likewise. (propagate_pure_const): Likewise. (propagate_nothrow): Likewise. (dump_malloc_lattice): Likewise. (propagate_malloc): Likewise. (pass_local_pure_const::execute): Likewise. * ipa-visibility.c (optimize_weakref): Likewise. (function_and_variable_visibility): Likewise. * ipa.c (symbol_table::remove_unreachable_nodes): Likewise. (ipa_discover_variable_flags): Likewise. * lto-streamer-out.c (output_function): Likewise. (output_constructor): Likewise. * tree-inline.c (copy_bb): Likewise. * tree-ssa-structalias.c (ipa_pta_execute): Likewise. * varpool.c (symbol_table::remove_unreferenced_decls): Likewise. 2020-01-08 Richard Biener PR middle-end/93199 * tree-eh.c (sink_clobbers): Update virtual operands for the first and last stmt only. Add a dry-run capability. (pass_lower_eh_dispatch::execute): Perform clobber sinking after CFG manipulations and in RPO order to catch all secondary opportunities reliably. 2020-01-08 Georg-Johann Lay PR target/93182 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document. 2019-01-08 Richard Biener PR middle-end/93199 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified. * tree-ssa-loop-im.c (move_computations_worker): Properly adjust virtual operand, also updating SSA use. * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction): Update stmt after resetting virtual operand. (tree_loop_interchange::move_code_to_inner_loop): Likewise. * gimple-iterator.c (gsi_remove): When not removing the stmt permanently do not delink immediate uses or mark the stmt modified. 2020-01-08 Martin Liska * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name. (ipa_call_context::estimate_size_and_time): Likewise. (inline_analyze_function): Likewise. 2020-01-08 Martin Liska * cgraph.c (cgraph_node::dump): Use systematically dump_asm_name. 2020-01-08 Georg-Johann Lay Add -nodevicespecs option for avr. PR target/93182 * config/avr/avr.opt (-nodevicespecs): New driver option. * config/avr/driver-avr.c (avr_devicespecs_file): Only issue "-specs=device-specs/..." if that option is not set. * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document. 2020-01-08 Georg-Johann Lay Implement 64-bit double functions for avr. PR target/92055 * config.gcc (tm_defines) [target=avr]: Support --with-libf7, --with-double-comparison. * doc/install.texi: Document them. * config/avr/avr-c.c (avr_cpu_cpp_builtins) : New built-in defines. * doc/invoke.texi (AVR Built-in Macros): Document them. * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New. * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function. * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro. 2020-01-08 Richard Earnshaw PR target/93188 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants when only building rm-profile multilibs. 2020-01-08 Feng Xue PR ipa/93084 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate lattice for a value to check. (propagate_vals_across_arith_jfunc): Add an assertion to ensure finite propagation in self-recursive scc. 2020-01-08 Luo Xiong Hu * ipa-inline.c (caller_growth_limits): Restore the AND. 2020-01-07 Andrew Stubbs * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator. (VEC_ALLREG_ALT): New iterator. (VEC_ALLREG_INT_MODE): New iterator. (VCMP_MODE): New iterator. (VCMP_MODE_INT): New iterator. (vec_cmpudi): Use VCMP_MODE_INT. (vec_cmpv64qidi): New define_expand. (vec_cmpdi_exec): Use VCMP_MODE. (vec_cmpudi_exec): New define_expand. (vec_cmpv64qidi_exec): New define_expand. (vec_cmpdi_dup): Use VCMP_MODE. (vec_cmpdi_dup_exec): Use VCMP_MODE. (vcond): Rename ... (vcond): ... to this. (vcond_exec): Rename ... (vcond_exec): ... to this. (vcondu): Rename ... (vcondu): ... to this. (vcondu_exec): Rename ... (vcondu_exec): ... to this. * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes. * config/gcn/gcn.md (expander): Add sign_extend and zero_extend. 2020-01-07 Andrew Stubbs * config/gcn/constraints.md (DA): Update description and match. (DB): Likewise. (Db): New constraint. * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second parameter. * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter. Implement 'Db' mixed immediate type. * config/gcn/gcn-valu.md (addcv64si3): Rework constraints. (addcv64si3_dup): Delete. (subcv64si3): Rework constraints. (addv64di3): Rework constraints. (addv64di3_exec): Rework constraints. (subv64di3): Rework constraints. (addv64di3_dup): Delete. (addv64di3_dup_exec): Delete. (addv64di3_zext): Rework constraints. (addv64di3_zext_exec): Rework constraints. (addv64di3_zext_dup): Rework constraints. (addv64di3_zext_dup_exec): Rework constraints. (addv64di3_zext_dup2): Rework constraints. (addv64di3_zext_dup2_exec): Rework constraints. (addv64di3_sext_dup2): Rework constraints. (addv64di3_sext_dup2_exec): Rework constraints. 2020-01-07 Andre Vieira * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented existing target checks. 2020-01-07 Richard Biener * doc/install.texi: Bump minimal supported MPC version. 2020-01-07 Richard Sandiford * langhooks-def.h (lhd_simulate_enum_decl): Declare. (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it. * langhooks.c: Include stor-layout.h. (lhd_simulate_enum_decl): New function. * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call handle_arm_sve_h for the LTO frontend. (register_vector_type): Cope with null returns from pushdecl. 2020-01-07 Richard Sandiford * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p) (aarch64_sve::nvectors_if_data_type): Replace with... (aarch64_sve::builtin_type_p): ...this. * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h. (find_vector_type): Delete. (add_sve_type_attribute): New function. (lookup_sve_type_attribute): Likewise. (register_builtin_types): Add an "SVE type" attribute to each type. (register_tuple_type): Likewise. (svbool_type_p, nvectors_if_data_type): Delete. (mangle_builtin_type): Use lookup_sve_type_attribute. (builtin_type_p): Likewise. Add an overload that returns the number of constituent vector and predicate registers. * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete. (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p instead of aarch64_sve_argument_p. (aarch64_takes_arguments_in_sve_regs_p): Likewise. (aarch64_pass_by_reference): Likewise. (aarch64_function_value_1): Likewise. (aarch64_return_in_memory): Likewise. (aarch64_layout_arg): Likewise. 2020-01-07 Jakub Jelinek PR tree-optimization/93156 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second least significant bit is always clear. PR tree-optimization/93118 * match.pd ((x >> c) << c -> x & (-1< * params.opt: Add Optimization for various parameters. 2020-01-07 Martin Liska PR ipa/83411 * doc/extend.texi: Explain cloning for target_clone attribute. 2020-01-07 Martin Liska PR tree-optimization/92860 * common.opt: Make in Optimization option as it is affected by -O0, which is an Optimization option. * tree-inline.c (tree_inlinable_function_p): Use opt_for_fn for warn_inline. (expand_call_inline): Likewise. 2020-01-07 Martin Liska PR tree-optimization/92860 * common.opt: Make flag_ree as optimization attribute. 2020-01-07 Martin Liska PR optimization/92860 * params.opt: Mark param_min_crossjump_insns with Optimization keyword. 2020-01-07 Luo Xiong Hu * ipa-inline-analysis.c (estimate_growth): Fix typo. * ipa-inline.c (caller_growth_limits): Use OR instead of AND. 2020-01-06 Michael Meissner * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New helper function to return the valid addressing formats for a given hard register and mode. (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask. * config/rs6000/constraints.md (Q constraint): Update documentation. * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint documentation. * config/rs6000/vsx.md (vsx_extract__var, VSX_D iterator): Use 'Q' for doing vector extract from memory. (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from memory. (vsx_extract__var, VSX_EXTRACT_I iterator): Use 'Q' for doing vector extract from memory. (vsx_extract__mode_var): Use 'Q' for doing vector extract from memory. * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support for the offset being 34-bits when -mcpu=future is used. 2020-01-06 John David Anglin * config/pa/pa.md: Revert change to use ordered_comparison_operator instead of cmpib_comparison_operator in cmpib patterns. * config/pa/predicates.md (cmpib_comparison_operator): Revert removal of cmpib_comparison_operator. Revise comment. 2020-01-06 Richard Sandiford * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts in an IFN_DIV_POW2 node to be equal. 2020-01-06 Richard Sandiford * tree-vect-stmts.c (vect_check_load_store_mask): Rename to... (vect_check_scalar_mask): ...this. (vectorizable_store, vectorizable_load): Update call accordingly. (vectorizable_call): Use vect_check_scalar_mask to check the mask argument in calls to conditional internal functions. 2020-01-06 Andrew Stubbs * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for '0' matching inputs. (subv64di3_exec): Likewise. 2020-01-06 Bryan Stenson * config/mips/mips.c (vr4130_align_insns): Fix typo. * doc/md.texi (movstr): Likewise. 2020-01-06 Andrew Stubbs * config/gcn/gcn-valu.md (vec_extract): Add early clobber. 2020-01-06 Richard Sandiford * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md): Depend on... (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents to a temporary file and use move-if-change to update the real file where necessary. 2020-01-06 Richard Sandiford * config/aarch64/aarch64-sve.md (@aarch64_sel_dup): Use Upl rather than Upa for CPY /M. 2020-01-06 Andrew Stubbs * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline immediate. 2020-01-06 Martin Liska PR tree-optimization/92860 * params.opt: Mark param_max_combine_insns with Optimization keyword. 2020-01-05 Jakub Jelinek PR target/93141 * config/i386/i386.md (SWIDWI): New mode iterator. (DWI, dwi): Add TImode variants. (addv4): Use SWIDWI iterator instead of SWI. Use instead of . Use CONST_SCALAR_INT_P instead of CONST_INT_P. (*addv4_1): Rename to ... (addv4_1): ... this. (QWI): New mode attribute. (*addv4_doubleword, *addv4_doubleword_1): New define_insn_and_split patterns. (*addv4_overflow_1, *addv4_overflow_2): New define_insn patterns. (uaddv4): Use SWIDWI iterator instead of SWI. Use instead of . (*addcarry_1): New define_insn. (*add3_doubleword_cc_overflow_1): New define_insn_and_split. 2020-01-03 Konstantin Kharlamov * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm): Use "call" instead of "set". 2020-01-03 Martin Jambor PR ipa/92917 * ipa-cp.c (print_all_lattices): Skip functions without info. 2020-01-03 Jakub Jelinek PR target/93089 * config/i386/i386-options.c (ix86_simd_clone_adjust): If TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd' simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512 for 'e' simd clones. PR target/93089 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave entry. (mprefer-vector-width=): Add Save. * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment. (ix86_debug_options, ix86_function_specific_print): Adjust ix86_target_string callers. (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=. (ix86_valid_target_attribute_tree): Likewise. * config/i386/i386-options.h (ix86_target_string): Add PVW argument. * config/i386/i386-expand.c (ix86_expand_builtin): Adjust ix86_target_string caller. PR target/93110 * config/i386/i386.md (abs2): Use expand_simple_binop instead of emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode instead of gen_int_shift_amount + convert_modes. PR rtl-optimization/93088 * loop-iv.c (find_single_def_src): Punt after looking through 128 reg copies for regs with single definitions. Move definitions to first uses. 2020-01-02 Dennis Zhang * config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC, __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and __ARM_BF16_FORMAT_ALTERNATIVE when enabled. * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features. * config/arm/arm-tables.opt: Regenerated. * config/arm/arm.c (arm_option_reconfigure_globals): Initialize arm_arch_i8mm and arm_arch_bf16 when enabled. * config/arm/arm.h (TARGET_I8MM): New macro. (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise. * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a. * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a. * config/arm/t-multilib: Add matching rules for -march=armv8.6-a. (v8_6_a_simd_variants): New. (v8_*_a_simd_variants): Add i8mm and bf16. * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. 2020-01-02 Jakub Jelinek PR ipa/93087 * predict.c (compute_function_frequency): Don't call warn_function_cold on functions that already have cold attribute. 2020-01-01 John David Anglin PR target/67834 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to COMDAT group function labels in .data.rel.ro.local section. * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define. PR target/93111 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of comparison_operator in B and S integer comparisons. Likewise, use ordered_comparison_operator instead of cmpib_comparison_operator in cmpib patterns. * config/pa/predicates.md (cmpib_comparison_operator): Remove. 2020-01-01 Jakub Jelinek Update copyright years. * gcc.c (process_command): Update copyright notice dates. * gcov-dump.c (print_version): Ditto. * gcov.c (print_version): Ditto. * gcov-tool.c (print_version): Ditto. * gengtype.c (create_file): Ditto. * doc/cpp.texi: Bump @copying's copyright year. * doc/cppinternals.texi: Ditto. * doc/gcc.texi: Ditto. * doc/gccint.texi: Ditto. * doc/gcov.texi: Ditto. * doc/install.texi: Ditto. * doc/invoke.texi: Ditto. 2020-01-01 Jan Hubicka * ipa.c (walk_polymorphic_call_targets): Fix updating of overall summary. 2020-01-01 Jakub Jelinek PR tree-optimization/93098 * match.pd (popcount): For shift amounts, use integer_onep or wi::to_widest () == cst instead of tree_to_uhwi () == cst tests. Make sure that precision is power of two larger than or equal to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro instead of ULL suffixed constants. Formatting fixes. Copyright (C) 2020 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright notice and this notice are preserved.