diff options
author | Tom Stellard <tstellar@redhat.com> | 2017-08-08 05:52:00 +0000 |
---|---|---|
committer | Tom Stellard <tstellar@redhat.com> | 2017-08-08 05:52:00 +0000 |
commit | 56199e7135e10c344df07f1029b59903338e63e4 (patch) | |
tree | 4ce81d73094e22ad7a7ee53718cbecc1b5d4a5b5 | |
parent | 39aad0ab0821dc127da1f1278ce6f1bc249b5bbe (diff) |
AMDGPU: Fix warnings introduced by r310336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310337 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 6ecbe2743af..dfa26c871bc 100644 --- a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -383,7 +383,6 @@ static bool getConstantValue(SDValue N, uint32_t &Out) { } void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { - unsigned Opc = N->getOpcode(); EVT VT = N->getValueType(0); unsigned NumVectorElts = VT.getVectorNumElements(); EVT EltVT = VT.getVectorElementType(); @@ -420,7 +419,7 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { } if (NOps != NumVectorElts) { // Fill in the missing undef elements if this was a scalar_to_vector. - assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); + assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, EltVT); for (unsigned i = NOps; i < NumVectorElts; ++i) { @@ -481,7 +480,6 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) { case ISD::BUILD_VECTOR: { EVT VT = N->getValueType(0); unsigned NumVectorElts = VT.getVectorNumElements(); - EVT EltVT = VT.getVectorElementType(); if (VT == MVT::v2i16 || VT == MVT::v2f16) { if (Opc == ISD::BUILD_VECTOR) { @@ -498,7 +496,7 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) { break; } - assert(EltVT.bitsEq(MVT::i32)); + assert(VT.getVectorElementType().bitsEq(MVT::i32)); unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts); SelectBuildVector(N, RegClassID); return; |