[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table

Resolving fixup_riscv_call by assembler when the linker relaxation diabled
and the function and callsite within the same compile unit.

And also adding static_assert after Infos array declaration
to avoid missing any new fixup in MCFixupKindInfo in the future.

Differential Revision: https://reviews.llvm.org/D47126

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333487 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 41 insertions, 8 deletions

diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index a0ae4bc4df7..d8ea969da2f 100644
--- a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -74,7 +74,7 @@ public:
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
-    const static MCFixupKindInfo Infos[RISCV::NumTargetFixupKinds] = {
+    const static MCFixupKindInfo Infos[] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
       // RISCVFixupKinds.h.
       //
@@ -89,8 +89,11 @@ public:
       { "fixup_riscv_branch",        0,     32,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_rvc_jump",      2,     11,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_rvc_branch",    0,     16,  MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_riscv_call",          0,     64,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_relax",         0,      0,  0 }
     };
+    static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
+                  "Not all fixup kinds added to Infos array");
 
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
@@ -273,6 +276,14 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
     Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
     return Value;
   }
+  case RISCV::fixup_riscv_call: {
+    // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
+    // we need to add 0x800ULL before extract upper bits to reflect the
+    // effect of the sign extension.
+    uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
+    uint64_t LowerImm = Value & 0xfffULL;
+    return UpperImm | ((LowerImm << 20) << 32);
+  }
   case RISCV::fixup_riscv_rvc_jump: {
     // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
     unsigned Bit11  = (Value >> 11) & 0x1;
diff --git a/test/MC/RISCV/fixups.s b/test/MC/RISCV/fixups.s
index c76fca51e31..0f5432dd117 100644
--- a/test/MC/RISCV/fixups.s
+++ b/test/MC/RISCV/fixups.s
@@ -48,3 +48,25 @@ addi zero, zero, 0
 .set val, 0x12345678
 
 # CHECK-REL-NOT: R_RISCV
+
+# Testing the function call offset could resovled by assembler
+# when the function and the callsite within the same compile unit
+# and the linker relaxation is disabled.
+func:
+.fill 100
+call func
+# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
+# CHECK-INSTR: auipc   ra, 0
+# CHECK-INSTR: jalr    ra, ra, -100
+
+.fill 10000
+call func
+# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
+# CHECK-INSTR: auipc   ra, 1048574
+# CHECK-INSTR: jalr    ra, ra, -1916
+
+.fill 20888
+call func
+# CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call
+# CHECK-INSTR: auipc   ra, 1048568
+# CHECK-INSTR: jalr    ra, ra, 1764
diff --git a/test/MC/RISCV/function-call.s b/test/MC/RISCV/function-call.s
index d1a076efef4..05ae7abbb0c 100644
--- a/test/MC/RISCV/function-call.s
+++ b/test/MC/RISCV/function-call.s
@@ -11,12 +11,12 @@ call foo
 # RELOC: R_RISCV_CALL foo 0x0
 # INSTR: auipc ra, 0
 # INSTR: jalr  ra
-# FIXUP: fixup A - offset: 0, value: foo, kind:
+# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call
 call bar
 # RELOC: R_RISCV_CALL bar 0x0
 # INSTR: auipc ra, 0
 # INSTR: jalr  ra
-# FIXUP: fixup A - offset: 0, value: bar, kind:
+# FIXUP: fixup A - offset: 0, value: bar, kind: fixup_riscv_call
 
 # Ensure that calls to functions whose names coincide with register names work.
 
@@ -24,16 +24,16 @@ call zero
 # RELOC: R_RISCV_CALL zero 0x0
 # INSTR: auipc ra, 0
 # INSTR: jalr  ra
-# FIXUP: fixup A - offset: 0, value: zero, kind:
+# FIXUP: fixup A - offset: 0, value: zero, kind: fixup_riscv_call
 
 call f1
 # RELOC: R_RISCV_CALL f1 0x0
 # INSTR: auipc ra, 0
 # INSTR: jalr  ra
-# FIXUP: fixup A - offset: 0, value: f1, kind:
+# FIXUP: fixup A - offset: 0, value: f1, kind: fixup_riscv_call
 
 call ra
 # RELOC: R_RISCV_CALL ra 0x0
 # INSTR: auipc ra, 0
 # INSTR: jalr  ra
-# FIXUP: fixup A - offset: 0, value: ra, kind:
+# FIXUP: fixup A - offset: 0, value: ra, kind: fixup_riscv_call
diff --git a/test/MC/RISCV/linker-relaxation.s b/test/MC/RISCV/linker-relaxation.s
index 92cbe39c049..0184d174e90 100644
--- a/test/MC/RISCV/linker-relaxation.s
+++ b/test/MC/RISCV/linker-relaxation.s
@@ -19,8 +19,8 @@ call foo
 # NORELAX-RELOC-NOT: R_RISCV_RELAX
 # RELAX-RELOC: R_RISCV_CALL foo 0x0
 # RELAX-RELOC: R_RISCV_RELAX foo 0x0
-# RELAX-FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_relax
-# RELAX-FIXUP: fixup B - offset: 0, value: foo, kind:
+# RELAX-FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call
+# RELAX-FIXUP: fixup B - offset: 0, value: foo, kind: fixup_riscv_relax
 beq s1, s1, .L1
 # RELAX-RELOC: R_RISCV_BRANCH .L1 0x0
 # RELAX-FIXUP: fixup A - offset: 0, value: .L1, kind: fixup_riscv_branch