diff options
| author | wangyue <wangyue41@huawei.com> | 2017-03-18 09:04:12 +0800 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-04-06 17:47:49 +0100 |
| commit | 82d7ad24c1489ceb2a9443f8a72057ea516bd4f2 (patch) | |
| tree | e20c2ba8fe1fb9b86aad61ce4d209b87a4579ff9 | |
| parent | bb301e7ef8ce737046c1411c5720ced2249d7171 (diff) | |
Hisilicon/D02: fix IORT test issue in luvOS test
Luvos test report:
"FAILED [HIGH] IORTMemAttrInvalid: Test 1, IORT PCI Root Complex Node
Memory Attributes are illegal, CCA cannot be 1 if CPM is 0."
Reference to 《DEN0049B_IO_Remapping_Table》 3.1.1.4
Table13 and Table14:
“Note that if CCA is 0x1, CPM must also be 0x1.
Conversely, If CPM is 0x0 then CCA must be 0x0.”
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Signed-off-by: Chenhui Sun <chenhui.sun@linaro.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
| -rw-r--r-- | Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index bcd31d6..8f38359 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -205,8 +205,8 @@ Read Allocate : 0
Override : 0
[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 00
- Coherency : 0
+[0001] Memory Flags (decoded below) : 01
+ Coherency : 1
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000001
@@ -234,8 +234,8 @@ Read Allocate : 0
Override : 0
[0002] Reserved : 0000
-[0001] Memory Flags (decoded below) : 00
- Coherency : 0
+[0001] Memory Flags (decoded below) : 01
+ Coherency : 1
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000002
|