diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-04-07 14:24:04 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-04-12 10:46:05 +0100 |
| commit | cb796437ea816c578c3b933835bfa1dc15167c0f (patch) | |
| tree | 36d13e336449e2749f5443cb57a61b84f0adbb57 | |
| parent | 229a040b41a83577a5e72b5d3c83bb86040362f6 (diff) | |
Platforms/AMD: correct legacy PCI interrupt routing in DSDT
The _PRT method in the PCI0 object describes something that resembles
the legacy interrupt routing of the first slot only, but applies it to
all PCI-PCI bridges, which means the wrong interrupt is reported for
devices in slots 2 and 3. Since most devices support MSI, this is not
actually a big deal, but it would be nice to fix this nonetheless.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
| -rw-r--r-- | Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 63 |
1 files changed, 34 insertions, 29 deletions
diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl index 3bfa26a..4741bb4 100644 --- a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl @@ -508,40 +508,45 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
- Name (_PRT, Package (0x04) // _PRT: PCI Routing Table
+ Name (_PRT, Package () // _PRT: PCI Routing Table
{
- Package (0x04)
- {
- 0xFFFF,
- 0x00,
- 0x00,
- 0x0140
- },
+ // INTA of the bridge device itself
+ Package () { 0x2FFFF, 0x0, 0x0, 0x140 }
+ })
- Package (0x04)
+ Device (EXP1)
+ {
+ Name (_ADR, 0x20001) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
{
- 0xFFFF,
- 0x01,
- 0x00,
- 0x0141
- },
-
- Package (0x04)
+ Package () { 0xFFFF, 0x0, 0x0, 0x140 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x141 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x142 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x143 }
+ }) // _PRT
+ }
+ Device (EXP2)
+ {
+ Name (_ADR, 0x20002) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
{
- 0xFFFF,
- 0x02,
- 0x00,
- 0x0142
- },
-
- Package (0x04)
+ Package () { 0xFFFF, 0x0, 0x0, 0x144 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x145 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x146 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x147 }
+ }) // _PRT
+ }
+ Device (EXP3)
+ {
+ Name (_ADR, 0x20003) // _ADR: Address
+ Name (_PRT, Package () // _PRT: PCI Routing Table
{
- 0xFFFF,
- 0x03,
- 0x00,
- 0x0143
- }
- }) // _PRT
+ Package () { 0xFFFF, 0x0, 0x0, 0x148 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x149 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x14A },
+ Package () { 0xFFFF, 0x3, 0x0, 0x14B }
+ }) // _PRT
+ }
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
|