Switched to common mem defs between arm & aarch64

Signed-off-by: Greg Bellows <greg.bellows@linaro.org>

5 files changed, 9 insertions, 28 deletions

diff --git a/arm/Makefile b/arm/Makefile
index 38006f3..adbe6bd 100644
--- a/arm/Makefile
+++ b/arm/Makefile
@@ -12,7 +12,7 @@ CFLAGS += -DAARCH64
 
 $(BIOS_IMAGE): $(SEC_IMAGE) $(NSEC_IMAGE)
 	dd if=$(SEC_IMAGE) of=$@ 2> /dev/null
-	dd oflag=seek_bytes seek=65536 if=$(NSEC_IMAGE) of=$@ 2> /dev/null
+	dd oflag=seek_bytes seek=131072 if=$(NSEC_IMAGE) of=$@ 2> /dev/null
 	chmod +x $(BIOS_IMAGE)
 
 $(SEC_IMAGE):
diff --git a/arm/common/memory.h b/arm/common/memory.h
index ede6049..986b8df 100644
--- a/arm/common/memory.h
+++ b/arm/common/memory.h
@@ -7,16 +7,6 @@
 #define TnSZ (32-VA_SIZE)
 #define STACK_SIZE 0x40000
 
-/* NORFLASH0 on Vexpress aseries (a15) is mapped from 0x08000000 to 0x0A000000
- * which is 32MB.  It is also aliased to 0x0 (to 0x2000000).
- * It is acceptable to have the text here as it is RO.
- */
-#define FLASH_SEC_BASE 0x00000000
-#define FLASH_NSEC_BASE 0x00010000
-
-#define RAM_SEC_BASE 0x40000000
-#define RAM_NSEC_BASE 0x48000000
-
 #define EL3_FLASH_BASE FLASH_BASE
 #define EL3_RAM_BASE RAM_BASE
 #define EL3_RAM_SIZE (512*1024)
@@ -26,17 +16,8 @@
 #define EL3_STACK_SIZE STACK_SIZE
 #define EL3_STACK_BASE 0xFF00000000
 
-#define EL1_S_FLASH_BASE (FLASH_BASE+0x10000)
-#define EL1_S_RAM_BASE (RAM_BASE+0x1000000)
-#define EL1_S_RAM_SIZE (512*1024)
-#define EL1_S_BASE_VA 0xC000000000
-#define EL1_S_PGTBL_SIZE 0x40000
-#define EL1_S_PGTBL_BASE EL1_S_RAM_BASE+EL1_S_RAM_SIZE-EL1_S_PGTBL_SIZE
-#define EL1_S_STACK_SIZE STACK_SIZE
-#define EL1_S_STACK_BASE 0xCF00000000
-
 #define EL1_NS_FLASH_BASE (FLASH_BASE+0x20000)
-#define EL1_NS_RAM_BASE (RAM_BASE+0x2000000)
+#define EL1_NS_RAM_BASE (RAM_BASE+0x8000000)
 #define EL1_NS_RAM_SIZE (512*1024)
 #define EL1_NS_BASE_VA 0x80000000
 #define EL1_NS_PGTBL_SIZE 0x40000
diff --git a/arm/nonsecure/tztest_nonsecure.lds.S b/arm/nonsecure/tztest_nonsecure.lds.S
index 45e33ea..472141c 100644
--- a/arm/nonsecure/tztest_nonsecure.lds.S
+++ b/arm/nonsecure/tztest_nonsecure.lds.S
@@ -20,9 +20,9 @@ TARGET(binary)
 
 SECTIONS
 {
- . = FLASH_NSEC_BASE;
+ . = EL1_NS_FLASH_BASE;
  _flash_nsectext_start = .;
- . = RAM_NSEC_BASE;
+ . = EL1_NS_RAM_BASE;
  _ram_nsec_base = .;
  _ram_nsectext_start = .;
  .text : AT ( _flash_nsectext_start ) { *(.text); }
diff --git a/arm/secure/tzboot.S b/arm/secure/tzboot.S
index be66323..ba284a0 100644
--- a/arm/secure/tzboot.S
+++ b/arm/secure/tzboot.S
@@ -81,13 +81,13 @@ copy_secdata:
     /* Branch to the nonsecure image base.  It should be set-up so that this is
      * the image loader which returns the starting execution point.
      */
-    mov r0, #FLASH_NSEC_BASE
+    mov r0, #EL1_NS_FLASH_BASE
     blx r0
 
     /* Branch to the starting point of the secure image in RAM which should
      * kick off initialization.
      */
-    mov r1, #RAM_SEC_BASE
+    mov r1, #EL3_RAM_BASE
     bx r1
 
     /* We shouldn't get here as the secure image will shutdown */
diff --git a/arm/secure/tztest_secure.lds.S b/arm/secure/tztest_secure.lds.S
index 0cbb783..4ed2288 100644
--- a/arm/secure/tztest_secure.lds.S
+++ b/arm/secure/tztest_secure.lds.S
@@ -13,16 +13,16 @@ TARGET(binary)
 
 #include "memory.h"
 
-_ram_nsec_base = RAM_NSEC_BASE;
+_ram_nsec_base = EL1_NS_RAM_BASE;
 
 SECTIONS
 {
-	. = FLASH_SEC_BASE;
+	. = EL3_FLASH_BASE;
 	.boot : { tzboot.o }
 	_eboot = .;
 
 	_flash_secvecs_start = .;
-	. = RAM_SEC_BASE;
+	. = EL3_RAM_BASE;
 	_ram_sec_base = .;
 
 	/* We separate out the secure vector table and level 1 handlers, so we