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authorEugeni Dodonov <eugeni.dodonov@intel.com>2012-01-07 23:40:35 -0200
committerKeith Packard <keithp@keithp.com>2012-01-09 14:17:53 -0800
commit07c1e8c1462fa7324de4c36ae9e55da2abd79cee (patch)
treea63b70ca032659120000821247115a502dd49f7d
parent5e5b7fa2ad84f7806d0c7f5af8e1440bc91b4ec7 (diff)
drm/i915: handle 3rd pipe
We don't need to check 3rd pipe specifically, as it shares PLL with some other one. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index c0b945cdcd9..30d924f447c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -35,6 +35,10 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
struct drm_i915_private *dev_priv = dev->dev_private;
u32 dpll_reg;
+ /* On IVB, 3rd pipe shares PLL with another one */
+ if (pipe > 1)
+ return false;
+
if (HAS_PCH_SPLIT(dev))
dpll_reg = PCH_DPLL(pipe);
else