diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-04-02 16:10:09 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-04-05 20:47:20 +0200 |
| commit | 9c8e09b7a551fc81842a2d9cdc3e42a5b729820f (patch) | |
| tree | bb3d1dd24b775960ab4dc554ce93e7f56e37d536 | |
| parent | 84b046f3985357a040721affebff8603264d793e (diff) | |
drm/i915: Set PIPECONF color range bit on Valleyview
VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: fixup rebase issues due to slightly different baseline.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7f860c6b266..b7005640144 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4583,6 +4583,13 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) else pipeconf |= PIPECONF_PROGRESSIVE; + if (IS_VALLEYVIEW(dev)) { + if (intel_crtc->config.limited_color_range) + pipeconf |= PIPECONF_COLOR_RANGE_SELECT; + else + pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT; + } + I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); POSTING_READ(PIPECONF(intel_crtc->pipe)); } |