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authorstanley cai <stanley.w.cai@com.rmk.(none)>2006-10-16 15:13:43 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-11-30 12:24:47 +0000
commit127e477e0cd8da4d3058709ab2dc7b92dccbcba5 (patch)
treefb179df1ba09697af102beddcb5485b0774f3ca9
parentd94cffe3d3794f70f928c3e5b97c252930775332 (diff)
[ARM] 3894/1: pxa27x: Update DCSR_EORINTR bit definition in DCSR
This patch updates a bit definition name to align with the PXA27x spec.EORINTR(End-Of-Receive Intr) bit in DCSR register (DMA Channel Control/Status Register) Signed-off-by: Stanley Cai <stanley.w.cai@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 9b82531e4b5..083e03c5639 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
-#define DCSR_ENRINTR (1 << 9) /* The end of Receive */
+#define DCSR_EORINTR (1 << 9) /* The end of Receive */
#endif
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */