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| author | Nicolas Pitre <nicolas.pitre@linaro.org> | 2012-06-13 09:19:05 -0400 |
|---|---|---|
| committer | Jon Medhurst <tixy@linaro.org> | 2013-04-29 09:43:22 +0100 |
| commit | eedf05bea83c12b323719560bfa42c10491d9b4e (patch) | |
| tree | 6d6cd4627cfbf33561079b989d028f5793de554d | |
| parent | 31d74d48627957a76ae9fa2484ffe0d61e16c105 (diff) | |
ARM: b.L: assume aliasing I-cache
To deal with the I-cache discrepancy between Cortex-A15 and Cortex-A7,
let's assume aliasing I-cache in both cases.
Note: this might need to be refined i.e. detect a big.LITTLE system
somehow by probing all CPUs not only the boot one.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
| -rw-r--r-- | arch/arm/kernel/setup.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 234e339196c..f44e249154a 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -260,6 +260,19 @@ static int cpu_has_aliasing_icache(unsigned int arch) int aliasing_icache; unsigned int id_reg, num_sets, line_size; +#ifdef CONFIG_BIG_LITTLE + /* + * We expect a combination of Cortex-A15 and Cortex-A7 cores. + * A7 = VIPT aliasing I-cache + * A15 = PIPT (non-aliasing) I-cache + * To cater for this discrepancy, let's assume aliasing I-cache + * all the time. This means unneeded extra work on the A15 but + * only ptrace is affected which is not performance critical. + */ + if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc0f0) + return 1; +#endif + /* PIPT caches never alias. */ if (icache_is_pipt()) return 0; |