diff options
| author | Rob Herring <rob.herring@calxeda.com> | 2012-06-11 21:32:14 -0500 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-06-27 09:01:29 -0300 |
| commit | 69154d069869b612383cef9d594f39b34ffba6dd (patch) | |
| tree | ca356af0247ba18c0ffb1c00d9519530d2347832 /Documentation/devicetree/bindings/arm/calxeda | |
| parent | a1b01edb274518c7da6d69b84e7558c092282aad (diff) | |
edac: add support for Calxeda highbank L2 cache ecc
Add support for L2 ECC on Calxeda highbank platform.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/calxeda')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt new file mode 100644 index 00000000000..94e642a33db --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt @@ -0,0 +1,15 @@ +Calxeda Highbank L2 cache ECC + +Properties: +- compatible : Should be "calxeda,hb-sregs-l2-ecc" +- reg : Address and size for ECC error interrupt clear registers. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. + +Example: + + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4 0 72 4>; + }; |