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authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2013-06-06 10:59:23 +0100
committerJon Medhurst <tixy@linaro.org>2013-07-01 11:04:57 +0100
commitaf17603909e9e54771741e30bfacf2a718d901ca (patch)
tree095c628d454db16bf7986d4238c6dc0859db7f02 /Documentation
parent854f623384031939e66b1b838e7c332a9da2aac5 (diff)
drivers: mfd: vexpress: add Serial Power Controller (SPC) support
The TC2 versatile express core tile integrates a logic block that provides the interface between the dual cluster test-chip and the M3 microcontroller that carries out power management. The logic block, called Serial Power Controller (SPC), contains several memory mapped registers to control among other things low-power states, operating points and reset control. This patch provides a driver that enables run-time control of features implemented by the SPC control logic. The driver also provides a bridge interface through the vexpress config infrastructure. Operations allowing to read/write operating points are made to go via the same interface as configuration transactions so that all requests to M3 are serialized. Device tree bindings documentation for the SPC component is provided with the patchset. Cc: Samuel Ortiz <sameo@linux.intel.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Jon Medhurst <tixy@linaro.org> Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/mfd/vexpress-spc.txt35
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mfd/vexpress-spc.txt b/Documentation/devicetree/bindings/mfd/vexpress-spc.txt
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+* ARM Versatile Express Serial Power Controller device tree bindings
+
+Latest ARM development boards implement a power management interface (serial
+power controller - SPC) that is capable of managing power/voltage and
+operating point transitions, through memory mapped registers interface.
+
+On testchips like TC2 it also provides a configuration interface that can
+be used to read/write values which cannot be read/written through simple
+memory mapped reads/writes.
+
+- spc node
+
+ - compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be
+ "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc"
+ - reg:
+ Usage: required
+ Value type: <prop-encode-array>
+ Definition: A standard property that specifies the base address
+ and the size of the SPC address space
+ - interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: SPC interrupt configuration. A standard property
+ that follows ePAPR interrupts specifications
+
+Example:
+
+spc: spc@7fff0000 {
+ compatible = "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc";
+ reg = <0 0x7FFF0000 0 0x1000>;
+ interrupts = <0 95 4>;
+};