diff options
| author | Nicolas Pitre <nicolas.pitre@linaro.org> | 2012-11-29 16:37:51 -0500 |
|---|---|---|
| committer | Jon Medhurst <tixy@linaro.org> | 2013-04-29 09:42:50 +0100 |
| commit | cf2fea8ca44ba4f52942b53a6933ff898a69f4fc (patch) | |
| tree | 6e61722b694cda9d14bb0d9c901014201a21c52e /arch/arm/boot | |
| parent | 58ca1e1d25deb9278ff6a356f62ae617e6dec0e1 (diff) | |
ARM: RTSM: add DCSCB address definition to ca15x*-ca7x* .dts files
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts index cbec3de46d1..9f5683fe48b 100644 --- a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts +++ b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts @@ -94,6 +94,11 @@ reg = <0 0x2c090000 0 0x8000>; }; + dcscb@60000000 { + compatible = "arm,dcscb"; + reg = <0 0x60000000 0 0x1000>; + }; + gic: interrupt-controller@2c001000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts index 1b7de69a4b5..ba02441f070 100644 --- a/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts +++ b/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts @@ -172,6 +172,11 @@ reg = <0 0x2c090000 0 0x8000>; }; + dcscb@60000000 { + compatible = "arm,dcscb"; + reg = <0 0x60000000 0 0x1000>; + }; + gic: interrupt-controller@2c001000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; |