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authorDave Martin <dave.martin@linaro.org>2012-12-12 18:13:44 +0000
committerAndrey Konovalov <andrey.konovalov@linaro.org>2013-05-25 13:22:44 +0400
commitda0a0ae272e5c117f43da3522a01a28219ca9a31 (patch)
tree460f7484f43657867e84d5a809e2016744876953 /arch/arm/kernel/perf_event_cpu.c
parentb115c4933bebff32c29da495cd0c8ade248548c3 (diff)
ARM: perf: [WIP] Manipulate the right shadow register for PM*CLR
Where the ARM Architecture exposes PM*SET and PM*CLR, these really manipulate the same underlying register. This patch uses the PM*SET register for storing the logical state when the PMU is not active, and mainpulates that state when the code attempts to access the corresponding PM*CLR register. PMOVSR is a special case: this is a reset-only register, so the logical copy of PMOVSR is always used. These changes result a small number of unused fields in the armv7_pmu_logical_state structre. For now, this is considered to be harmless -- it may be tidied up later. Signed-off-by: Dave Martin <dave.martin@linaro.org>
Diffstat (limited to 'arch/arm/kernel/perf_event_cpu.c')
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