diff options
| author | Will Deacon <will.deacon@arm.com> | 2013-01-16 12:01:59 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2013-01-16 12:01:59 +0000 |
| commit | 40c390c768f898497e17d934f6715d516ff67294 (patch) | |
| tree | 87f49311dfb80e19d790fa76f97ceed0536e7628 /arch/arm/kernel/perf_event_xscale.c | |
| parent | 1764c591dfed2ce7075465df0591ce9564ff37a1 (diff) | |
ARM: perf: don't pretend to support counting of L1I writes
ARM has a harvard cache architecture and cannot write directly to the
I-side.
This patch removes the L1I write events from the cache map (which
previously returned *read* events in many cases).
Reported-by: Mike Williams <michael.williams@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/perf_event_xscale.c')
| -rw-r--r-- | arch/arm/kernel/perf_event_xscale.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 2b0fe30ec12..63990c42fac 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, |