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authorJon Medhurst <tixy@linaro.org>2013-05-09 14:07:03 +0100
committerJon Medhurst <tixy@linaro.org>2013-05-09 14:07:03 +0100
commitc5b970dd2f809ce3675902f672a1d676aed43c7a (patch)
tree89311b14d29ab1d8ea2966e22941ac5b2214db25 /arch/arm/kernel/setup.c
parent3bc528d32c5c98a496c3473353e701a6e23c0cb3 (diff)
parent892404cc9460bdc9156ec0ca3ac27c6f20539213 (diff)
Merge branch 'tracking-armlt-tc2-pm' into lsk-3.9-vexpress
Conflicts: arch/arm/mach-vexpress/Kconfig arch/arm/mach-vexpress/Makefile
Diffstat (limited to 'arch/arm/kernel/setup.c')
-rw-r--r--arch/arm/kernel/setup.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 166e427ed2b..3f0d5e969ef 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -260,6 +260,19 @@ static int cpu_has_aliasing_icache(unsigned int arch)
int aliasing_icache;
unsigned int id_reg, num_sets, line_size;
+#ifdef CONFIG_BIG_LITTLE
+ /*
+ * We expect a combination of Cortex-A15 and Cortex-A7 cores.
+ * A7 = VIPT aliasing I-cache
+ * A15 = PIPT (non-aliasing) I-cache
+ * To cater for this discrepancy, let's assume aliasing I-cache
+ * all the time. This means unneeded extra work on the A15 but
+ * only ptrace is affected which is not performance critical.
+ */
+ if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc0f0)
+ return 1;
+#endif
+
/* PIPT caches never alias. */
if (icache_is_pipt())
return 0;