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authorJames Bottomley <JBottomley@Parallels.com>2013-06-26 23:08:22 -0700
committerJames Bottomley <JBottomley@Parallels.com>2013-06-26 23:08:22 -0700
commita9e94ec3504ead4b87a929bc57f5aa99a6590437 (patch)
treeb6e7aaec0e844dc066e93296a85e5769542ef525 /arch/arm/mach-mvebu/coherency_ll.S
parent36a279686bc02d340eb213a9f2a0b67e50de64b4 (diff)
parent2884d4230867c8a46cf701214051e923301e7429 (diff)
Merge tag 'fcoe1' into fixes
This patch fixes a critical bug that was introduced in 3.9 related to VLAN tagging FCoE frames.
Diffstat (limited to 'arch/arm/mach-mvebu/coherency_ll.S')
-rw-r--r--arch/arm/mach-mvebu/coherency_ll.S16
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391192c..5476669ba90 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent)
/* Add CPU to SMP group - Atomic */
add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
- ldr r2, [r3]
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
/* Enable coherency on CPU - Atomic */
- add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET
- ldr r2, [r3]
+ add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
dsb