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authorPaul Walmsley <paul@pwsan.com>2009-01-28 12:08:14 -0700
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 17:50:33 +0000
commitb8168d1e3989bc141da6bba87ad49e218ff04658 (patch)
tree7eabca71f38410867174acb06aa2e2013701ac47 /arch/arm/mach-omap2/clock34xx.h
parentf0587b63c24e0c7539c6e77f1bfc68e6053608c7 (diff)
[ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this into the OMAP3 clock framework. linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r--arch/arm/mach-omap2/clock34xx.h20
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9dec69860ba..f8088c0ec01 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1060,8 +1060,15 @@ static struct clk corex2_fck = {
/* DPLL power domain clock controls */
-static const struct clksel div2_core_clksel[] = {
- { .parent = &core_ck, .rates = div2_rates },
+static const struct clksel_rate div4_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 0 }
+};
+
+static const struct clksel div4_core_clksel[] = {
+ { .parent = &core_ck, .rates = div4_rates },
{ .parent = NULL }
};
@@ -1076,7 +1083,7 @@ static struct clk dpll1_fck = {
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
- .clksel = div2_core_clksel,
+ .clksel = div4_core_clksel,
.flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -1151,7 +1158,7 @@ static struct clk dpll2_fck = {
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
- .clksel = div2_core_clksel,
+ .clksel = div4_core_clksel,
.flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -1187,6 +1194,11 @@ static struct clk iva2_ck = {
/* Common interface clocks */
+static const struct clksel div2_core_clksel[] = {
+ { .parent = &core_ck, .rates = div2_rates },
+ { .parent = NULL }
+};
+
static struct clk l3_ick = {
.name = "l3_ick",
.ops = &clkops_null,