aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-shmobile/intc-r8a7779.c
diff options
context:
space:
mode:
authorSimon Horman <horms+renesas@verge.net.au>2013-01-29 14:21:46 +0900
committerSimon Horman <horms+renesas@verge.net.au>2013-03-13 02:13:18 +0900
commitc58a1545e39ed1ff54dd2c167d3d25ae62c0dbd3 (patch)
tree6154acc9a50fe7112b3be8479794dc70fc541aa1 /arch/arm/mach-shmobile/intc-r8a7779.c
parentdf2ddd7b9b781f0aee7fc90e6bed21e62ebf7564 (diff)
ARM: mach-shmobile: r8a7779: Allow initialisation of GIC by DT
This allows the GIC interrupt controller of the r8a7779 SoC to be initialised using a flattened device tree blob. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v3 * Fix copy-paste error and use unique reg values for each CPU v2 As suggested by Mark Rutland * Add reg and device_type to cpus * Remove #address-cells from gic
Diffstat (limited to 'arch/arm/mach-shmobile/intc-r8a7779.c')
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c27
1 files changed, 21 insertions, 6 deletions
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 8807c27f71f..f9cc4bc9c79 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
+#include <linux/irqchip.h>
#include <mach/intc.h>
#include <mach/r8a7779.h>
#include <asm/mach-types.h>
@@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
return 0; /* always allow wakeup */
}
-void __init r8a7779_init_irq(void)
+static void __init r8a7779_init_irq_common(void)
{
- void __iomem *gic_dist_base = IOMEM(0xf0001000);
- void __iomem *gic_cpu_base = IOMEM(0xf0000100);
-
- /* use GIC to handle interrupts */
- gic_init(0, 29, gic_dist_base, gic_cpu_base);
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
/* route all interrupts to ARM */
@@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void)
__raw_writel(0xbffffffc, INT2SMSKCR3);
__raw_writel(0x003fee3f, INT2SMSKCR4);
}
+
+void __init r8a7779_init_irq(void)
+{
+ void __iomem *gic_dist_base = IOMEM(0xf0001000);
+ void __iomem *gic_cpu_base = IOMEM(0xf0000100);
+
+ /* use GIC to handle interrupts */
+ gic_init(0, 29, gic_dist_base, gic_cpu_base);
+
+ r8a7779_init_irq_common();
+}
+
+#ifdef CONFIG_OF
+void __init r8a7779_init_irq_dt(void)
+{
+ irqchip_init();
+ r8a7779_init_irq_common();
+}
+#endif