diff options
| author | Joseph Lo <josephl@nvidia.com> | 2012-11-13 10:04:48 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-11-15 15:09:22 -0700 |
| commit | 29a0e7beab8e05be53d5b9c050253a4dc417041e (patch) | |
| tree | eddaa429e909f209cb0628b0733e0ade8e277fd0 /arch/arm/mach-tegra/headsmp.S | |
| parent | d552920a02759cdc45d8507868de10ac2f5b9a18 (diff) | |
ARM: tegra: retain L2 content over CPU suspend/resume
The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable L2 before
the MMU is enabled. But the L2 controller is in the same power domain
with the CPU cluster. We need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/headsmp.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 82dc84b6b86..4a317fae686 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -2,6 +2,8 @@ #include <linux/init.h> #include <asm/cache.h> +#include <asm/asm-offsets.h> +#include <asm/hardware/cache-l2x0.h> #include "flowctrl.h" #include "iomap.h" @@ -113,10 +115,19 @@ ENTRY(tegra_resume) str r1, [r0] #endif + /* L2 cache resume & re-enable */ + l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr + b cpu_resume ENDPROC(tegra_resume) #endif +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_saved_regs_addr +l2x0_saved_regs_addr: + .long 0 +#endif + .align L1_CACHE_SHIFT ENTRY(__tegra_cpu_reset_handler_start) |