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authorStany MARCEL <stany.marcel@novasys-ingenierie.com>2012-10-16 15:26:11 +1000
committerGreg Ungerer <gerg@uclinux.org>2013-04-29 09:17:57 +1000
commita4eff487da4e4e55a15da2a8e8769151b1881a95 (patch)
treed7cf81c84869f51554cd1b2e93f66a6a72cb5e04 /arch/m68k
parente4ba4fc2b98f659f525d02721643a01015a8e3ed (diff)
m68k: Set ColdFire ACR1 cache mode depending on kernel configuration
For coldfire with MMU enabled, data cache did not follow the configuration but was configured in writethrough mode. Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/m54xxacr.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 192bbfeabf7..6d13cae44af 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -96,8 +96,13 @@
*/
#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
+#if defined(CONFIG_CACHE_COPYBACK)
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
- ACR_ENABLE+ACR_SUPER+ACR_SP)
+ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
+#else
+#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
+ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
+#endif
#define ACR2_MODE 0
#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP)