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authorRichard Retanubun <RichardRetanubun@RuggedCom.com>2009-04-08 11:51:27 +1000
committerGreg Ungerer <gerg@uclinux.org>2009-04-22 14:45:07 +1000
commit592578a1dd1be0c940e36f769acdd3cc6651a7a1 (patch)
treef91e06fd511870f19eb61f3cca3af3ef3f41d90b /arch/m68knommu
parentccc5ff94c66e628d3c501b26ace5d4339667715d (diff)
m68knommu: Fixed GPIO pin initialization for CONFIG_M5271 FEC.
This processor only have one FEC and its MDIO pins are located at a different offset than the code used for the current CONFIG_M527x. Tesed on M5271EVB eval platform. Without this patch the FEC driver will report no PHY attached if the bootloader does not pre-initialize the PAR_FECI2C GPIO register. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/platform/527x/config.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c
index 49343fb157b..428b15922ef 100644
--- a/arch/m68knommu/platform/527x/config.c
+++ b/arch/m68knommu/platform/527x/config.c
@@ -189,10 +189,15 @@ static void __init m527x_fec_init(void)
m527x_fec_irq_init(0);
/* Set multi-function pins to ethernet mode for fec0 */
+#if defined(CONFIG_M5271)
+ v = readb(MCF_IPSBAR + 0x100047);
+ writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+#else
par = readw(MCF_IPSBAR + 0x100082);
writew(par | 0xf00, MCF_IPSBAR + 0x100082);
v = readb(MCF_IPSBAR + 0x100078);
writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+#endif
#ifdef CONFIG_FEC2
m527x_fec_irq_init(1);