diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-03-02 07:44:16 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-03-02 07:44:16 -0800 |
commit | aebb2afd5420c860b7fbc3882a323ef1247fbf16 (patch) | |
tree | 05ee0efcebca5ec421de44de7a6d6271088c64a8 /arch/mips/include/asm/mach-pnx8550/glb.h | |
parent | 8eae508b7c6ff502a71d0293b69e97c5505d5840 (diff) | |
parent | edb15d83a875a1f4b1576188844db5c330c3267d (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
o Add basic support for the Mediatek/Ralink Wireless SoC family.
o The Qualcomm Atheros platform is extended by support for the new
QCA955X SoC series as well as a bunch of patches that get the code
ready for OF support.
o Lantiq and BCM47XX platform have a few improvements and bug fixes.
o MIPS has sent a few patches that get the kernel ready for the
upcoming microMIPS support.
o The rest of the series is made up of small bug fixes and cleanups
that relate to various parts of the MIPS code. The biggy in there is
a whitespace cleanup. After I was sent another set of whitespace
cleanup patches I decided it was the time to clean the whitespace
"issues" for once and and that touches many files below arch/mips/.
Fix up silly conflicts, mostly due to whitespace cleanups.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits)
MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h
MIPS: remove broken conditional inside vpe loader code
MIPS: SMTC: fix implicit declaration of set_vi_handler
MIPS: early_printk: drop __init annotations
MIPS: Probe for and report hardware virtualization support.
MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board
MIPS: ath79: add USB controller registration code for the QCA955X SoCs
MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
MIPS: ath79: add WMAC registration code for the QCA955X SoCs
MIPS: ath79: register UART for the QCA955X SoCs
MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}
MIPS: ath79: add GPIO setup code for the QCA955X SoCs
MIPS: ath79: add IRQ handling code for the QCA955X SoCs
MIPS: ath79: add clock setup code for the QCA955X SoCs
MIPS: ath79: add SoC detection code for the QCA955X SoCs
MIPS: ath79: add early printk support for the QCA955X SoCs
MIPS: ath79: fix WMAC IRQ resource assignment
mips: reserve elfcorehdr
mips: Make sure kernel memory is in iomem
MIPS: ath79: use dynamically allocated USB platform devices
...
Diffstat (limited to 'arch/mips/include/asm/mach-pnx8550/glb.h')
-rw-r--r-- | arch/mips/include/asm/mach-pnx8550/glb.h | 86 |
1 files changed, 0 insertions, 86 deletions
diff --git a/arch/mips/include/asm/mach-pnx8550/glb.h b/arch/mips/include/asm/mach-pnx8550/glb.h deleted file mode 100644 index 07aa85e609b..00000000000 --- a/arch/mips/include/asm/mach-pnx8550/glb.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * PNX8550 global definitions - * - * Author: source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ - -#ifndef __PNX8550_GLB_H -#define __PNX8550_GLB_H - -#define PNX8550_GLB1_BASE 0xBBE63000 -#define PNX8550_GLB2_BASE 0xBBE4d000 -#define PNX8550_RESET_BASE 0xBBE60000 - -/* PCI Inta Output Enable Registers */ -#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050) - -/* Bit 1:Enable DAC Powerdown - 0:DACs are enabled and are working normally - 1:DACs are powerdown -*/ -#define PNX8550_GLB_DAC_PD 0x2 -/* Bit 0:Enable of PCI inta output - 0 = Disable PCI inta output - 1 = Enable PCI inta output -*/ -#define PNX8550_GLB_ENABLE_INTA_O 0x1 - -/* PCI Direct Mappings */ -#define PNX8550_PCIMEM 0x12000000 -#define PNX8550_PCIMEM_SIZE 0x08000000 -#define PNX8550_PCIIO 0x1c000000 -#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */ - -#define PNX8550_PORT_BASE KSEG1 - -// GPIO def -#define PNX8550_GPIO_BASE 0x1Be00000 - -#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500) -#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004) -#define PNX8550_GPIO_MC_31_BIT 30 -#define PNX8550_GPIO_MC_30_BIT 28 -#define PNX8550_GPIO_MC_29_BIT 26 -#define PNX8550_GPIO_MC_28_BIT 24 -#define PNX8550_GPIO_MC_27_BIT 22 -#define PNX8550_GPIO_MC_26_BIT 20 -#define PNX8550_GPIO_MC_25_BIT 18 -#define PNX8550_GPIO_MC_24_BIT 16 -#define PNX8550_GPIO_MC_23_BIT 14 -#define PNX8550_GPIO_MC_22_BIT 12 -#define PNX8550_GPIO_MC_21_BIT 10 -#define PNX8550_GPIO_MC_20_BIT 8 -#define PNX8550_GPIO_MC_19_BIT 6 -#define PNX8550_GPIO_MC_18_BIT 4 -#define PNX8550_GPIO_MC_17_BIT 2 -#define PNX8550_GPIO_MC_16_BIT 0 - -#define PNX8550_GPIO_MODE_PRIMOP 0x1 -#define PNX8550_GPIO_MODE_NO_OPENDR 0x2 -#define PNX8550_GPIO_MODE_OPENDR 0x3 - -// RESET module -#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0) -#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4) -#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8) - -#define PNX8550_RST_REL_MIPS_RST_N 0x8 -#define PNX8550_RST_DO_SW_RST 0x4 -#define PNX8550_RST_REL_SYS_RST_OUT 0x2 -#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1 -#endif |