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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-26 19:46:23 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-26 19:46:23 -0800
commita9a07d40bc9c57881555b64fe8bf66fd28e2f13a (patch)
tree20c08b4e6756db92bf7720d5ca1af67b83430828 /arch/openrisc
parent2003cd90c473f66d34114bc61c49e7d74d370894 (diff)
parent160d83781a32e94a1e337efd6722939001e62398 (diff)
Merge branch 'for-upstream' of git://openrisc.net/jonas/linux
Pull OpenRISC updates from Jonas Bonn: "An equal number of bug fixes and trivial cleanups; no new features. - Two patches to fix errors thrown by the updated toolchain. - Three other bug fixes. - Four trivial cleanups." * 'for-upstream' of git://openrisc.net/jonas/linux: openrisc: add missing header inclusion openrisc: really pass correct arg to schedule_tail Add bitops include needed for ext2 filesystem openrisc: update DTLB-miss handler last openrisc: fix up vmalloc page table loading openrisc idle: delete pm_idle openrisc: remove CONFIG_SYMBOL_PREFIX openrisc: avoid using function parameter regs in reset vector openrisc: remove unused current_regs
Diffstat (limited to 'arch/openrisc')
-rw-r--r--arch/openrisc/Kconfig4
-rw-r--r--arch/openrisc/include/asm/bitops.h1
-rw-r--r--arch/openrisc/include/asm/processor.h1
-rw-r--r--arch/openrisc/kernel/entry.S16
-rw-r--r--arch/openrisc/kernel/head.S13
-rw-r--r--arch/openrisc/mm/init.c17
6 files changed, 34 insertions, 18 deletions
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 0ac66f67521..35a4e5f6e71 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -26,10 +26,6 @@ config OPENRISC
config MMU
def_bool y
-config SYMBOL_PREFIX
- string
- default ""
-
config HAVE_DMA_ATTRS
def_bool y
diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
index a9e11efae14..2c64f2228dc 100644
--- a/arch/openrisc/include/asm/bitops.h
+++ b/arch/openrisc/include/asm/bitops.h
@@ -54,6 +54,7 @@
#include <asm-generic/bitops/atomic.h>
#include <asm-generic/bitops/non-atomic.h>
+#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic.h>
#endif /* __ASM_GENERIC_BITOPS_H */
diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h
index 33691380608..cab746fa9e8 100644
--- a/arch/openrisc/include/asm/processor.h
+++ b/arch/openrisc/include/asm/processor.h
@@ -70,7 +70,6 @@ struct thread_struct {
*/
#define task_pt_regs(task) user_regs(task_thread_info(task))
-#define current_regs() user_regs(current_thread_info())
#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index 54afd0a129f..d8a455ede5a 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -201,12 +201,17 @@ EXCEPTION_ENTRY(_bus_fault_handler)
l.nop
/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
+EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
+ l.and r5,r5,r0
+ l.j 1f
+ l.nop
EXCEPTION_ENTRY(_data_page_fault_handler)
/* set up parameters for do_page_fault */
+ l.ori r5,r0,0x300 // exception vector
+1:
l.addi r3,r1,0 // pt_regs
/* r4 set be EXCEPTION_HANDLE */ // effective address of fault
- l.ori r5,r0,0x300 // exception vector
/*
* __PHX__: TODO
@@ -276,12 +281,17 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
l.nop
/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
+EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
+ l.and r5,r5,r0
+ l.j 1f
+ l.nop
EXCEPTION_ENTRY(_insn_page_fault_handler)
/* set up parameters for do_page_fault */
+ l.ori r5,r0,0x400 // exception vector
+1:
l.addi r3,r1,0 // pt_regs
/* r4 set be EXCEPTION_HANDLE */ // effective address of fault
- l.ori r5,r0,0x400 // exception vector
l.ori r6,r0,0x0 // !write access
/* call fault.c handler in or32/mm/fault.c */
@@ -1040,7 +1050,7 @@ ENTRY(_switch)
* we are expected to have set up the arg to schedule_tail already,
* hence we do so here unconditionally:
*/
- l.lwz r3,TI_STACK(r3) /* Load 'prev' as schedule_tail arg */
+ l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
l.jr r9
l.nop
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1088b5fca3b..1d3c9c28ac2 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -19,6 +19,7 @@
#include <linux/threads.h>
#include <linux/errno.h>
#include <linux/init.h>
+#include <linux/serial_reg.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
@@ -291,9 +292,9 @@
/* Jump to .init code at _start which lives in the .head section
* and will be discarded after boot.
*/
- LOAD_SYMBOL_2_GPR(r4, _start)
- tophys (r3,r4) /* MMU disabled */
- l.jr r3
+ LOAD_SYMBOL_2_GPR(r15, _start)
+ tophys (r13,r15) /* MMU disabled */
+ l.jr r13
l.nop
/* ---[ 0x200: BUS exception ]------------------------------------------- */
@@ -1069,8 +1070,7 @@ d_pte_not_present:
EXCEPTION_LOAD_GPR4
EXCEPTION_LOAD_GPR5
EXCEPTION_LOAD_GPR6
- l.j _dispatch_do_dpage_fault
- l.nop
+ EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
/* ==============================================[ ITLB miss handler ]=== */
ENTRY(itlb_miss_handler)
@@ -1192,8 +1192,7 @@ i_pte_not_present:
EXCEPTION_LOAD_GPR4
EXCEPTION_LOAD_GPR5
EXCEPTION_LOAD_GPR6
- l.j _dispatch_do_ipage_fault
- l.nop
+ EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
/* ==============================================[ boot tlb handlers ]=== */
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index 79dea9740a3..e7fdc50c4bf 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -167,15 +167,26 @@ void __init paging_init(void)
unsigned long *dtlb_vector = __va(0x900);
unsigned long *itlb_vector = __va(0xa00);
+ printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler);
+ *itlb_vector = ((unsigned long)&itlb_miss_handler -
+ (unsigned long)itlb_vector) >> 2;
+
+ /* Soft ordering constraint to ensure that dtlb_vector is
+ * the last thing updated
+ */
+ barrier();
+
printk(KERN_INFO "dtlb_miss_handler %p\n", &dtlb_miss_handler);
*dtlb_vector = ((unsigned long)&dtlb_miss_handler -
(unsigned long)dtlb_vector) >> 2;
- printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler);
- *itlb_vector = ((unsigned long)&itlb_miss_handler -
- (unsigned long)itlb_vector) >> 2;
}
+ /* Soft ordering constraint to ensure that cache invalidation and
+ * TLB flush really happen _after_ code has been modified.
+ */
+ barrier();
+
/* Invalidate instruction caches after code modification */
mtspr(SPR_ICBIR, 0x900);
mtspr(SPR_ICBIR, 0xa00);