diff options
| author | Shaohui Xie <Shaohui.Xie@freescale.com> | 2012-07-17 15:18:31 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-07-26 08:09:53 -0500 |
| commit | e1bd5d8bc13f51c7c991f04255b3868e31933252 (patch) | |
| tree | 6d865cb7ebea4bd182812fbaf61011a34d3535b5 /arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | |
| parent | 771e6089e3638ea1e06700a9dc4660cd678e35bb (diff) | |
powerpc/85xx: P3041DS - change espi input-clock from 40MHz to 35MHz
Default CoreNet Coherency Bus (CCB) frequency on P3041 is 750MHz, but espi
cannot work at 40MHz with this CCB frequency, so we need to slow down the
clock rate of espi to 35MHz to make it work stable at the CCB frequency.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_85xx_l2ctlr.c')
0 files changed, 0 insertions, 0 deletions