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authorFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>2010-06-29 16:32:42 +0900
committerChris Metcalf <cmetcalf@tilera.com>2010-07-06 13:41:57 -0400
commit4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f (patch)
tree58bb13374c4ca02b2a89f63169af72303216f41a /arch/tile
parent0707ad30d10110aebc01a5a64fb63f4b32d20b73 (diff)
tile: remove homegrown L1_CACHE_ALIGN macro
Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/include/asm/cache.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
index c2b7dcfe532..ee597147e5c 100644
--- a/arch/tile/include/asm/cache.h
+++ b/arch/tile/include/asm/cache.h
@@ -20,7 +20,6 @@
/* bytes per L1 data cache line */
#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
/* bytes per L1 instruction cache line */
#define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()