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| author | Ingo Molnar <mingo@elte.hu> | 2009-03-13 05:54:43 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-13 05:54:43 +0100 |
| commit | 17d85bc7564571a1cce23ffdb2d2a33301876925 (patch) | |
| tree | 815bfc3a02e94303c7c834770bf2a17012c10bf8 /arch/x86/mm | |
| parent | d95c3578120e5bc4784069439f00ccb1b5f87717 (diff) | |
| parent | 041b62374c7fedc11a8a1eeda2868612d3d1436c (diff) | |
Merge commit 'v2.6.29-rc8' into cpus4096
Diffstat (limited to 'arch/x86/mm')
| -rw-r--r-- | arch/x86/mm/pageattr.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 8253bc97587..9c4294986af 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -522,6 +522,17 @@ static int split_large_page(pte_t *kpte, unsigned long address) * primary protection behavior: */ __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); + + /* + * Intel Atom errata AAH41 workaround. + * + * The real fix should be in hw or in a microcode update, but + * we also probabilistically try to reduce the window of having + * a large TLB mixed with 4K TLBs while instruction fetches are + * going on. + */ + __flush_tlb_all(); + base = NULL; out_unlock: |