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authorManuel Lauss <mano@roarinelk.homelinux.net>2009-03-25 17:49:30 +0100
committerRalf Baechle <ralf@linux-mips.org>2009-03-30 14:49:46 +0200
commit2f794d099da2f081de2fe19b289a3aa807f735fa (patch)
tree9d4065219b135c17c94a532fd8b4d51e49535f72 /arch
parent32647e0c1f63eead3e84d52b3edb8bc2f1fa2dd4 (diff)
MIPS: Alchemy: MIPS hazard workarounds are not required.
The Alchemy manuals state: "All pipeline hazards and dependencies are enforced by hardware interlocks so that any sequence of instructions is guaranteed to execute correctly. Therefore, it is not necessary to pad legacy MIPS hazards (such as load delay slots and coprocessor accesses) with NOPs." Run-tested on Au12x0, without any ill effects. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/hazards.h4
-rw-r--r--arch/mips/mm/tlbex.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 134e1fc8f4d..a12d971db4f 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do { \
: "=r" (tmp)); \
} while (0)
-#elif defined(CONFIG_CPU_MIPSR1)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
/*
* These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,7 +139,7 @@ do { \
} while (0)
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
- defined(CONFIG_CPU_R5500)
+ defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 122c9c12e75..0615b62efd6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -292,7 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R4300:
case CPU_5KC:
case CPU_TX49XX:
- case CPU_ALCHEMY:
case CPU_PR4450:
uasm_i_nop(p);
tlbw(p);
@@ -315,6 +314,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
+ case CPU_ALCHEMY:
tlbw(p);
break;