diff options
| author | Yuvaraj Kumar C D <yuvaraj.cd@gmail.com> | 2013-05-17 15:56:24 +0530 |
|---|---|---|
| committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2014-04-16 23:51:34 +0400 |
| commit | 6f7f0bd9ad62bda74b48a950418aa676b6884f2b (patch) | |
| tree | f4942f403eb0f6f9effad5cae821257f098bd862 /arch | |
| parent | 4c6484650554ca333492b7b4ed190a5c748cfd2b (diff) | |
ata: samsung: Rebase as per 3.10-rc1
This patchset integrate the SATA patches submitted by Vasanth Ananthan.
In addition to that SATA and SATA PHY driver will use common clock
framework API.
Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-sata.h | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-sata.h b/arch/arm/mach-exynos/include/mach/regs-sata.h deleted file mode 100644 index 80dd564eb32..00000000000 --- a/arch/arm/mach-exynos/include/mach/regs-sata.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - SATA PHY controller definition - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define EXYNOS5_SATA_RESET 0x4 -#define RESET_CMN_RST_N (1 << 1) -#define LINK_RESET 0xF0000 - -#define EXYNOS5_SATA_MODE0 0x10 - -#define EXYNOS5_SATA_CTRL0 0x14 -#define CTRL0_P0_PHY_CALIBRATED_SEL (1 << 9) -#define CTRL0_P0_PHY_CALIBRATED (1 << 8) - -#define EXYNOS5_SATA_PHSATA_CTRLM 0xE0 -#define PHCTRLM_REF_RATE (1 << 1) -#define PHCTRLM_HIGH_SPEED (1 << 0) - -#define EXYNOS5_SATA_PHSATA_STATM 0xF0 -#define PHSTATM_PLL_LOCKED (1 << 0) - -#define SATA_PHY_CON_RESET 0xF003F |