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author | Jon Medhurst <tixy@linaro.org> | 2014-04-15 11:46:14 +0100 |
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committer | Jon Medhurst <tixy@linaro.org> | 2014-04-15 11:46:14 +0100 |
commit | 87500fa128c96229f51325b88daea12e8367f8d8 (patch) | |
tree | b6ad6e86d28ed92884562cd2384237d0736c4107 /arch | |
parent | 46daf47ab930d6fbe7e5cbd49eb52b49dd58f640 (diff) | |
parent | eb63514d2340259f017bc48b7795744cb8aeaaf8 (diff) |
Merge branch 'tracking-armlt-mcpm' into integration-linaro-vexpress
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/kernel/setup.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1e8b030dbef..4a5e9430f16 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -273,6 +273,19 @@ static int cpu_has_aliasing_icache(unsigned int arch) int aliasing_icache; unsigned int id_reg, num_sets, line_size; +#ifdef CONFIG_BIG_LITTLE + /* + * We expect a combination of Cortex-A15 and Cortex-A7 cores. + * A7 = VIPT aliasing I-cache + * A15 = PIPT (non-aliasing) I-cache + * To cater for this discrepancy, let's assume aliasing I-cache + * all the time. This means unneeded extra work on the A15 but + * only ptrace is affected which is not performance critical. + */ + if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc0f0) + return 1; +#endif + /* PIPT caches never alias. */ if (icache_is_pipt()) return 0; |