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authorMatthew Garrett <mjg59@srcf.ucam.org>2005-07-29 14:03:39 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-29 15:01:15 -0700
commitb0825488a642cadcf39709961dde61440cb0731c (patch)
treecd73116cb0298a6333cbfda8ba2874b1ff180e05 /drivers/char/agp/intel-agp.c
parentb87a1e506115e7df4c6bfd266267ee0088cba3b7 (diff)
[PATCH] agp: restore APBASE after setting APSIZE
When leaving S3 state, the AGP bridge may not have all PCI configuration registers set in the same way as they were at boot. This should be fixed by pci_restore_state - however, the APBASE register cannot be set to conflict with the APSIZE register. If APSIZE is larger than it was before suspend, pci_restore_state will not restore APBASE correctly. The attached patch adds an extra item to the agp_bridge_data structure and uses it to store the value of APBASE. On resume, this is then written after APSIZE has been set. This patch only touches the path used for Intel chipsets without integrated graphics, and may need to be extended to work with the others. Without this patch, I get the symptoms described in bug 4921 - APBASE ends up overlapping various PCI devices, and as a result they fail to work after resume. Signed-off-by: Matthew Garrett <mjg59@srcf.ucam.org> Acked-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/char/agp/intel-agp.c')
-rw-r--r--drivers/char/agp/intel-agp.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 51266d6b4d7..1f7d415f432 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -1047,9 +1047,15 @@ static int intel_845_configure(void)
/* aperture size */
pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
- /* address to map to */
- pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
- agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ if (agp_bridge->apbase_config != 0) {
+ pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
+ agp_bridge->apbase_config);
+ } else {
+ /* address to map to */
+ pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ agp_bridge->apbase_config = temp;
+ }
/* attbase - aperture base */
pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);