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| author | Thierry Reding <thierry.reding@gmail.com> | 2013-11-18 16:11:35 +0100 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 18:44:00 +0200 |
| commit | 00c674e42c278e7af7b39b6c72dbbaa5e7ebd96c (patch) | |
| tree | 72308d5561ffefccd18e45524a6f27817e2271d1 /drivers/clk/tegra/clk-periph-gate.c | |
| parent | 480fe6f4cb35d1a3bd14c41736924a97f28346bb (diff) | |
clk: tegra: Fix clock rate computation
The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.
This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-periph-gate.c')
0 files changed, 0 insertions, 0 deletions