diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-04-03 17:40:44 +0300 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-04-04 16:10:59 -0600 |
| commit | fdcccbd804088eb96881c9f6532de04868f9dbc1 (patch) | |
| tree | cdec0c69139e1a8a4f6577c8bc3c91e7ebcbf22e /drivers/clk/tegra/clk-periph-gate.c | |
| parent | a26a029893096204f08a3ff5e262f99e1a75e273 (diff) | |
clk: tegra: Workaround for Tegra114 MSENC problem
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-periph-gate.c')
| -rw-r--r-- | drivers/clk/tegra/clk-periph-gate.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index d87e1cece9f..bafee9895a2 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock); #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32)) +#define LVL2_CLK_GATE_OVRE 0x554 + /* Peripheral gate clock ops */ static int clk_periph_is_enabled(struct clk_hw *hw) { @@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw) } } + if (gate->flags & TEGRA_PERIPH_WAR_1005168) { + writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); + writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); + udelay(1); + writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); + } + spin_unlock_irqrestore(&periph_ref_lock, flags); return 0; |