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authorLee Jones <lee.jones@linaro.org>2013-08-08 10:38:15 +0100
committerLinus Walleij <linus.walleij@linaro.org>2013-09-26 11:05:22 +0200
commit0473b177c3dd5abdb2a7b54eec1921283928a17b (patch)
tree18626b5d66d634cce400a9d3ddd77f4e1a2bc3f7 /drivers/clk
parent970eb8fe135ed11e0805ceb0566a940d3eeccbca (diff)
clk: ux500: Remove BML8580 clock
There is no mention of the PRCMU_BML8580CLK in any of the Design Specifications for the chips supported in Mainline. In fact, where it is incorrectly used in the u8540 clock definition driver it would have the side effect of using the incorrect clock management address ([PRCM_BML8580CLK_MGT] 0x108 instead of the correct value 0x04C). Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ux500/u8540_clk.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
index f26258869de..20c8add90d1 100644
--- a/drivers/clk/ux500/u8540_clk.c
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -83,7 +83,7 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
clk_register_clkdev(clk, NULL, "lcd");
clk_register_clkdev(clk, "lcd", "mcde");
- clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BML8580CLK,
+ clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK,
CLK_IS_ROOT);
clk_register_clkdev(clk, NULL, "bml");