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authorVivek Gautam <gautam.vivek@samsung.com>2013-12-19 19:02:12 +0530
committerAndrey Konovalov <andrey.konovalov@linaro.org>2014-04-16 23:51:37 +0400
commite012d60207788e3269d32bf9836c498bde971cd0 (patch)
treee74b9eeb4e63f5ff06b6143bf9ab8f0d5449f889 /drivers/clk
parent97b0680d5b921cbb1a475254f9ca98c167b33772 (diff)
clk: exynos5420: Enable Gate for sclk_usbphy3*
sclk_usbphy3* are the operational clocks used by USB 3.0 PHY on exynos5420 platform, but the same are not handled by the phy-samsung-usb3 driver. So enable the gates for these sclk_usbphy3* for now to make USB 3.0 ports present on smdk5420 working. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index ab4f2f7d88e..79254587988 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -539,9 +539,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
- GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
+ GATE_TOP_SCLK_FSYS, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
- GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+ GATE_TOP_SCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",