diff options
| author | Tushar Behera <tushar.behera@linaro.org> | 2013-04-15 15:43:45 +0530 |
|---|---|---|
| committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2014-04-16 23:51:26 +0400 |
| commit | ed11dafe8bf7d39f6af4002189c97638e224da04 (patch) | |
| tree | f4ff234242445809c27bb09d507e2d047c4f6049 /drivers/clocksource | |
| parent | 777e9c92e77e752abdd8649f14b3899000282d5b (diff) | |
ARM: EXYNOS: Set arch_sys_counter as default clocksource
The Exynos 5250 includes an architected timer which is on core and
very cheap to read.
Enabling the architected timer can lead to a significant performance
improvement for timer sensitive workloads such as TCP/IP.
It turns out that both arch_sys_counter and mct-frc have a rating of
400. On bootup, arch_sys_counter is initialized first then the
clocksource changes to mct-frc when that initialises later on.
If the rating of mct-frc is reduced below 400, then arch_sys_counter
becomes the default.
Suggested-by: Steve Capper <steve.capper@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Diffstat (limited to 'drivers/clocksource')
| -rw-r--r-- | drivers/clocksource/exynos_mct.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 48f76bc05da..8cc5040a7bb 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -27,6 +27,8 @@ #include <asm/mach/time.h> +#include <plat/cpu.h> + #define EXYNOS4_MCTREG(x) (x) #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) @@ -198,6 +200,10 @@ static void __init exynos4_clocksource_init(void) { exynos4_mct_frc_start(0, 0); + if (soc_is_exynos5250()) { + mct_frc.rating = 399; + } + if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); } |