diff options
| author | Forrest Shi <b29237@freescale.com> | 2010-12-09 16:14:04 +0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2010-12-13 14:05:27 -0800 |
| commit | f3c677b997757326e1f29d33060719a6a5091950 (patch) | |
| tree | 3135e7ee4a04d5abd929cc863168c0c6a574e824 /drivers/dma/fsldma.c | |
| parent | c989a7fc139ec8975fdc230e2de42f3c4555880e (diff) | |
fsldma: fix issue of slow dma
Fixed fsl dma slow issue by initializing dma mode register with
bandwidth control. It boosts dma performance and should works
with 85xx board.
Signed-off-by: Forrest Shi <b29237@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/fsldma.c')
| -rw-r--r-- | drivers/dma/fsldma.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 286c3ac6bdc..e5e172d2169 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -50,9 +50,11 @@ static void dma_init(struct fsldma_chan *chan) * EIE - Error interrupt enable * EOSIE - End of segments interrupt enable (basic mode) * EOLNIE - End of links interrupt enable + * BWC - Bandwidth sharing among channels */ - DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE - | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); + DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC + | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE + | FSL_DMA_MR_EOSIE, 32); break; case FSL_DMA_IP_83XX: /* Set the channel to below modes: |