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authorForrest Shi <b29237@freescale.com>2010-12-09 16:14:04 +0800
committerDan Williams <dan.j.williams@intel.com>2010-12-13 14:05:27 -0800
commitf3c677b997757326e1f29d33060719a6a5091950 (patch)
tree3135e7ee4a04d5abd929cc863168c0c6a574e824 /drivers/dma/fsldma.h
parentc989a7fc139ec8975fdc230e2de42f3c4555880e (diff)
fsldma: fix issue of slow dma
Fixed fsl dma slow issue by initializing dma mode register with bandwidth control. It boosts dma performance and should works with 85xx board. Signed-off-by: Forrest Shi <b29237@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/fsldma.h')
-rw-r--r--drivers/dma/fsldma.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index cb4d6ff5159..ba9f403c0fb 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
*
* Author:
* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
@@ -36,6 +36,13 @@
#define FSL_DMA_MR_DAHE 0x00002000
#define FSL_DMA_MR_SAHE 0x00001000
+/*
+ * Bandwidth/pause control determines how many bytes a given
+ * channel is allowed to transfer before the DMA engine pauses
+ * the current channel and switches to the next channel
+ */
+#define FSL_DMA_MR_BWC 0x08000000
+
/* Special MR definition for MPC8349 */
#define FSL_DMA_MR_EOTIE 0x00000080
#define FSL_DMA_MR_PRC_RM 0x00000800