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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-04-04 15:13:42 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-04-18 09:43:19 +0200
commita6f429a5a2f6ae0e1e8df2493884f9a881486d81 (patch)
tree467d802032ad600e98201ff1756cfc15e9d446da /drivers/gpu/drm/i915/i915_gem_tiling.c
parenta65c2fcd00518b7339d72e08e6b2b4261fbcc22a (diff)
drm/i915: Configure GAM_ECOCHK appropriatly for Gen7
IVB and HSW use different encodings for the PPGTT cacheability bits in the GAM_ECOCHK register. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
0 files changed, 0 insertions, 0 deletions