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authorBen Widawsky <benjamin.widawsky@intel.com>2013-12-12 17:26:03 -0800
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-12-13 17:51:24 +0100
commit63801f211c6eeb6def635ceee39d165e00fd6e09 (patch)
tree46b597f444fb8aecec8647da2eea4fdf805e6d65 /drivers/gpu/drm/i915/intel_bios.h
parenta3564d2b5236b73bceb271f482965d38cd9d8d8e (diff)
downloadlinaro-lsk-63801f211c6eeb6def635ceee39d165e00fd6e09.tar.gz
drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent
I stumbled on to some unimplemented errata. To be honest, I am not really sure of the impact, just that the docs say to do. No w/a name for this one. v2: v1 was a stale thing which should have never seen the light of day. (Haihao) Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_bios.h')
0 files changed, 0 insertions, 0 deletions