diff options
| author | Zhao Yakui <yakui.zhao@intel.com> | 2009-03-03 18:06:42 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-03-27 15:12:10 -0700 |
| commit | 6bcdcd9e3c09d133e3278edabebc314a2451b74a (patch) | |
| tree | 775a5bed00a3c02c8d2d07284421bd9ddf4b1a5e /drivers/gpu/drm/i915/intel_crt.c | |
| parent | ba01079c71559304771f9d741c9bbe8b2eac22a2 (diff) | |
drm/i915: Sync mode_valid/mode_set with intel video driver
This covers:
Limit CRT DAC speed better.
and also clears the border color in case it's set to some garbage, which would
fix ugly outlines in the blank regions of the CRT.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
[anholt: replaced *drm_dev with *dev]
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_crt.c | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index dcaed3466e8..e58defa247d 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -64,11 +64,21 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode) static int intel_crt_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { + struct drm_device *dev = connector->dev; + + int max_clock = 0; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; - if (mode->clock > 400000 || mode->clock < 25000) - return MODE_CLOCK_RANGE; + if (mode->clock < 25000) + return MODE_CLOCK_LOW; + + if (!IS_I9XX(dev)) + max_clock = 350000; + else + max_clock = 400000; + if (mode->clock > max_clock) + return MODE_CLOCK_HIGH; return MODE_OK; } @@ -113,10 +123,13 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) adpa |= ADPA_VSYNC_ACTIVE_HIGH; - if (intel_crtc->pipe == 0) + if (intel_crtc->pipe == 0) { adpa |= ADPA_PIPE_A_SELECT; - else + I915_WRITE(BCLRPAT_A, 0); + } else { adpa |= ADPA_PIPE_B_SELECT; + I915_WRITE(BCLRPAT_B, 0); + } I915_WRITE(ADPA, adpa); } |