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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-12-10 14:06:45 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-12-10 20:04:58 +0100
commit8212d56329b223a106d3d4f7dda95f571b1fa044 (patch)
tree8e02d693966d5adbb490bd31a1c266294ec23650 /drivers/gpu/drm/i915/intel_display.c
parentfff6386766fc846f19d5628878a4638fa7ece0a4 (diff)
drm/i915: Move VLV PHY CRI clock enable into intel_init_dpio()
The CRI clock is related to the display PHY, so the setup belongs in intel_init_dpio(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 596ad09f0e5..10a803f6936 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1367,6 +1367,10 @@ static void intel_init_dpio(struct drm_device *dev)
if (!IS_VALLEYVIEW(dev))
return;
+ /* Enable the CRI clock source so we can get at the display */
+ I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+ DPLL_INTEGRATED_CRI_CLK_VLV);
+
DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
/*
* From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
@@ -10788,17 +10792,10 @@ static void i915_disable_vga(struct drm_device *dev)
void intel_modeset_init_hw(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
intel_prepare_ddi(dev);
intel_init_clock_gating(dev);
- /* Enable the CRI clock source so we can get at the display */
- if (IS_VALLEYVIEW(dev))
- I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
- DPLL_INTEGRATED_CRI_CLK_VLV);
-
intel_init_dpio(dev);
mutex_lock(&dev->struct_mutex);