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authorBen Widawsky <benjamin.widawsky@intel.com>2013-11-02 21:07:40 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-08 18:09:55 +0100
commit50ed5fbd9dcd6e8531cc34bb2a1e2c01ea00697d (patch)
treebf46c3b4b591f1f39faf69f5478554f8000d5fd4 /drivers/gpu/drm/i915/intel_pm.c
parent6bbfa1c5b6851e6ed784a550992813950710ab3b (diff)
drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority
GEN8 also needs this workaround. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> [danvet: Add a generic comment that we need to recheck all these w/a.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9496abd76d..b05f141a5a0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5188,6 +5188,12 @@ static void gen8_init_clock_gating(struct drm_device *dev)
I915_WRITE(WM3_LP_ILK, 0);
I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0);
+
+ /* FIXME(BDW): Check all the w/a, some might only apply to
+ * pre-production hw. */
+
+ /* WaSwitchSolVfFArbitrationPriority */
+ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
}
static void haswell_init_clock_gating(struct drm_device *dev)