diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-11-14 20:24:35 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-11-18 14:55:37 +1000 |
| commit | 16790569eddf4d406a16a65f4750f405fa669c52 (patch) | |
| tree | d43fd3e94ecb0a7548863ffbe9b7aa4ad5cdfaff /drivers/gpu/drm/radeon/r600d.h | |
| parent | 0143832cc96d0bf78486297aad5c8fb2c2ead02a (diff) | |
drm/radeon/kms: fix and unify tiled buffer alignment checking for r6xx/7xx
Tiled buffers have the same alignment requirements regardless of
whether the surface is for db, cb, or textures. Previously, the
calculations where inconsistent for each buffer type.
- Unify the alignment calculations in a common function
- Standardize the alignment units (pixels for pitch/height/depth,
bytes for base)
- properly check the buffer base alignments
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 966a793e225..bff4dc4f410 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h @@ -51,6 +51,12 @@ #define PTE_READABLE (1 << 5) #define PTE_WRITEABLE (1 << 6) +/* tiling bits */ +#define ARRAY_LINEAR_GENERAL 0x00000000 +#define ARRAY_LINEAR_ALIGNED 0x00000001 +#define ARRAY_1D_TILED_THIN1 0x00000002 +#define ARRAY_2D_TILED_THIN1 0x00000004 + /* Registers */ #define ARB_POP 0x2418 #define ENABLE_TC128 (1 << 30) |