diff options
author | Dave Airlie <airlied@redhat.com> | 2013-12-23 10:43:42 +1000 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2013-12-23 10:43:42 +1000 |
commit | 785e15ecefbfe8ea311ae320fdacd482a84b3cc3 (patch) | |
tree | 46ed5413424d3893bf6236684e597388f68ad5ad /drivers/gpu/drm/tegra/mipi-phy.c | |
parent | e6c3dcdea6c95e4de98681a6cb3124ed8eacd5d6 (diff) | |
parent | 81239c6f7972d4909a6862d08ed1d2943983ffd4 (diff) |
Merge tag 'drm/for-3.14-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.14-rc1
This series of changes brings DRM panel support as well as initial code
to register DSI hosts and peripherals and bind them to DSI drivers. The
panel and DSI code are both used by the simple panel driver.
The Tegra-specific changes build on top of this work to add support for
various panels found on Tegra boards. New drivers enable the DSI host
found on Tegra114 and a special hardware block that calibrates the pads
used for DSI and CSI. The host1x and the display controller drivers gain
basic Tegra124 support. To round of the new features, the DRM driver now
sports a very simple PRIME implementation.
In addition there are various improvements such as the host1x API being
exported so that client drivers (like the Tegra DRM driver) can be built
as modules. HDMI now does better power management and legacy FBDEV can
now be disabled via Kconfig (though it's still enabled by default). A
few sparse warnings have been squashed and various parts of the code
have become more robust.
* tag 'drm/for-3.14-rc1' of git://anongit.freedesktop.org/tegra/linux: (121 commits)
drm/tegra: fix compile w/ CONFIG_DYNAMIC_DEBUG
drm/tegra: Add PRIME support
drm/tegra: Relocate some output-specific code
drm/tegra: Add Tegra124 DC support
drm/tegra: Fix small leak on error in tegra_fb_alloc()
drm/tegra: Make legacy fbdev support optional
drm/tegra: Sort reverse-dependencies alphabetically
drm/tegra: Fix return value check
drm/tegra: Add DSI support
drm/tegra: Disable outputs for power-saving
drm/tegra: Track HDMI enable state
drm/tegra: Fix HDMI audio frequency typo
drm/tegra: Do not export tegra_bo_ops
drm/tegra: Remove spurious blank line
drm/tegra: Increase compile test coverage
drm/tegra: Allow the driver to be built as a module
gpu: host1x: Add Tegra124 support
gpu: host1x: clk_round_rate() can return a zero upon error
gpu: host1x: Fix build warnings
gpu: host1x: Increase compile test coverage
...
Diffstat (limited to 'drivers/gpu/drm/tegra/mipi-phy.c')
-rw-r--r-- | drivers/gpu/drm/tegra/mipi-phy.c | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/mipi-phy.c b/drivers/gpu/drm/tegra/mipi-phy.c new file mode 100644 index 00000000000..e2c4aedaee7 --- /dev/null +++ b/drivers/gpu/drm/tegra/mipi-phy.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2013 NVIDIA Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include <linux/errno.h> +#include <linux/kernel.h> + +#include "mipi-phy.h" + +/* + * Default D-PHY timings based on MIPI D-PHY specification. Derived from + * the valid ranges specified in Section 5.9 of the D-PHY specification + * with minor adjustments. + */ +int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, + unsigned long period) +{ + timing->clkmiss = 0; + timing->clkpost = 70 + 52 * period; + timing->clkpre = 8; + timing->clkprepare = 65; + timing->clksettle = 95; + timing->clktermen = 0; + timing->clktrail = 80; + timing->clkzero = 260; + timing->dtermen = 0; + timing->eot = 0; + timing->hsexit = 120; + timing->hsprepare = 65 + 5 * period; + timing->hszero = 145 + 5 * period; + timing->hssettle = 85 + 6 * period; + timing->hsskip = 40; + timing->hstrail = max(8 * period, 60 + 4 * period); + timing->init = 100000; + timing->lpx = 60; + timing->taget = 5 * timing->lpx; + timing->tago = 4 * timing->lpx; + timing->tasure = 2 * timing->lpx; + timing->wakeup = 1000000; + + return 0; +} + +/* + * Validate D-PHY timing according to MIPI Alliance Specification for D-PHY, + * Section 5.9 "Global Operation Timing Parameters". + */ +int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing, + unsigned long period) +{ + if (timing->clkmiss > 60) + return -EINVAL; + + if (timing->clkpost < (60 + 52 * period)) + return -EINVAL; + + if (timing->clkpre < 8) + return -EINVAL; + + if (timing->clkprepare < 38 || timing->clkprepare > 95) + return -EINVAL; + + if (timing->clksettle < 95 || timing->clksettle > 300) + return -EINVAL; + + if (timing->clktermen > 38) + return -EINVAL; + + if (timing->clktrail < 60) + return -EINVAL; + + if (timing->clkprepare + timing->clkzero < 300) + return -EINVAL; + + if (timing->dtermen > 35 + 4 * period) + return -EINVAL; + + if (timing->eot > 105 + 12 * period) + return -EINVAL; + + if (timing->hsexit < 100) + return -EINVAL; + + if (timing->hsprepare < 40 + 4 * period || + timing->hsprepare > 85 + 6 * period) + return -EINVAL; + + if (timing->hsprepare + timing->hszero < 145 + 10 * period) + return -EINVAL; + + if ((timing->hssettle < 85 + 6 * period) || + (timing->hssettle > 145 + 10 * period)) + return -EINVAL; + + if (timing->hsskip < 40 || timing->hsskip > 55 + 4 * period) + return -EINVAL; + + if (timing->hstrail < max(8 * period, 60 + 4 * period)) + return -EINVAL; + + if (timing->init < 100000) + return -EINVAL; + + if (timing->lpx < 50) + return -EINVAL; + + if (timing->taget != 5 * timing->lpx) + return -EINVAL; + + if (timing->tago != 4 * timing->lpx) + return -EINVAL; + + if (timing->tasure < timing->lpx || timing->tasure > 2 * timing->lpx) + return -EINVAL; + + if (timing->wakeup < 1000000) + return -EINVAL; + + return 0; +} |