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authorBen Widawsky <benjamin.widawsky@intel.com>2013-11-02 21:07:52 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-08 18:10:02 +0100
commit6edee7f3e7daab105b33148b49c74a8f881d172e (patch)
treec299ac3895eaf17185c9c7901fd289de881a27db /drivers/gpu/drm/ttm
parente3c3357863db7cb8e847b3adff5b6be94cecde82 (diff)
drm/i915/bdw: Create a separate BDW rps enable
This is mostly what we have for HSW with the exceptions of: no writes: GEN6_RC1_WAKE_RATE_LIMIT GEN6_RC6pp_WAKE_RATE_LIMIT GEN6_RC1e_THRESHOLD GEN6_RC6p_THRESHOLD GEN6_RC6pp_THRESHOLD GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s Don't try to overclock, or program ring/IA frequency tables since we don't quite have sufficient docs yet. NOTE: These values do not reflect the changes made recently by Chris. Since we have no evidence yet what the proper way to tweak for this platform is, I think it is good to go, and can be optimized by Chris, or whomever, later. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> [danvet: Drop spurious hunk and drop TODO - having per-platform rps register frobbing code is in my opinion preferred, now that all the infrastructure functions are extracted.] Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/ttm')
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